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NJU7505
PPRELIMINARY

BAND PASS FILTER FOR AUDIO SPECTRUM ANALYZER DISPLAY
s GENERAL DESCRIPTION The NJU7505 is a band pass filter for audio spectrum analyzer display. It consists of high and low band pass filters, CR oscillation circuit, control circuit and DC transfer circuit. Each band pass filter using the switched capacitor filter technology operates at the shared time by 5 bands which filter constant is switched by the internal clock. Therefore, the audio signal shared of 5 bands is output from a serial output terminal. The 10 band version using the double by the cascade connection is prepared. s PACKAGE OUTLINE

NJU7505XD

NJU7505XM

s FEATURES q BPF for the audio spectrum analyzer display of the 5 bands q 10 bands extension is available by the cascade connection (Version of A: For 5-band application by the single) (Version of B: For 10-band application by the double) q BPF using the switched capacitor filter technology q CR oscillation circuit on chip (External clock input is available) q Power-on initialization circuit on chip (External reset input is available) q C-MOS Technology q Package Outline DIP8, DMP8

s PIN CONFIGURATION

OSC1 OSC2 RST/CLKO RD

1 2 3 4

5 6 7 8

VDD AIN AOUT VSS

s BLOCK DIAGRAM
Audi o Signal RST/CLKO RD Control Signa Crock Signal

OSC1 OSC2

OSC
f OSC f OSC/16

Control Circuit
f OSC/4
iH iL RL RH

Power-on Initialize
H L

BPF High Band
AIN

High Band Peak Detector
Lev el Shifter & Out Put BUF
AOUT

Input BUF

LPF
BPF Low Band Low Band Peak Detector

VDD

VDD

AGND

VSS

VSS

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NJU7505
s TERMINAL DESCRIPTION NO. 1 2 3 4 5 8 6 7 FUNCTION External Resistor connecting terminal. External Resistor connecting terminal or External clock input terminal. Both as Reset input terminal RST/CLKO and the clock of (2/3)*fosc output terminal. RD Trigger signal for reading-out the AOUT of each band output terminal. VSS GND 0V Positive power supply +5.0 V VDD AOUT Peak voltage of each band output terminal. AIN Audio signal input terminal. SYMBOL OSC1 OSC2

s VERSION LINEUP AND PEAK FREQUENCY The NJU7505 prepares two version of A and B which are different of the peak frequency of each bands. The version of A is recommended for the 5 bands application using the single and the version of B is recommended for the 10 bands using the double by the cascade connection, however, the version of A can be used for the 10 bands using the double and the version of B can be used for the 5 bands using the single. Peak Frequency ( Hz ) Using the single Using the double Version of A Version of B Version of A Version of B 12k 18k 12k 18k 8k 12k 3.5k 5.3k 3.5k 5.3k 2.3k 3.5k 1k 1.5k 1k 1.5k 670 1k 250 375 250 375 165 250 63 95 63 95 * 63 42

Band f1a f1b f2a f2b f3a f3b f4a f4b f5a f5b

Note) The bands of f1a, f2a, ... f5a correspond to the master side and the bands of f1b, f2b, ... f5b correspond to the slave side at the cascade connection of the double. Note) It may not be output along the expectation at the peak frequency of * marking, since the sampling time is not enough. The example of using the single The example of using the double

OSC1

AOUT

f 1a to f5a

OSC1

AOUT

f 1a to f5a

OSC1

AOUT

f 1b to f5b

NJU7505
f OSC OSC2 f OSC

NJU7505 Master
2/3 * fOSC RST/CLK0

NJU7505 Slave
OSC2

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NJU7505
s FUNCTIONAL DESCRIPTION q Interface to external controller The example of the interface between the NJU7505 and the external controller is shown below; (1) Example of the interface to the external controller ( Using the single ) After the RST signal from the external controller is input and then the internal circuit is initialized, each band data is output as shown below timing chart; Since the RD signal is output before each band is switched, the external controller is to count the number of the RD signal and is to recognize the status of the band and is to read the output data from the AOUT terminal through the external A/D converter. The output type of the external controller connected to the RST/CLK0 terminal as the RST input should be the N-channel and open-drain type or the diode should be connected between the RST/CLK0 terminal and the output terminal of the external controller, so that the voltage of the RST/CLKO terminal is not gotten over the VSS level.

A IN OSC1

NJU7505
A/D CONVERTER A OUT

OSC2

fOSC

VSS RST/CLKO RD

COM

3*214 / fO SC A OUT RD RST f1 f1 f2 f2 f3 f3 f5 f5 f1 f1 f2 f2 f4 f4 f3 f3 f1 f1 f1 f2 f2 f3

Since the RD signal is output before 256/fOSC of each band switched, the output data should be read out within the limited time as shown right;
256 / fosc A OUT RD Available Period of Read-out 8 / fosc

If the RST signal which pulse width is more than 4/fOSC is input, the internal circuit is initialized and the data of f1 band is output from the AOUT terminal after 52/fOSC of the rise edge of the RST signal.

A OUT

fn

f1

4/ fosc[MIN] 52/ fosc RST

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NJU7505
(2) Example of the interface to the external controller (Using the double) The 10 bands application is available using the cascade connection of the double NJU7505 as shown blow. After the RST signals from the external controller are input to each of the master and the slave of the NJU7505 and then each internal circuit is initialized, each band data is output as shown below timing chart; Since the RD signals are output from the master and the slave before each band is switched, the external controller is to count the number of the RD signals and is to Lognize the status of the band and is to read the output data from each AOUT terminals through the external A/D converter. The master clock for the slave is provided with the output signal from the RST/CLK0 terminal of the master. The master clock for the slave is stopped when the RST signal is input from the external controller to the master, so that the RST/CLK0 terminal of the master is used both as the RST input of the master and the master clock for the slave. The output type of the external controller connected to each RST/CLK0 terminal as the RST input should be the N-channel and open-drain type or the diode's should be connected between each RST/CLK0 terminal and the output terminals of the external controller, so that the voltage of each RST/CLKO terminal is not gotten over the VSS level.

A IN

A IN OSC1 OSC2

A/D CONVERTER

NJU7505 A OUT Slave

NJU7505 OSC2 Master
A OUT VSS

RST/CLKO

RD

RST/CLKO

RD

COM

Master
A OUT RD RST f1 f1 f2 f2

3*214 / fO SC f3 f3 f5 f5 f1 f1 f2 f2 f4 f4 f3 f3 f1 f1 f2 f2 f3 f3 f1 f1 f2

Slave
A OUT f1 f1 RD RST

3*214 / fO * 3/2 SC f2 f2

f3 f3

f5 f5

f1 f1

f2 f2

f4 f4

f3 f3

f1 f1

f2

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NJU7505
Since each RD signal of the master and the slave is output before 256/fOSC (256/fOSC*3/2) of each band switched, the output data should be read out within the limited time as shown right; * The "( )" is corresponded to the slave.

256 / fosc (256/ fosc*3/2) A OUT RD Available Period of Read-out 8 / fosc (8/ fosc*3/2)

If the RST signal which pulse width is more than 4/fOSC is input to the master, the internal circuit is initialized and the data of f1 band is output from the AOUT terminal of the master after 52/fOSC of the rise edge of the RST signal. The RST signal for the slave should be set to "L" level while the RST signal for the master is "L" level and should keep "L" level more than 6/fOSC. So the slave operates as same as the master after 78/fOSC of the rise edge of the RST signal for the slave.

A OUT
(Master)

fn

f1

4/fosc[MIN] RST
(Master)

52/ fsoc

RST
(Slave)

6/fosc[MIN] A OUT
(Slave)

78/ fsoc
f 1'

f n'

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NJU7505
s ABSOLUTE MAXIMUM RATINGS PARAMETER Supply Voltage Input Voltage SYMBOL VDD VIN VIO VOUT PD RATINGS -0.3 to +7 -0.3 to VDD+0.3 -0.3 to 0 -0.3 to VDD+0.3 500(DIP), 300(DMP) -30 to 85 -55 to 125 UNIT V V V mW C C 5 3, 6 (Ta=25C) NOTE

Output Voltage Power Dissipation Operating Topr Temperature Storage Temperature Tstg

Note 1) If the IC are used on condition above the absolute maximum ratings, the IC may be destroyed. Using the IC within electric characteristic conditions will cause malfunction and poor reliability. Note 2) All voltage values are specified as VSS = 0V. Note 3) When the voltage of the RST/CLKO terminal is gotten over the VSS level, the diode should be connected between the RST/CLK0 terminal and the external. Note 4) Decoupling capacitor should be connected between the VDD terminal and the VSS due to the stabilization of the operation. Note 5) Applied to the AIN or the OSC2 terminals. Note 6) Applied to the RST/CLKO terminal. s ELECTRICAL CHARACTERISTICS DC CHARACTERISTICS PARAMETER Operating Voltage Operating Current SYMBOL VDD IDD IIL1 IIH1 IIL2 VILC VIHC VOL1 VOH1 VOL2 VOH2 VOS CONDITITONS

(VDD=5V, VSS= 0V, Ta=25C)

MIN TYP MAX UNIT NOTE 4.5 5.0 6.0 V VDD TERMINAL 6.0 12 mA VIL1=0V -0.1 -0.05 -0.033 Input Leak Current 1 AIN TERMINAL mA VIH1=5V 0.033 0.05 0.1 Input Leak Current 2 RST/CLKO TERMINAL VIH2=0V -0.2 -0.1 -0.05 mA External Clock 0 1.5 OSC2 TERMINAL V Input Voltage 3.5 5.0 IOL1=100A 0 0.5 V Output Voltage 1 RD TERMINAL 4.5 5.0 IOH1=-100A RST/CLKO IOL1=100A 0 0.5 V Output Voltage 2 TERMINAL 4.25 4.5 4.75 IOH1=-5A Output Offset Voltage AOUT TERMINAL AIN:OPEN 300 mV 26.0 dB 7,8,9 AOUT TERMINAL Sine Wave Input BPF Output Voltage VOUT fIN=f1 to f5 VIN=200mVp-p 3.5 V 7,8 Note 7) This specification is tested on condition of fCLK=400KHz (The external clock is input to the OSC2 terminal through the capacitor for AC coupling. Note 8) Each input frequency of f1 to f5 is referred to the table of the " VERSION LINEUP AND PEAK FREQUENCY ". Note 9) This specification is calculated from " VOUT / VIN ".

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NJU7505
s AC CHARACTERISTICS PARAMETER Oscillation Clock Freq SYMBOL CONDITIONS fOSC RST/CLKO Terminal VDD=5V RST/CLKO Terminal VILC=0V External Clock Frequency fCLK VIHC=VDD Master RD Pulse Width tPWRD RD Terminal Slave Master RST Pulse Width tPWRS RST/CLKO Terminal Slave RST Rise/Fall Time tr, tf RST/CLKO Terminal Note 10) The example for the CR Oscillation RT: 13K(2%) CT: 220pF(5%) 4/fOSC 4/fCLK 6/fOSC 6/fCLK 100 ( VDD=4.5 to 6.0V, VSS=0V, Ta=25C) MIN 360 TYP 400 400 8/fOSC 8/fCLK 12/fOS
C

MAX 440 800

UNIT NOTE KHz 10 KHz 11

s

12

12/fCLK s nA 13 13

OSC1 RT OSC2 CT

*The oscillation clock frequency is calculated from the output frequency of the RST/CLK0 terminal by 3/2.

VSS

Note 11) The example for the external clock input
Open OSC1

The input signal for the OSC2 terminal should be the condition of the pulse of DUTY50%10%. * The oscillation clock frequency is calculated from the output frequency of the RST/CLK0 terminal by 3/2.

Oscillator

OSC2

Note 12) The output wave form of the RD terminal.
0.8VDD 0.8VDD

tPWRD

Note 13) The input wave form of the RST terminal.
tf 0.8VDD 0.2VDD TPWRS tr 0.8V DD 0.2VDD

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NJU7505
s APPLICATION CIRCUIT (1)

AUDIO IN

AUDIO IN

Lch

Rch

AUDIO OUT

AUDIO OUT

RESONANCE CERCUIT

NJU7305

RESONANCE CERCUIT

*1 *2 ATT. A IN OSC1 13K OSC2

NJU7505
VSS RST/CLKO RD

220pF

AOUT

*3

A/D

COM

DISPLAY DRIVER

DISPLAY

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NJU7505
s APPLICATION CIRCUIT (2)

AUDIO IN

AUDIO IN

Lch

Rch

AUDIO OUT

AUDIO OUT

RESONANCE CERCUIT

NJU7305

RESONANCE CERCUIT

ATT. A IN *2

*1

ATT. *2 A IN OSC1 13K

NJU7505

OSC2

NJU7505

OSC2 220pF
VSS

RD

RST/CLKO

RST/CLKO

RD

AOUT

*3

*3

AOUT

A/D

A/D

COM

DISPLAY DRIVER

DISPLAY

[CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights

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