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5 4 3 2 1
VER : 1A
BOM P/N Description ZQ9 SYSTEM BLOCK DIAGRAM
D D
Channel B
64Mb * 16 *4 pc
P22
Arrandale ATI-Park
rPGA 989 VRAM DDRIII EXT_HDMI
Dual Channel DDR III P4, 5, 6, 7 PCI-E x16 512MB
DDRIII-SODIMM1
800/1066 MHZ IMC GFX
DDRIII-SODIMM2 EXT_CRT
P14,15
CRT Con.
EXT_LVDS P23
P16, 17, 18, 21, 22, 23
FDI DMI
X'TAL SLG8LV595 DMI(x4)
14.318MHz CLOCK USB-8
LVDS/CCD/MIC
INT_CRT
GENERATOR P3 FDI DMI Con.
INT_LVDS Int. MIC P23
CLK
Display
C C
SATA 0
SATA - HDD
P28 INT_HDMI PS8101
SATA
LS P24 HDMI Con.
SATA - ODD SATA 1
P28 EXT_HDMI P24
PCIE-6
PCI-E x1
USB Port USB-1 MINI CARD
USB Ibex Peak-M USB-13
P33 WLAN
P27
USB-3/9/11 PCH
USB/B Con. P33 P8, 9, 10, 11, 12, 13
(USB Port x2) PCIE-1 BRM 57780
RJ45
USB-4
GIGA LAN P26
Bluetooth Con. X'TAL P26
32.768KHz
P33
X'TAL
B 25MHz B
Cardreader AU6437-GBL USB-12 X'TAL 25MHz
P31
Cardreader control
P31
P9 BATTERY RTC
Azalia SPI SPI ROM
IHDA
P9
LPC
ISL88731A UP6111AQDD ISL62881HRZ-T
LPC Batery Charger P36 +1.05V P39 +VGFX_AXG P41
Int. MIC ALC272X NPCE781 X'TAL RT8206B RT8207A HPA00835RTER
AUDIO CODEC P30 EC P37 32.768KHz 3V/5V P37 +1.5V_SUS P40 +1.8V P43
ADP3212 MAX8792ETD+T Discharger
CPU core P38 +VGPU_CORE P42 P43
BOM Option Table
GMT 1453L amp Touch Pad
A MIC JACK P29 A
P30 Board Con. RT9018A Thermal Protection
Reference Description
P34 +1V P44 P44
IV@ for UMA only SKU
for Discrete Graphic only SKU Speaker W25X40BVSSIG
EV@
P30 SPI FLASH P35
for different VRAM parts K/B Con. Fan Driver Quanta Computer Inc.
VRAM@
HP P30 P34 (PWM Type) P34
* do not stuff PROJECT : ZQ9
Size Document Number Rev
1A
Block Diagram
Date: Tuesday, June 22, 2010 Sheet 1 of 45
5 4 3 2 1
1 2 3 4 5 6 7 8
GPU PWR CTRL Option 1 (Default/ VDDR3 before VDDC)
+3.3V VIN VIN +1.5V +1.5V_SUS +1.8V +5V
VDDR3 +3V_D VDDC PG_GPUIO_EN VDDCI PG_1V_EN +1V (DP PLL PWR) PG_1.5V_EN VDDR1 PG_1.5V_EN VDDR4 PG_1.5V_EN BJT dGPU_PWROK MOS
dGPU_VRON dGPU_PWR_EN#
MOS (AO3413) ISL6264 ISL62872 G9334ADJ & MOS MOS (AO4710) MOS (AO6402) AO3413
P22 P44 P45 P47 P43 P43 P22 P22
A
+3_D (0.5A) +VGPU_CORE (20A) +VGPU_IO (4.5A) +1V (3A) +1.5V_GPU (10A) +1.8V_GPU (3A) +5_GPU A
GPU PWR CTRL Option 2 (VDDR3 after VDDR1)
VIN VIN +1.5V +1.5V_SUS +3.3V +1.8V +5V
VDDC PG_GPUIO_EN VDDCI PG_1V_EN +1V (DP PLL PWR) PG_1.5V_EN VDDR1 +1.5V_GPU VDDR3 +3V_D VDDR4 PG_1.5V_EN BJT dGPU_PWROK MOS
dGPU_VRON dGPU_PWR_EN#
ISL6264 ISL62872 G9334ADJ & MOS MOS (AO4710) MOS (AO3413) MOS (AO6402) AO3413
P44 P45 P47 P43 P22 P43 P22 P22
+VGPU_CORE (20A) +VGPU_IO (4.5A) +1V (3A) +1.5V_GPU (10A) +3_D (0.5A) +1.8V_GPU (3A) +5_GPU
Thermal Follow Chart
Power States
CONTROL
POWER PLANE VOLTAGE DESCRIPTION ACTIVE IN
SIGNAL
B VIN +10V~+19V MAIN POWER ALWAYS ALWAYS B
+VCCRTC +3V~+3.3V RTC POWER ALWAYS ALWAYS NTC
Thermal
+3VPCU +3.3V EC POWER ALWAYS ALWAYS
Protection
+5VPCU +5V CHARGE POWER ALWAYS ALWAYS
+15V +15V CHARGE PUMP POWER ALWAYS ALWAYS
+3V_S5 +3.3V LAN/BT/CIR POWER S5_ON S0-S5 CPU 3V/5 V
H_ORICHOT# PM_THRMTRIP# SYS_SHDN#
CORE PWR
CPU WIRE-AND SYS PWR
+5V_S5 +5V USB POWER S5_ON S0-S5 H/W Throttling
+5V +5V HDD/ODD/Codec/TP/CRT/HDMI POWER MAINON S0
+3V +3.3V PCH/GPU/Peripheral component POWER MAINON S0
SML1ALERT#
+1.5VSUS +1.5V CPU/SODIMM CORE POWER SUSON S0-S3
PCH FAN Driver FAN
+0.75V_DDR_VTT +0.75V SODIMM Termination POWER MAINON S0
+VGFX_AXG variation Internal GPU POWER GFX_ON S0
SM-Bus
+1.8V +1.8V CPU/PCH/Braidwood POWER MAINON S0
C C
+1.5V +1.5V MINI CARD/NEW CARD POWER MAINON S0
EC
+1.1V_VTT +1.05V or +1.1V CPU VTT POWER MAINON S0 CPUFAN#
+1.05V +1.05V PCH CORE POWER MAINON S0
+VCC_CORE variation CPU CORE POWER VRON S0
LCDVCC +3.3V LCD POWER LVDS_VDDEN S0
+5V_GPU +5V SWITCHABLE PWM IC POWER dGPU_PWR_EN# Discrete enable
+GPU_CORE +0.9V~+1.1V GPU CORE POWER +3V_D Discrete enable
+GPU_IO +0.9V~+1.1V GPU I/O POWER PG_GPUIO_EN Discrete enable
+1.5V_GPU +1.5V VRAM CORE POWER PG_1.5V_EN Discrete enable
+1.8V_GPU +1.8V GPU_CRE/LVDS/PLL POWER +1.5V_GPU Discrete enable
+1V +1V DP/PEG POWER PG_1V_EN Discrete enable
D D
Quanta Computer Inc.
PROJECT : ZQ9
Size Document Number Rev
1A
PWR Status & GPU PWR CRL & THRM
Date: Tuesday, June 22, 2010 Sheet 2 of 45
1 2 3 4 5 6 7 8
5 4 3 2 1
D
6/21 unstuff D
150mA(30mil)
+1.5V L50 *PBY160808T-181Y-N/2A/180ohm_6 +1.5V_CLK 80mA(20mil)
+VDDIO_CLK L48 PBY160808T/2A/180ohm_6 +1.05V
C243 C627 C246 6/21 add for 3V CLK gen
C613 C244 C607 C609
.1u/16V_4 .1u/16V_4 .1u/16V_4
R565 .1u/16V_4 .1u/16V_4 10u/Y5V_8 10u/Y5V_8
0_6 U20
Place each 0.1uF cap as close as
1 VDD_DOT possible to each VDD IO pin. Place
17 VDD_SRC VDD_SRC_I/O 15 the 10uF caps on the VDD_IO plane.
24 VDD_CPU VDD_CPU_I/O 18
20mil 5 VDD_27
+3V L23 BLM18AG601SN1D/200mA/600ohm_6 +3V_CLK 29 3
VDD_REF DOT_96 CLK_BUF_DREFCLK <10>
DOT_96# 4 CLK_BUF_DREFCLK# <10>
CLK_SDATA 31
C238 C267 C251 CLK_SCLK SDA R448 *EV@33_4
32 SCL 27M 6 27M_CLK <17>
7 R447 *EV@33_4 27M_CLK_SS <17>
4.7u/10V_8 .1u/16V_4 .1u/16V_4 27M_SS C270 *EV@10p/50V_4
R455 33_4 CPU_SEL 30 10 5/13 add for cost down solution
<10> CLK_ICH_14M REF_0/CPU_SEL SRC_1/SATA CLK_BUF_DREFSSCLK <10>
SRC_1#/SATA# 11 CLK_BUF_DREFSSCLK# <10>
C614 33p/50V_4 13
SRC_2 CLK_BUF_PCIE_3GPLL <10>
C SRC_2# 14 CLK_BUF_PCIE_3GPLL# <10> C
XTAL_IN 28 6/21 change the order
Y6 XTAL_IN +3V
14.318MHz XTAL_OUT 27 16 R130 10K_4
XTAL_OUT *CPU_STOP#
C612 33p/50V_4 2 20
VSS_DOT CPU_1 TP23
8 VSS_27 CPU_1# 19 TP24
9 VSS_SATA CPU_0 23 CLK_BUF_BCLK <10>
12 VSS_SRC CPU_0# 22 CLK_BUF_BCLK# <10>
21 VSS_CPU
IDT: AL003197001 (ICS9LVS3197AKLFT) 26 25 CK_PWRGD_R
VSS_REF CKPWRGD/PD#
33
Realtek: AL000890000 (RTM890N-632-GRT) GND
Silego: AL000595000 (SLG8LV595VTR)
ICS9LRS3197AKLFT
+3V
CPU_CLK select SMBus
B
+1.05V
CLK Enable +3V B
R543
R545
2
R451 2.2K_4 1K/F_4
*10K_4
3 1 CLK_SDATA CLK_SDATA <14,15,27>
<10> ICH_SMBDATA
CK_PWRGD_R
CPU_SEL Q18
3
2N7002K Q19
2N7002K
R446 C617
+3V <38> VR_PWRGD_CK505# 2 R544
10K_4 *10p/50V/COG_4 100K/F_4
1
R542
2
2.2K_4
0 1
3 1 CLK_SCLK CLK_SCLK <14,15,27>
<10> ICH_SMBCLK
A CPU_SEL CPU0/1=133MHz CPU0/1=100MHz Q17 A
2N7002K
(default)
Quanta Computer Inc.
PROJECT : ZQ9
Size Document Number Rev
1A
Clock Generator
Date: Tuesday, June 22, 2010 Sheet 3 of 45
5 4 3 2 1
5 4 3 2 1
AUBURNDALE/CLARKSFIELD PROCESSOR (DMI,PEG,FDI) AUBURNDALE/CLARKSFIELD PROCESSOR (CLK,MISC,JTAG)
DPLL_REF_SSCLK and DPLL_REF_SSCLK# can be connected to GND on Arrandale
directly if motherboard only supports discrete graphics. If motherboard supports
integrated graphics but without eDP, these pins can also be connected to GND directly.
Processor Compensation Signals
U22A U22B T20
B26 R436 49.9/F_4 R444 20/F_4 H_COMP3 AT23
PEG_ICOMPI COMP3
A26 A16 CLK_CPU_BCLK <11>
PEG_ICOMPO BCLK
MISC
MISC
A24 B27 R442 20/F_4 H_COMP2 AT24 B16 CLK_CPU_BCLK# <11>
<8> DMI_TXN0 DMI_RX#[0] PEG_RCOMPO COMP2 BCLK#
C23 A25 R437 750/F_4
<8> DMI_TXN1 DMI_RX#[1] PEG_RBIAS R173 49.9/F_4 H_COMP1 T62 T21
CLOCKS
<8> DMI_TXN2 B22 PEG_RXN[0..15] <16> G16 AR30
DMI_RX#[2] PEG_RXN0 COMP1 BCLK_ITP T67
<8> DMI_TXN3 A21 K35 AT30
D DMI_RX#[3] PEG_RX#[0] PEG_RXN1 R440 49.9/F_4 H_COMP0 BCLK_ITP# D
J34 AT26
PEG_RX#[1] PEG_RXN2 COMP0
<8> DMI_TXP0 B24 J33 E16 CLK_PCIE_3GPLL <10>
DMI_RX[0] PEG_RX#[2] PEG_RXN3 PEG_CLK
<8> DMI_TXP1 D23 G35 D16 CLK_PCIE_3GPLL# <10>
DMI_RX[1] PEG_RX#[3] PEG_CLK#
DMI
DMI
B23 G32 PEG_RXN4 T10 AH24
<8> DMI_TXP2 DMI_RX[2] PEG_RX#[4] SKTOCC#
A22 F34 PEG_RXN5 A18 DPLL_REF_SSCLK_R R465 *IV@0_4 DPLL_REF_SSCLK <10>
<8> DMI_TXP3 DMI_RX[3] PEG_RX#[5] DPLL_REF_SSCLK
F31 PEG_RXN6 A17 DPLL_REF_SSCLK#_R R471 *IV@0_4 DPLL_REF_SSCLK# <10>
PEG_RX#[6] PEG_RXN7 H_CATERR# DPLL_REF_SSCLK# R472 0_4
D24 D35 AK14
<8> DMI_RXN0 DMI_TX#[0] PEG_RX#[7] Use reverse type CATERR#
THERMAL
THERMAL
G24 E33 PEG_RXN8 R463 0_4
<8> DMI_RXN1 DMI_TX#[1] PEG_RX#[8]
F23 C33 PEG_RXN9 Layout Note: Place
<8>
<8>
DMI_RXN2
DMI_RXN3 H23
DMI_TX#[2]
DMI_TX#[3]