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A B C D E

MODEL NAME : VAW00 ZZZ R1@ ZZZ GCER3@ ZZZ TRIR3@

PROJECT CODE : ANRVAW0000
PCB NO : LA-9104P (Thames XT ) PCB VAW00 LA-9104P LS-9101P/9102P/9103P PCB VAW00 LA-9104P LS-9101P/9102P/9103P GOLD A31 ! PCB VAW00 LA-9104P LS-9101P/9102P/9103P TRIPOD A31 !
DAZ0SZ00200 DAZ0SZ00201 DAZ0SZ00202
1
DA60000VV00 LA-9104P M/B 1

DA40001FO00 LS-9101P POWER BUTTON/B ZZZ HANNR3@ ZZZ ZDTR3@

DA40001FP00 LS-9102P USB/B
DA40001FQ00 LS-9103P TP BUTTON/B PCB VAW00 LA-9104P LS-9101P/9102P/9103P HANNSTARB A31 ! PCB VAW00 LA-9104P LS-9101P/9102P/9103P ZDT A31 !
DAZ0SZ00203 DAZ0SZ00204

Dell / Compal Confidential
2
Schematic Document 2

Intel Chief River
Ivy Bridge(BGA) + Panther Point
OAK 15" UMA/DIS AMD Thames XT
2012-08-22
3
Rev: 1.0 3

46@ : for 46 level
R1@ : R1 P/N i3R1@ : CPU i3-3217 1.8G DIS@ : Only for Discrete
@ : Nopop Component
R3@ : R3 P/N i3VOSR1@ : CPU i3-2365 1.4G TH@/THR1@ : Thames-XT
CONN@ : Connector Component
i5R1@ : CPU i5-3317 1.7G MS@/MSR1@ : Mars Pro
KB9012@ : ENE KB9012 Implemented
i7R1@ : CPU i7-3517 1.9G X76@ :
UMA@ : Only for UMA
CELR1@ : CPU Celeron 887 1.5G SPI-ROM & VRAM Group
EMC@ : EMI/ESD parts
PENR1@ : CPU Pentium 997 1.6G
GCLK@ : Green CLK implemented
4
GCLKUMA@ : Green CLK for UMA 4

GCLKDIS@ : Green CLK for DIS
XTAL@ : X'tal implemented Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/08/22 Deciphered Date 2013/08/31 Title

XTALDIS@ : X'tal with DIS implemented THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Size Document Number
Custom
Cover Page
LA-9104P
Rev
1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, August 29, 2012 Sheet 1 of 57
A B C D E
A B C D E

64M*16 128M*16 Fan Control CPU XDP
VRAM * 4 VRAM * 4 P.40 Conn. P.6
DDR3 P.30 DDR3 P.30 Intel
64M*16
64bit Ivy Bridge Memory Bus (DDR3)
1

AMD Dual Channel DDRIII-DIMM X2 1

VRAM * 4 PEG 2.0 x8
Processor BANK 0, 1, 2, 3, 4 ,5 ,6 ,7
DDR3 P.31 1.5V DDR3 1333 MHz P.11~12
Thames-XT
128M*16 64bit
17W DC
VRAM * 4 24-26 W P.24~29 8GB Max
DDR3 P.31 BGA 1023
AMD Thames XT, 128b, P.5~10

Radeon HD7670M,
P5500 FDI x8 DMI x4
1GB DDR3 (8-64Mx16), 100MHz 100MHz
2GB DDR3 (8-128Mx16) 2.7GT/s 5GB/s

SATA3.0 Port 0
LVDS SATA HDD Conn.
P.35
LVDS Conn.
P.21
Port 2 SATA ODD Conn.
HDMI P.35
2 HDMI Conn. 2
P.22
Intel
Panther Point
PCH HM76 USB 3.0 Port 1,2
USB 3.0 Conn. 1
P.36
Port 0,1 USB 3.0 Conn. 2
USB2.0
Port 2,3 USB 3.0 Conn. 3
PCI-E x1
BGA 989 Balls USB 2.0 Conn. 4 P.37
Daughter board
Port 11 Digital Camera
Port 2 Port 1 (With Digital MIC) P.21
Mini Card Ethernet Port 8 Mini Card
WLAN/BT4.0 RTL8105E WLAN (Half) P.38

Half P.38 P.32
Port 10 Card Reader
RTS5179 P.34 3 in 1 Socket
P.34
3 3

RJ45 Port 9 Touch Screen
P.32
P.21
HD Audio
P13~20
Digital Mic.
SPI
RTC CKT. SPI ROM
P.44 4MB P.13 LPC Bus Audio Codec Headphone Jack / Mic. Jack combo P.33

Power On/Off CKT. SPI
33MHz ALC3221 Int. Speaker R / L
P.33 P.33
P.40 SPI ROM
2MB P.13

DC/DC Interface CKT. ENE KBC
P.41
KB9012 P.39

PS/2
4 4

Int.KBD Touch Pad
P.40 P.40

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/08/22 Deciphered Date 2013/08/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9104P
Date: Wednesday, August 29, 2012 Sheet 2 of 57
A B C D E
A B C D E

Compal Confidential
Project Code : VAW00
File Name : LA-9104P
LS-9101P (PWR/B)
1 1

UE5
Lid (SA00003VQ00)

SW1 4 pin-Hot Bar
(SN100004Y00)
PBATT
Battery

JMINI
PWR-BTN FFC
4 pin MINI Card JLVDS
40 pin

PJPDC JKB
5 pin 30 pin

JTP
LS-9102P (USB/B)
2 2
6 pin
JHDMI HDMI

JTOUCH JPWR
JODD
6 pin 4 pin JFAN
3 pin USB JUSB4
USB-DB FFC 8 pin
XDP 8 pin Hot Bar
JLAN RJ-45
JXDP
LA-9104P M/B JDB
8 pin

JUSB1 USB Top Side JHDD
RTC JRTC
Bottom Side
2 pin
JUSB2 USB
(OAK 15")
JUSB3 USB
JREAD
3
JSPK 3
4 pin
JHP Card
HP Reader
TP-MB FFC
6 pin Led1 Led3
Led2 Led4

TP-Module

4
TP-BTN FFC 4
4 pin
LS-9103P (TP-BTN/B)

4 pin
Security Classification Compal Secret Data Compal Electronics, Inc.
Hot Bar Issued Date 2012/08/22 Deciphered Date 2013/08/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DB block diagram
SW2 SW3 Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9104P
Date: Wednesday, August 29, 2012 Sheet 3 of 57
A B C D E
A

Board ID Table for AD channel
Vcc 3.3V +/- 5%
Ra 100K +/- 5% BOARD ID Table Project ID Table
Board ID Rb V AD_BID min V AD_BID typ V AD_BID max EC AD3 ID PCB Revision ID Project Revision USB PORT# DESTINATION
0 0 0 V 0 V 0.155 V 0x00-0x0C 0 0.1 0
1 8.2K +/- 5% 0.168 V 0.250 V 0.362 V 0x0D-0x1C 1 0.1 0.1 1 0 USB conn.2
2 18K +/- 5% 0.375 V 0.503 V 0.621 V 0x1D-0x30 2 0.2 2
3 33K +/- 5% 0.634 V 0.819 V 0.945 V 0x31-0x49 3 0.2 0.2 3 1 USB conn.1
4 56K +/- 5% 0.958 V 1.185 V 1.359 V 0x4A-0x69 4 0.3 4
5 100K +/- 5% 1.372 V 1.650 V 1.838 V 0x6A-0x8E 5 0.3 0.3 5 UMA
2 USB conn.3
6 200K +/- 5% 1.851 V 2.200 V 2.420 V 0x8F-0xBB 6 1.0 6 DIS THAMES
7 NC 2.433 V 3.300 V 3.300 V 0xBC-0xFF 7 1.0 1.0 7 DIS MARS PRO
3 USB conn.4 (DB)
UMA THM MARS

4 NC
SMBUS Control Table
Express Thermal VGA Thermal
SOURCE MINI1 MINI2 BATT SODIMM Card Sensor FFS Sensor VGA XDP Charger 5 NC
PCH 6 NC
EC_SMB_CK1
EC_SMB_DA1
KB9012
V V
EC_SMB_CK2 KB9012
V V 7 NC
EC_SMB_DA2

PCH_SML0CLK PCH Link 8 MINI CARD (WLAN)
PCH_SML0DATA

PCH_SML1CLK PCH 9 Touch Screen
PCH_SML1DATA

MEM_SMBCLK PCH
V V V V V V 10 Card Reader
MEM_SMBDATA

11 Camera

12 NC
1
DIFFERENTIAL DESTINATION FLEX CLOCKS DESTINATION 1

13 NC
CLKOUT_PCIE0 10/100 LAN CLKOUTFLEX0 None

CLKOUT_PCIE1 MINI CARD WLAN CLKOUTFLEX1 None
SATA DESTINATION PCI EXPRESS DESTINATION
CLKOUT_PCIE2 None CLKOUTFLEX2 None

CLKOUT_PCIE3 None CLKOUTFLEX3 None SATA0 HDD Lane 1 10/100 LAN
CLK
SATA1 None Lane 2 MINI CARD (WLAN)
CLKOUT_PCIE4 None
SATA2 ODD Lane 3 None
CLKOUT_PCIE5 None
CLKOUT DESTINATION
SATA3 None Lane 4 None
CLKOUT_PCIE6 None
PCI0 PCH_LOOPBACK SATA4 None Lane 5 None
CLKOUT_PCIE7 None
PCI1 EC LPC
CLKOUT_PEG_B None SATA5 None Lane 6 None
PCI2 None
Lane 7 None
PCI3 None
Lane 8 None
: etoN lobmyS
PCI4 None
dnuorG latigiD snaem :
dnuorG golanA snaem :
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/08/22 Deciphered Date 2013/08/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9104P
Date: Wednesday, August 29, 2012 Sheet 4 of 57
A
5 4 3 2 1

UC1 i3R1@ UC1 i3R3@ UC1 i3VOSR1@ UC1 i3VOSR3@

SA00005L52L SA00005L53L SA00005UH1L SA00005UH2L

AV8063801058401-SR0N9-L1-1.8G_BGA1023~D AV8063801058401-SR0N9-L1-1.8G_BGA1023~D AV8062701313000-SR0U3-J1-1.4G_BGA1023~D AV8062701313000-SR0U3-J1-1.4G_BGA1023~D
UC1 i5R3@ UC1 i7R1@ UC1 i7R3@

SA00005K62L SA00005K53L SA00005K52L

(1)PEG_RCOMPO (G4) use 4mil connect to PEG_ICOMPI, then use 4mil connect to RC1. AV8063801058002-SR0N8-L1-1.7G_BGA1023~D AV8063801057605-SR0N6-L1-1.9G_BGA1023~D AV8063801057605-SR0N6-L1-1.9G_BGA1023~D
(2)PEG_ICOMPO use 12mil connect to RC1 UC1 CELR1@ UC1 CELR3@
D D

PEG_RCOMPO (G4) R_COMP place close to CPU SA00006021L SA00006022L
width 4 mils
PEG_ICOMPI (G3) VCC_IO AV8062701085401-SR0VA-Q0-1.5G_BGA1023~D AV8062701085401-SR0VA-Q0-1.5G_BGA1023~D
Trace length width 12 mils UC1 PENR1@ UC1 PENR3@
Max is 500 mils PEG_ICOMPO (G1) R_COMP
SA00005ZZ1L SA00005ZZ2L
+VCCP
AV8062701084801-SR0V5-Q0-1.6G_BGA1023~D AV8062701084801-SR0V5-Q0-1.6G_BGA1023~D

1
RC2
24.9_0402_1%

SA00005K63L UC1I i5R1@

2
UC1A i5R1@
G3 PEG_COMP PEG_ICOMPI and RCOMPO signals should be shorted and routed
PEG_ICOMPI G1
PEG_ICOMPO with - max length = 500 mils - typical impedance = 43 mohms
M2 G4 BG17 M4
<15> DMI_CRX_PTX_N0
P6 DMI_RX#[0] PEG_RCOMPO PEG_ICOMPO signals should be routed with - max length = 500 mils BG21 VSS[181] VSS[250] M58
<15> DMI_CRX_PTX_N1 DMI_RX#[1] - typical impedance = 14.5 mohms VSS[182] VSS[251]
P1 BG24 M6
<15> DMI_CRX_PTX_N2 DMI_RX#[2] VSS[183] VSS[252]
P10 H22 BG28 N1
<15> DMI_CRX_PTX_N3 DMI_RX#[3] PEG_RX#[0] VSS[184] VSS[253]
J21 BG37 N17
N3 PEG_RX#[1] B22 BG41 VSS[185] VSS[254] N21
<15> DMI_CRX_PTX_P0 DMI_RX[0] PEG_RX#[2] VSS[186] VSS[255]
P7 D21 BG45 N25
<15> DMI_CRX_PTX_P1 DMI_RX[1] PEG_RX#[3] VSS[187] VSS[256]

DMI
P3 A19 BG49 N28
<15> DMI_CRX_PTX_P2 DMI_RX[2] PEG_RX#[4] VSS[188] VSS[257]
<15> DMI_CRX_PTX_P3
P11 D17 BG53 N33
DMI_RX[3] PEG_RX#[5] B14 BG9 VSS[189] VSS[258] N36
K1 PEG_RX#[6] D13 C29 VSS[190] VSS[259] N40
<15> DMI_CTX_PRX_N0 M8 DMI_TX#[0] PEG_RX#[7] A11 C35 VSS[191] VSS[260] N43
PEG_GTX_C_HRX_N7 PEG_GTX_C_HRX_N7 <24>
<15> DMI_CTX_PRX_N1 N4 DMI_TX#[1] PEG_RX#[8] B10 C40 VSS[192] VSS[261] N47
PEG_GTX_C_HRX_N6 PEG_GTX_C_HRX_N6 <24>
<15> DMI_CTX_PRX_N2 R2 DMI_TX#[2] PEG_RX#[9] G8 D10 VSS[193] VSS[262] N48
C PEG_GTX_C_HRX_N5 PEG_GTX_C_HRX_N5 <24> C
<15> DMI_CTX_PRX_N3 DMI_TX#[3] PEG_RX#[10] A8 D14 VSS[194] VSS[263] N51
PEG_GTX_C_HRX_N4 PEG_GTX_C_HRX_N4 <24>
K3 PEG_RX#[11] B6 PEG_GTX_C_HRX_N3 D18 VSS[195] VSS[264] N52
<15> DMI_CTX_PRX_P0 DMI_TX[0] PEG_RX#[12] PEG_GTX_C_HRX_N3 <24> VSS[196] VSS[265]
M7 H8 PEG_GTX_C_HRX_N2 PEG_GTX_C_HRX_N2 <24> D22 N56
<15> DMI_CTX_PRX_P1 P4 DMI_TX[1] PEG_RX#[13] E5 D26 VSS[197] VSS[266] N61
PEG_GTX_C_HRX_N1 PEG_GTX_C_HRX_N1 <24>
<15> DMI_CTX_PRX_P2 T3 DMI_TX[2] PEG_RX#[14] K7 D29 VSS[198] VSS[267] P14
PEG_GTX_C_HRX_N0 PEG_GTX_C_HRX_N0 <24>
<15> DMI_CTX_PRX_P3 DMI_TX[3] PEG_RX#[15] D35 VSS[199] VSS[268] P16
K22 D4 VSS[200] VSS[269] P18
PEG_RX[0] K19 D40 VSS[201] VSS[270] P21