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A B C D E
SYSTEM
TPS51120 40
Project code: 91.4P401.001
Garda-3 Block Diagram
(Discrete)
PCB P/N : 55.4P401.XXX
INPUTS
DCBATOUT
OUTPUTS
5V_S5
REVISION : 06208-2 3D3V_S5
Mobile CPU (Hannstar, GCE) SYSTEM DC/DC
4 CLK GEN. G791/G792 APL5912 43 4
IDT CV125PA
Yonah 478 19
DATE:2006/0?/?? INPUTS OUTPUTS
(ICS 954206) 3 PCB STACKUP
1D8V_S3 1D05V_S0
4, 5 TOP
TVO
14
TPS51116 41
HOST BUS 400/533/667MHz VCC
LVDS 1D8V_S3
14"WSXGA+
DDR2 533/667MHz LCD 13
S DCBATOUT
DDR_VREF_S0
533 MHz RGB CRT
S
11,12 PCI Express x16 ATI CRT APL5332KAC
Calistoga M56 Ver.: B24 M54P / M52P
14 GND
3D3V_S0 2D5V_S0
DDR2 533/667MHz
Ver.:A2 :71.945PM.00U / QK46 M52 Ver.: A12 45,46,47,48,49 BOTTOM 43
M54 Ver.: A12
533 MHz 6,7,8,9,10
VRAM x4
APL5912
11,12
3 128/256M
50,51 1D8V_S3 1D5V_S0 3
DMI I/F 100MHz 43
Line In PCMCIA I/F PCMCIA
30
Codec ENE CB1410 SLOT
AZALIA CARDBUS PWR SW Support
30 ALC883 24,25 TPS2211 TypeII MAXIM CHARGER
29 25
25 ISL6255 42
MIC In RICOH
PCI BUS R5C832 INPUTS OUTPUTS
1394 1394
28 MS/MS Pro/xD/ CHG_PWR
CONN 18V 4.0A
INT.MIC CardReader MMC/SD/SDIO DCBATOUT
6 in 1 UP+5V
27,28 Mini-PCI 28
Line Out
(SPDIF)
ICH7M 802.11A/B/G 31
5V 100mA
OP AMP Ver. : B0, 71.ICH7M.A0U / QK65
30
MAX4411 LAN CPU
30 GIGA or 10/100 TXFM ISL6262
2 RTL8110 or RTL8100CL
23 RJ45
23
38,39
2
22 INPUTS OUTPUTS
30 OP AMP PCIEx1 Mini Card*1
G1432Q 802.11A/B/G 26 VCC_CORE_S0
DCBATOUT
30 0~1.3V
INT.SPKR 44A
SPI I/F BIOS
SST25LF080A
MODEM LPC BUS
35 ATI M52 DC/DC
RJ11 MDC Card 15,16,17,18 ISL6269 52
21
INPUTS OUTPUTS
SATA
PATA
PCI Express Thermal
SIO KBC
Renesas
LPC DCBATOUT VGA_CORE_S0
New card USB NS87381 G792SFUF DEBUG
31 RE144B FAN CONN
3 PORT 34 32 CONN. 35 APL5331 43
21 19
1D8V_S0 1D2V_S0
21
1 PWR SW MINI USB FIR 34 Touch INT. BOM
1
TPS2231 31 HDD 20 CDROM Blue-tooth Pad 33 KB 33
20 Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
BLOCK DIAGRAM
Size Document Number Rev
A3
AG3 2
Date: Thursday, April 20, 2006 Sheet 1 of 55
A B C D E
ICH7M Integrated Pull-up 954305D 27Mhz/LCDCLK Spread Calistoga Strapping Signals and
and Pull-down Resistors ICH7-M EDS 17837 1.5V1
and Frequency Selection Table Configuration EDS 17050 0.71
page 7
SS3 SS2 SS1 SS0
Byte9 bit6 bit5 bit4 Spread Amount% page 3 Pin Name Strap Description Configuration
EE_DIN, EE_DOUT, GNT[3:0], GPIO[25], bit 7 CFG[2:0] FSB Frequency Select
GNT[4]#/GPIO48, GNT[5]#/GPO17, PME#, 0 0 0 0 -0.50 Down 001 = FSB533
ICH7 internal 20K pull-ups 011 = FSB667
LAD[3:0]#/FHW[3:0]#, LAN_RXD[2:0] 0 0 0 1 -1.00 Down others = Reserved
4 LDRQ[0], LDRQ[1]/GPIO[41], 0 0 1 0 -1.50 Down CFG[4:3] Reserved 4
PWRBTN#, TP[3] 0 0 1 1 -2.00 Down CFG5 DMI x2 Select 0 = DMI x2
1 = DMI x4 (Default)
0 1 0 0 -0.75 Down CFG6 Reserved
DD[7], DDREQ ICH7 internal 11.5K pull-downs
0 1 0 1 -1.25 Down CFG7 0 = Reserved
CPU Strap 1 =Mobile CPU(Default)
ACZ_BIT_CLK, ACZ_RST#, ACZ_SDIN[2:0], ICH7 internal 20K pull-downs 0 1 1 0 -1.75 Down
Reserved
ACZ_SDOUT, ACZ_SYNC, DPRSLPVR/GPIO16, 0 1 1 1 -2.25 Down CFG8
EE_CS,SPI_ARB, SPI_CLK, SPKR, 1 0 0 0 +-0.25 Center 0 = Reverse Lanes,15->0,14->1 ect..
CFG9 PCI Express Graphics 1= Normal operation(Default):Lane
1 0 0 1 +-0.5 Center Lane Reversal Numbered in order
USB[7:0][P,N] ICH7 internal 15K pull-downs
1 0 1 0 +-0.75 Center
CFG[11:10] Reserved
SATALED# ICH7 internal 15K pull-up 1 0 1 1 +-1.0 Center
XOR/ALL Z test 00 = Reserved
1 1 0 0 +-0.25 Center CFG[13:12] straps 01 = XOR mode enabled
LAN_CLK ICH7 internal 100K pull-down 10 = All Z mode enabled
1 1 0 1 +-0.5 Center 11 = Normal Operation
(Default)
1 1 1 0 +-0.75 Center
CFG[15:14] Reserved Reserved
ICH7M IDE Integrated Series 1 1 1 1 +-1.0 Center
CFG16 FSB Dynamic ODT 0 = Dynamic ODT Disabled
3 Termination Resistors Global R-comp Disable
1 = Dynamic ODT Enabled (Default)
0 = All R-comp Disable 3
CFG17 (All R-comps) 1 = Normal Operation (Default)
DD[15:0], DIOW#, DIOR#, DREQ,
approximately 33 ohm
PCI Routing page 16
CFG18 VCC Select 0 = 1.05V (Default)
DDACK#, IORDY, DA[2:0], DCS1#, 1 = 1.5V
DCS3#, IDEIRQ
IDSEL INT -> PIRQ REQ/GNT CFG19 DMI Lane Reversal 0 = Normal operation (Default):lane
Numbered in order
1410 22 A->G 0 1 =Reverse Lane,4->0,3->1 ect...
A/C -> E 0 = Only SDVO or PCIE x1 is
ICH7M Functional Strap Definitions page 16 MiniPCI 21 B/D -> E 1 CFG20 SDVO/PCIE
Concurrent
operational (Default)
1 =SDVO and PCIE x1 are operating
simultaneously via the PEG port
Signal Usage/When Sampled Comment LAN 23 A -> H 2 SDVOCRTL SDVO Present 0 = No SDVO Card present
ACZ_SDOUT XOR Chain Entrance/ Allows entrance to XOR Chain testing when TP3 _DATA (Default)
PCIE Port Config bit1, pulled low.When TP3 not pulled low at rising edge 1= SDVO Card present
Rising Edge of PWROK of PWROK,sets bit1 of RPC.PC(Config Registers: 1394 17 A->B, B->F, 3 NOTE: All strap signals are sampled with respect to the leading
offset 224h) edge of the Calistoga GMCH PWORK in signal.
ACZ_SYNC PCIE bit0, Sets bit0 of RPC.PC(Config Registers:Offset 224h)
Rising Edge of PWROK.
EE_CS Reserved This signal should not be pull high. History
EE_DOUT Reserved This signal should not be pull low.
2 GNT2# Reserved This signal should not be pull low. 2
Top-Block Sampled low:Top-Block Swap mode(inverts A16 for
GNT3# Swap Override. all cycles targeting FWH BIOS space).
Rising Edge of PWROK. Note: Software will not be able to clear the
Top-Swap bit until the system is rebooted
without GNT3# being pulled down.
GNT5#/ Boot BIOS Destination Controllable via Boot BIOS Destination bit
GPIO17#, Selection. (Config Registers:Offset 3410h:bit 11:10).
GNT4#/ Rising Edge of PWROK. GNT5# is MSB, 01-SPI, 10-PCI, 11-LPC.
GPIO48
DPRSLPVR Reserved This signal should not be pull high.
GPIO25 Reserved.
Rising Edge of RSMRST#. This signal should not be pull low.
INTVRMEN Integrated VccSus1_05 Enables integrated VccSus1_05 VRM when
VRM Enable/Disable. sampled high
Always sampled.
LINKALERT# Reserved Requires an external pull-up resistor.
REQ[4:1]# XOR Chain Selection. BOM
Rising Edge of PWROK. TBD, Chapter 8.
1 1
SATALED# Reserved This signal should not be pull low.
Wistron Corporation
SPKR No Reboot. If sampled high, the system is strapped to the 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Rising Edge of PWROK. "No Reboot" mode(ICH7 will disable the TCO Timer Taipei Hsien 221, Taiwan, R.O.C.
system reboot feature). The status is readable
Title
via the NO REBOOT bit.
Reference
TP3 XOR Chain Entrance. This signal should not be pull low unless using Size Document Number Rev
Rising Edge of PWROK. XOR Chain testing. A3
AG3 2
Date: Thursday, April 20, 2006 Sheet 2 of 55
A B C D E
3D3V_S0
3D3V_S0 3D3V_S0 R222
R530 0R3-0-U-GP
2 13D3V_CLKPLL_S0 2 1 3D3V_48MPW R_S0 3D3V_CLKGEN_S0 2 1
R532
1
1
1
1
1
1
1
1
1
1
1
4 C321 0R3-0-U-GP 0R3-0-U-GP 4
Do Not Stuff C650 C647 C320 C325 C651 C655 C645 C648 C653 C319
SC1U6D3V2ZY-GP SC1U6D3V2ZY-GP SCD1U16V2ZY-2GP
DY
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SC4D7U10V5ZY-3GP
2
2
2
2
2
2
2
2
2
2
2
3D3V_S0
DREFSSCLK_1 RN54 2 3 SRN33J-5-GP-U DREFSSCLK 7
DREFSSCLK#_1 1 GM 4 DREFSSCLK# 7
U34
1
RN59 2 3 SRN33J-5-GP-U
R522 SA 27 PCLK_R5C832 R223 1 2 33R2J-2-GP 1 4
CLK_MCH_3GPLL 7
CLK_MCH_3GPLL# 7
10KR2J-3-GP R227 1 2 33R2J-2-GP PCLKCLK0 56 17
32 PCLK_KBC PCI0 LVDS
31 PCLK_MINI R228 1 2 33R2J-2-GP PCLKCLK1 3 18 RN61 2 3 SRN33J-5-GP-U CLK_PCIE_ICH 16
R229 22R2J-2-GP PCLKCLK2 PCI1 LVDS#
24 PCLK_PCM 2 1 4 1 4 CLK_PCIE_ICH# 16
2
R231 33R2J-2-GP PCLKCLK3 PCI2 CLK_MCH_3GPLL_1
SS_SEL SA 34
35
PCLK_SIO
PCLK_FW H R225
1
2
2
1 22R2J-2-GP
5 PCI3 SRC1
SRC1#
19
20 CLK_MCH_3GPLL_1# 2 3 Do Not Stuff CLK_PCIE_MINI2 55
H/L: 100/96MHz 22 PCLK_LAN R233 1 2 33R2J-2-GP SS_SEL 9 PCIF1/SEL100/96# SRC2 22 CLK_PCIE_ICH_1 1 MINIC2 4 CLK_PCIE_MINI2# 55
1
R525 1 2 33R2J-2-GP ITP_EN 8 23 CLK_PCIE_ICH_1# RN106
16 CLK_ICHPCI PCIF0/ITP_EN SRC2#
R524 1 2 24 CLK_PCIE_MINI2_1 RN65 2 3 Do Not Stuff CLK_PCIE_SATA 15
Do Not Stuff R523 10KR2J-3-GP SRC3 CLK_PCIE_MINI2_2#
16 PM_STPPCI# 55 PCI_STOP# SRC3# 25 1 SATA 4 CLK_PCIE_SATA# 15
DY H/L : CPU_ITP/SRC7 SRC4 26 CLK_PCIE_SATA_1
PCLK_FWH & PCLK_PCM 27 CLK_PCIE_SATA_1# RN66 1 4 Do Not Stuff CLK_PCIE_NEW 31
2
SRC4# CLK_PCIE_NEW _1
3 need equal length 11,18 SMBC_ICH 46 SCL SRC5 31
CLK_PCIE_NEW _1#
2 NEW 3 CLK_PCIE_NEW # 31
3
11,18 SMBD_ICH 47 SDA SRC5# 30
33 CLK_PCIE_MINI1_1 RN62 1 4 SRN33J-5-GP-U CLK_PCIE_MINI1 26
RN50 SRC6 CLK_PCIE_MINI1_1#
DREFCLK_1 SRC6# 32 2 MINIC 3 CLK_PCIE_MINI1# 26
7 DREFCLK 1 4 14 DOT96
7 DREFCLK# 2 GM 3 DREFCLK#_1 15 36 CLK_PCIE_PEG_1 RN56 1 4 Do Not Stuff CLK_PCIE_PEG 45
SRN33J-5-GP-U DOT96# CPU2_ITP/SRC7 CLK_PCIE_PEG_1#
C323 CPU2_ITP#/SRC7# 35 2 ATI 3 CLK_PCIE_PEG# 45
1 2 GEN_XTAL_IN 50 44 CLK_CPU_BCLK_1 RN47 1 4 SRN33J-5-GP-U
Dummy when use UMA
XTAL_IN CPU0 CLK_CPU_BCLK 4
GEN_XTAL_OUT_R 1 2 GEN_XTAL_OUT 49 43 CLK_CPU_BCLK_1# 2 3 CLK_CPU_BCLK# 4
XTAL_OUT CPU0#
1
SC27P50V2JN-2-GP X3 R224 470R2J-2-GP 41
R232 1 CPU1
34 CLK14_SIO 2 22R2J-2-GP CPU1# 40 CLK_MCH_BCLK_1 RN51 1 4 SRN33J-5-GP-U CLK_MCH_BCLK 6
X-14D31818M-31GP 16 CLK_ICH14 R230 1 2 GEN_REF 52 CLK_MCH_BCLK_1# 2 3 CLK_MCH_BCLK# 6
C322 82.30005.831 22R2J-2-GP REF
2