Security Classification Compal Secret Data Compal Electronics, Inc. Issued Date 2011/10/12 Deciphered Date 2013/10/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Cover Page AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev B 0.1 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA8611P Date: Friday, November 04, 2011 Sheet 1 of 51 A B C D E A B C D E
4 * x1 PCI-E 2.0 x4 UMI Gen. 1 LVDS Conn. 2.5GT/s per lane page 25 GPP1 GPP0 2Channel Speaker page 30 LAN AR8161/8162 2 AZALIA Audio Codec Internal MIC 2 page 28~29 page 30 Hudson M3 CX20671-21Z page 30 PCI Express USB(WiMAX) uFCBGA-656 Audio Jacks CRT Conn. FCH CRT (VGA DAC) Mini Card Slot 1 page 27 24.5mm x 24.5mm Sub-board 4*USB3.0,10*USB2.0 WLAN/WiMAX page 32 4 * x1 PCI-E 2.0 CMOS Camera page 25 page 12~16 6*SATA serial BlueTooth Conn page 31
USB Port 3.0 x2(Left) page 37,38 LPC Bus SPI ROM USB Port 2.0 x 1 (Right) Sub-board page 13
RTS5178 3 EC Card Reader 2 in 1 Conn. 3 Cap Sensor USB 2.0 x 1 Sub-board SD/SDXC/MMC Sub-board ENE KB930/ KB9012 page 34
Touch Pad Int. KBD page 35 page 35 SATA0 SATA 3.0 HDD Conn. page 31
SATA1 SATA ODD Conn. page 31
Thermal Sensor EMC1403 4 page 32 4
Security Classification Compal Secret Data Compal Electronics, Inc. Issued Date 2011/10/12 Deciphered Date 2013/10/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Block Diagrams AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev B 0.1 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA8611P Date: Friday, November 04, 2011 Sheet 2 of 51 A B C D E A B C D E
Voltage Rails Power Plane Description S1 S3 S5 FCH Hudson-M2/3 Comal FCH Hudson-M2/3 FCH Hudson-M2/3 VIN Adapter power supply (19V) N/A N/A N/A SATA Port List PCIE Port List USB Port List USB OC PIN B+ AC or battery power rail for power circuit. N/A N/A N/A SATA0 NC PCIE0 LAN USB1.1 USB_OC0# USB3.0 (LP1, LP2) +APU_CORE Core voltage for APU ON OFF OFF SATA1 HDD PCIE1 WLAN Port0 NC USB_OC1# USB2.0 (RP1)
APU +APU_CORE_NB Voltage for On-die VGA of APU ON OFF OFF 1 1 +1.5V 1.5V power rail for APU VDDIO and DDR ON ON OFF SATA2 ODD PCIE2 NC Port1 NC USB_OC2# USB2.0 (RP2) +0.75VS 0.75V switched power rail for DDR terminator ON OFF OFF +1.2VS 1.2V (VDDR, VDDP) switched power rail for APU ON OFF OFF SATA3 NC PCIE3 NC USB2.0 USB_OC3# NC +2.5VS 2.5V for APU VDDA ON OFF OFF SATA4 NC PCIE0 NC Port0 Right USB1 USB_OC4# NC +1.1VALW 1.1V switched power rail for FCH ON ON ON* SATA5 NC PCIE1 NC Port1 Right USB2 USB_OC5# NC
FCH +1.1VS 1.1V switched power rail for FCH ON OFF OFF +1.5VS 1.5V switched power rail ON OFF OFF PCIE2 NC Port2 Mini PCIE USB_OC6# NC +VGA_CORE 0.95-1.2V switched power rail ON OFF OFF +1.5VGS 1.5V switched power rail ON OFF OFF PCIE3 NC Port3 USB Camera USB_OC7# NC +1.8VGS 1.8V switched power rail ON OFF OFF Port4 BT +1.0VGS 1.0V switched power rail for VGA ON OFF OFF +3VALW 3.3V always on power rail ON ON ON* Port5 Card Reader +3V_LAN 3.3V power rail for LAN ON ON ON* Port6 NC +3VS 3.3V switched power rail ON OFF OFF +5VALW 5V always on power rail ON ON ON* Port7 NC +5VS 5V switched power rail ON OFF OFF Port8 NC 2 2 +VSB VSB always on power rail ON ON ON* +RTCVCC RTC power ON ON ON Port9 NC Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF. Port10 USB3.0 LP1 Port11 USB3.0 LP2 Port12 NC EC SM Bus1 address EC SM Bus2 address BOM Structure Port13 NC Device Address HEX Device Address HEX UMA@ : UMA only Smart Battery 0001-011xb 15H EMC1403(VGA, DDR,WLAN) 1001-101xb 9AH PX@ : DIS muxluss SB-TSI (default) 1001-100xb 98H CMOS@ : USB camera VGA Thermal 1000-001xb 82H HDMI@ : HDMI function Cap Sensor 1000-0000b 80H nonHDMI@ : w/o HDMI function RTDS2132S-E 1010-1000b A8H BT@ : BT function ME@ : ME components X76@ : VRAM 3 3 45@ : 45 Level SM Bus Controller 0 (FCH_SMB1 ~ FCH_SMB4, SMB_ALERT#) PX4@ : PX4 PX5@ : PX5 Device Address HEX 8162@ : 10/100 LAN GIGA@ : giga LAN 14@ : G 14" 15@ : G 15" BBH@ : Best Buy high-end nonBBH@ : non Best Buy high-end SM Bus Controller 1 (FCH_SMB0) AN@ : Apple & Nokia combo A@ : Apple only Device Address HEX
Security Classification Compal Secret Data Compal Electronics, Inc. Issued Date 2011/10/12 Deciphered Date 2013/10/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Notes List AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev B 0.1 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA8611P Date: Friday, November 04, 2011 Sheet 3 of 51 A B C D E 5 4 3 2 1
Without BACO option : Power-Up/Down Sequence PE_GPIO0 (PXS_RST#) : Low > Reset dGPU ; High >Normal operation PE_GPIO1 (PXS_PWREN) : Low > dGPU Power OFF ; High > dGPU Power ON "Seymour" has the following requirements with regards to power-supply sequencing to avoid damaging the ASIC: BACO option : All the ASIC supplies, except for VDDR3, must fully reach their respective PE_GPIO0 (PXS_RST#) : High >Normal operation (dGPU is not reset on BACO mode) PE_GPIO1 (PXS_PWREN) : Low > dGPU Power OFF ; High > dGPU Power ON (always High) nominal voltages within 20 ms of the start of the ramp-up sequence, though a shorter ramp-up duration is preferred. There is no timing requirement on the dGPU Power Pins Voltage PX 3.0 BACO Mode Max current D ramp up of VDDR3 relative to other power rails. PCIE_PVDD, PCIE_VDDR, TSVDD, VDDR4, VDD_CT, 1.8V OFF ON 1679mA D
The external pull-up resistors on the DDC/AUX signals (if applicable) should DPE_PVDD, DP[F:E]_VDD18, DP[D:A]_PVDD, ramp up before or after both VDDC and VDD_CT have ramped up. DP[D:A]_VDD18, AVDD, VDD1DI, A2VDDQ, VDD2DI, VDDC and VDD_CT should not ramp up simultaneously. For example, VDDC DPLL_PVDD, MPV18, and SPV18 should reach 90% before VDD_CT starts to ramp up (or vice versa). For BACO DP[F:E]_VDD10, DP[D:A]_VDD10, DPLL_VDDC, and 1.0V OFF ON 775mA enabled designs, VDDC must ramp up before VDD_CT at system power up. SPV10 For power down, reversing the ramp-up sequence is recommended PCIE_VDDC 1.0V OFF ON 1.1A VDDR3 3.3V OFF ON 60mA BIF_VDDC (current consumption = 55mA@1.0V, in Same as OFF ON 70mA BACO mode) VDDC Same as PCIE_VDDC VDDR1 1.5V OFF OFF 1.2A VDDR3(3.3VGS) VDDC/VDDCI TBD OFF OFF 28
PCIE_VDDC(1.0V) PX4.0 C VDDR1(1.5VGS) C PE_GPIO0(PXS_RST#) PE_EN BACO Switch iGPU dGPU VDDC/VDDCI(1.12V) BIF_VDDC
Global ASIC Reset PX5.0 T4+16clock PE_GPIO0(PXS_RST#) +VGA_CORE iGPU dGPU BIF_VDDC
PE_GPIO1(PXS_PWREN)
+3.3VALW MOS +3.3VGS Short PX_MODE and PX_PWREN 1 B+ Regulator +1.5VGS +1.5V +1.0VGS LDO 2 3
A +B Regulator +VGA_CORE A +5VLAW +1.8VGS Regulator 5 4
Security Classification Compal Secret Data Compal Electronics, Inc. Issued Date 2011/10/12 Deciphered Date 2013/10/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL dGPU Notes List Size Document Number Rev AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.1 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA8611P Date: Friday, November 04, 2011 Sheet 4 of 51 5 4 3 2 1 A B C D E
