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5 4 3 2 1




VER : 1A BOM MARK
BOM P/N Description ZR7 SYSTEM BLOCK DIAGRAM [email protected] INT VGA
[email protected] DISCRETE
[email protected] SW VGA
[email protected] N11P VGA
[email protected] N11P VGA
[email protected] N11P + N11E VGA
D
Clarksfield
64MB/128MB x 8 [email protected] N11X+SW VGA
w/4 DIMM> N11M-GE1 Channel C
[email protected] Option P/N (ARD&R D)
P21, 22
Arrandale N11P-GE1 [email protected] Option P/N (GPU/ VRAM)
DDRIII-SODIMM2
Dual Channel DDR III Auburndale EXT_LVDS
DDRIII-SODIMM1 Nvidia-GPU
800/1066 MHZ IMC rPGA 989 PCI-E x16
P14,15 P4, 5, 6, 7
GFX EXT_CRT
P16, 17, 18, 19, 20, 21, 22,
CRT Con.
TS3DV421 P23
EXT_LVDS
FDI DMI
SN74CBT3257 x3
LVDS/CRT
X'TAL SLG8LV595 DMI(x4)
SWITCH
14.318MHz CLOCK USB-8
LVDS/CCD/MIC
FDI DMI
INT_CRT
GENERATOR P3 Con.
INT_LVDS P23 Int. MIC P23
CLK
Display
SATA 0
C SATA - HDD C

P28 INT_HDMI PS8101
SATA
LS P24 HDMI Con.
SATA - ODD SATA 1
P28 EXT_LVDS P24


PCIE-6
USB Port x4 PCI-E x1
USB-1/3/9/11 MINI CARD
P33 USB Ibex Peak-M USB-13
WLAN
P27
PCH
USB-4 P8, 9, 10, 11, 12, 13
Bluetooth Con.
P33
PCIE-1 AR8151
X'TAL RJ45
32.768KHz GIGA LAN P25 P26
Cardreader AU6437 USB-12
P31
Cardreader control
P31 X'TAL
B X'TAL 25MHz 25MHz B

P8 BATTERY RTC
BOM Option Table
Reference Description
for UMA only SKU ISL88731A MAX8792ETD+T
[email protected]
for Switchable Graphic only SKU Azalia SPI SPI ROM (ME) Batery Charger +VGPU_CORE
[email protected] IHDA P37 P43
P9
[email protected] special case component LPC
* do not stuff RT8206B
LPC 3V/5V P38


ISL62881HRZ-T
Int. MIC ALC271 NPCE781 +VGFX_AXG P46
X'TAL
AUDIO CODEC EC P36 32.768KHz
P29 UP6111AQDD HPA00835RTER
P40 +1.8V P45



Speaker MIC JACK HP/SPDIF Power CIR Function Touch Pad
P30 P30 P30 Board Con. Board Board Con.
A Con. A
P33 P37 P33 P35

P42
K/B Con. W25X16VSS1G EM-6781-T3
HALL SENSOR Fan Driver
SPI FLASH
P35 P37 P24
(PWM Type) P35 Quanta Computer Inc.
PROJECT : ZR7
Size Document Number Rev
3B
Block Diagram
Date: Monday, February 22, 2010 Sheet 1 of 49
5 4 3 2 1
1 2 3 4 5 6 7 8



GPU PWR CTRL Option 1 (Default/ VDDR3 before VDDC)
+3.3V VIN VIN +1.5V +1.5V_SUS +1.8V +5V



VDDR3 +3V_D VDDC PG_GPUIO_EN VDDCI PG_1V_EN +1V (DP PLL PWR) PG_1.5V_EN VDDR1 PG_1.5V_EN VDDR4 PG_1.5V_EN BJT dGPU_PWROK MOS
dGPU_VRON dGPU_PWR_EN#
MOS (AO3413) ISL6264 ISL62872 G9334ADJ & MOS MOS (AO4710) MOS (AO6402) AO3413
P22 P44 P45 P47 P43 P43 P22 P22



A
+3_D (0.5A) +VGPU_CORE (20A) +VGPU_IO (4.5A) +1V (3A) +1.5V_GPU (10A) +1.8V_GPU (3A) +5_GPU A




GPU PWR CTRL Option 2 (VDDR3 after VDDR1)
VIN VIN +1.5V +1.5V_SUS +3.3V +1.8V +5V



VDDC PG_GPUIO_EN VDDCI PG_1V_EN +1V (DP PLL PWR) PG_1.5V_EN VDDR1 +1.5V_GPU VDDR3 +3V_D VDDR4 PG_1.5V_EN BJT dGPU_PWROK MOS
dGPU_VRON dGPU_PWR_EN#
ISL6264 ISL62872 G9334ADJ & MOS MOS (AO4710) MOS (AO3413) MOS (AO6402) AO3413
P44 P45 P47 P43 P22 P43 P22 P22




+VGPU_CORE (20A) +VGPU_IO (4.5A) +1V (3A) +1.5V_GPU (10A) +3_D (0.5A) +1.8V_GPU (3A) +5_GPU


Thermal Follow Chart
Power States
CONTROL
POWER PLANE VOLTAGE DESCRIPTION SIGNAL ACTIVE IN

B VIN +10V~+19V MAIN POWER ALWAYS ALWAYS B



+VCCRTC +3V~+3.3V RTC POWER ALWAYS ALWAYS NTC
Thermal
+3VPCU +3.3V EC POWER ALWAYS ALWAYS
Protection
+5VPCU +5V CHARGE POWER ALWAYS ALWAYS

+15V +15V CHARGE PUMP POWER ALWAYS ALWAYS

+3V_S5 +3.3V LAN/BT/CIR POWER S5_ON S0-S5 CPU 3V/5 V
H_ORICHOT# PM_THRMTRIP# SYS_SHDN#
CORE PWR
CPU WIRE-AND SYS PWR
+5V_S5 +5V USB POWER S5_ON S0-S5 H/W Throttling



+5V +5V HDD/ODD/Codec/TP/CRT/HDMI POWER MAINON S0

+3V +3.3V PCH/GPU/Peripheral component POWER MAINON S0
SML1ALERT#
+1.5VSUS +1.5V CPU/SODIMM CORE POWER SUSON S0-S3
PCH FAN Driver FAN
+0.75V_DDR_VTT +0.75V SODIMM Termination POWER MAINON S0

+VGFX_AXG variation Internal GPU POWER GFX_ON S0
SM-Bus
+1.8V +1.8V CPU/PCH/Braidwood POWER MAINON S0
C C

+1.5V +1.5V MINI CARD/NEW CARD POWER MAINON S0
EC
+1.1V_VTT +1.05V or +1.1V CPU VTT POWER MAINON S0 CPUFAN#

+1.05V +1.05V PCH CORE POWER MAINON S0

+VCC_CORE variation CPU CORE POWER VRON S0

LCDVCC +3.3V LCD POWER LVDS_VDDEN S0

+5V_GPU +5V SWITCHABLE PWM IC POWER dGPU_PWR_EN# Discrete enable

+GPU_CORE +0.9V~+1.1V GPU CORE POWER +3V_D Discrete enable

+GPU_IO +0.9V~+1.1V GPU I/O POWER PG_GPUIO_EN Discrete enable

+1.5V_GPU +1.5V VRAM CORE POWER PG_1.5V_EN Discrete enable

+1.8V_GPU +1.8V GPU_CRE/LVDS/PLL POWER +1.5V_GPU Discrete enable

+1V +1V DP/PEG POWER PG_1V_EN Discrete enable


D D




Quanta Computer Inc.
PROJECT : ZR7
Size Document Number Rev
3B
PWR Status & GPU PWR CRL & THRM
Date: Monday, February 22, 2010 Sheet 2 of 49
1 2 3 4 5 6 7 8
5 4 3 2 1



CLK GEN.
L40
[email protected]/2A/180ohm_6 150mA(30mil) L36
+1.5V +1.5V_CLK 80mA(20mil) PBY160808T/2A/180ohm_6
+VDDIO_CLK +1.05V
C697 C698 C719
D 11/19 Change U39 PN. C696 C702 C695 C700 D
.1u/16V_4 .1u/16V_4 .1u/16V_4
R617 .1u/16V_4 .1u/16V_4 10u/Y5V_8 10u/Y5V_8
*[email protected]_6 U39
Place each 0.1uF cap as close as
1 VDD_DOT possible to each VDD IO pin. Place
17 VDD_SRC VDD_SRC_I/O 15 the 10uF caps on the VDD_IO plane.
L41 24 18
BLM18AG601SN1D/200mA/600ohm_6 VDD_CPU VDD_CPU_I/O
20mil 5 VDD_27
+3V_CLK 29 3
+3V
CLK_SDATA
VDD_REF DOT_96
DOT_96# 4
CLK_BUF_DREFCLK
CLK_BUF_DREFCLK#
10
10
9/16
31 SDA
C723 C494 C720 CLK_SCLK 32 6 27M_CLK 18
SCL 27M CLK_VGA_27M_SS R595 *[email protected]_4
27M_SS 7 CLK_27M_SS 18
4.7u/10V_8 .1u/16V_4 .1u/16V_4 C718 *[email protected]/50V/COG_4
R598 33_4 CPU_SEL 30 10
10 CLK_ICH_14M REF_0/CPU_SEL SRC_1/SATA CLK_BUF_PCIE_3GPLL 10
SRC_1#/SATA# 11 CLK_BUF_PCIE_3GPLL# 10
SRC_2 13 CLK_BUF_DREFSSCLK 10
SRC_2# 14 CLK_BUF_DREFSSCLK# 10
C707 33p/50V_4 XTAL_IN 28 XTAL_IN
C C
XTAL_OUT 27 16 R579 10K_4 +3V
Y5 XTAL_OUT *CPU_STOP#
14.318MHz 2 VSS_DOT CPU_1 20 T46
8 VSS_27 CPU_1# 19 T45
9 VSS_SATA CPU_0 23 CLK_BUF_BCLK 10
C701 33p/50V_4 12 22
VSS_SRC CPU_0# CLK_BUF_BCLK# 10
21 VSS_CPU
26 25 CK_PWRGD_R
VSS_REF CKPWRGD/PD#
IDT: AL003197001 (ICS9LVS3197AKLFT) 33 GND
Realtek: AL000890000 (RTM890N-632-GRT)
Silego: AL000595000 (SLG8LV595VTR) ICS9LVS3197AKLFT/SLG8LV595V




+3V
CPU_CLK select SMBus CLK Enable +3V
B B
+1.05V

R406 R578
1K/F_4




2
R599 2.2K_4
*10K_4
3 1 CLK_SDATA CLK_SDATA 14,15,27 CK_PWRGD_R
10 ICH_SMBDATA




3
CPU_SEL Q27 Q48
2N7002D 2N7002D

R603 C722 39 VR_PWRGD_CK505# 2 R577
+3V 100K/F_4
10K_4 *10p/50V/COG_4




1
R407
2




2.2K_4
A A
0 1
3 1 CLK_SCLK
10 ICH_SMBCLK
Q28
CLK_SCLK 14,15,27
Quanta Computer Inc.
CPU_SEL CPU0/1=133MHz CPU0/1=100MHz
2N7002D
(default) PROJECT : ZR7
Size Document Number Rev
3B
Clock Generator
Date: Monday, February 22, 2010 Sheet 3 of 49
5 4 3 2 1
5 4 3 2 1



[email protected] --> ARD CPU ARRANDALE/CLARKSFIELD PROCESSOR (DMI,PEG,FDI)
[email protected] --> CFD CPU ARRANDALE/CLARKSFIELD PROCESSOR (CLK,MISC,JTAG)
[email protected] --> External VGA SKU [email protected] --> ARD CPU
Processor Compensation Signals [email protected] --> CFD CPU
U37A U37B
B26 R497 49.9/F_4 R523 20/F_4 H_COMP3 AT23
PEG_ICOMPI COMP3
A26 A16 CLK_CPU_BCLK 11
PEG_ICOMPO BCLK




MISC
A24 B27 R522 20/F_4 H_COMP2 AT24 B16
8 DMI_TXN0 DMI_RX#[0] PEG_RCOMPO COMP2 BCLK# CLK_CPU_BCLK# 11
C23 A25 R498 750/F_4
8 DMI_TXN1 DMI_RX#[1] PEG_RBIAS




CLOCKS
B22 PEG_RXN[0..15] 16 R123 49.9/F_4 H_COMP1 G16 AR30
8 DMI_TXN2 DMI_RX#[2] PEG_RXN0 COMP1 BCLK_ITP T30
8 DMI_TXN3 A21 K35 AT30 T34
D DMI_RX#[3] PEG_RX#[0] PEG_RXN1 R520 49.9/F_4 H_COMP0 BCLK_ITP# D
J34 AT26
PEG_RX#[1] PEG_RXN2 COMP0
8 DMI_TXP0 B24 J33 E16 CLK_PCIE_3GPLL 10
DMI_RX[0] PEG_RX#[2] PEG_RXN3 PEG_CLK
8 DMI_TXP1 D23 G35 D16 CLK_PCIE_3GPLL# 10
DMI_RX[1] PEG_RX#[3] PEG_CLK#




DMI
B23 G32 PEG_RXN4 AH24
8 DMI_TXP2 DMI_RX[2] PEG_RX#[4] PEG_RXN5 T40 SKTOCC# DPLL_REF_SSCLK_R
A22 F34 A18 R496 [email protected]_4
8 DMI_TXP3 DMI_RX[3] PEG_RX#[5]
PEG_RX#[6]
F31 PEG_RXN6 PCIE 16X DPLL_REF_SSCLK