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1 1
Compal Confidential
2 2
PAWGE Schematics Document
AMD APU Zacate-FT1 + FCH Hudson-M3L + GPU RobsonXT
3
2011-11-21 3
REV:1.0
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/06/30 Deciphered Date 2012/06/30 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8681P
Date: Tuesday, November 29, 2011 Sheet 1 of 48
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A B C D E
QIWG5
Compal confidential
File Name : PAWGE LS7981P CardReader/B
LS7982P USB/B
LS7983P PWR/B
1
QIWG6 1
LVDS Conn.
Memory BUS(DDRIII) 200pin DDRII-SO-DIMM X2 LS7981P CardReader/B
page 22
LS7982P USB/B
AMD Brazos APU Single Channel BANK 0, 1, 2, 3 page 8,9 LS7983P PWR/B
CRT Conn. FT1 1.5V DDRIII 1333 LS7984P LED/B
page 24
LS7985P ODD/B
BGA 413-Ball
AMDRosbon XT_M2 HDMI Conn. 19mm x 19mm
page 23
page 5,6,7
VRAM 64*16 x4 PCI-E GPP GEN2
DDR3*4
x4 UMI Gen. 2
page 15 ~ 21
2Channel Speaker
page 27
2
Audio Codec Internal MIC 2
page 27
Hudson M3L AZALIA CX20671
page 27
BGA 656-Ball Audio Jacks
23mm x 23mm Stereo
HeadPhone Output
4 * x1 PCI-E 1.0 10*USB2.0
Microphone Input
CMOS Camera page 22
WLAN &WiMax page 10,11,12,13,14 2*SATA serial BlueTooth CONN page 28
page 29
USB PORT 2.0 x2(Left) page 33
GIGA LAN LPC BUS
RTL8111/8105 USB PORT 3.0 x2(Right) page 34
page 25,26
SPI ROM WLAN/WiMAX
3
page 11
EC 3
ENE KB9012
PCI Express USB(WiMAX) page 30 Card Reader
Realtek RTS5178
Mini card Slot 1 PCI-E(WLAN) SD/MMC
WLAN/WiMAX page 29 Daoughter board
Int.KBD
page 32
Touch Pad
page 32
SATA3.0 HDD CONN
page 28
Thermal Sensor
4
EMC1403 page 29 SATA ODD CONN
page 28 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/06/30 Deciphered Date 2012/06/30 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8681P
Date: Tuesday, November 29, 2011 Sheet 2 of 48
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A B C D E
Voltage Rails FCH Hudson-M3L Brazos FCH Hudson-M3L
Power Plane Description S1 S3 S5 USB Port List PCIE Port List SATA Port List
VIN Adapter power supply (19V) N/A N/A N/A USB1.1 PCIE0 SATA0 HDD
B+ AC or battery power rail for power circuit. N/A N/A N/A
Port0 NC PCIE1 SATA1 ODD
APU
+APU_CORE Core voltage for CPU (0.7-1.2V) ON OFF OFF GPU
+APU_CORE_NB 1.0V switched power rail ON OFF OFF Port1 NC PCIE2 PCIE x4 SATA2 NC
1 1
+1.5V 1.5V power rail for CPU VDDIO and DDRIII ON ON OFF
USB2.0 PCIE3 SATA3 NC
+0.75VS 0.75VS switched power rail for DDR terminator ON OFF OFF
+1.0VS 1.0V switched power rail for NB VDDC & VGA ON OFF OFF Port0 Right USB PCIE0 LAN SATA4 NC
+1.1VS 1.1VS switched power rail ON OFF OFF
Port1 Right USB PCIE1 WLAN SATA5 NC
FCH
+1.8VS 1.8V switched power rail ON OFF OFF
+3VALW 3.3V always on power rail ON ON ON* Port2 Mini-PCIE PCIE2 NC
+3V_LAN 3.3V power rail for LAN ON ON(WOL) OFF
Port3 USB Camera PCIE3 NC
+3VS 3.3V switched power rail ON OFF OFF
+5VALW 5V always on power rail ON ON ON* Port4 NC
+5VS 5V switched power rail ON OFF OFF
Port5 CardReader
+VSB VSB always on power rail ON ON ON*
+RTCVCC RTC power ON ON ON Port6 BT
+1.1VALW 1.1V always on power rail ON ON ON*
Port7 NC
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Port8 NC
2 Port9 NC BOM Structure 2
EC SM Bus1 address EC SM Bus2 address
Port10 Left USB1
UMA@ : UMA only
Device Address HEX Device Address HEX Left USB2 PX@ : DIS muxluss PX 4.0
Smart Battery 0001-011xb 15H EMC1412-2 (dGPU) 1111-100xb F8H
Port11
9AH
Robson@ : Robson GPU
EMC1403-2(DDR,WLAN) 1001-101xb Port12 NC
SB-TSI 1001-100xb 98H
GIGA@ : RTL8111 1000
Port13 NC 8105@ : RTL8105 10/100
DIMM@ : DIMM select
SM Bus Controller 0 (FCH_SMB1 ~ FCH_SMB4, SMB_ALERT#)
CMOS@ : USB camera
BT@ : BT function
Device Address HEX ME@ : ME components
APU SIC/SID (FCH_SMB3)
X76@, H1G@, H512@, S1G@, S512@ : VRAM
H_THERMTRIP# (FCH_ALERT#)
45@ : 45 Level
HDMI@ : HDMI function
non HDMI@ : HDMI function
AN@ : Apple + Nokia ear phone combo
3
SM Bus Controller 1 (FCH_SMB0)
A@ : Apple ear phone 3
PCB@ : PCB PN
Device Address HEX 14@ : 14"
DDR DIMM1 (FCH_SMB0) 1001-000xb
15@ : 15"
90
DDR DIMM2 (FCH_SMB0) 1001-001xb
BBH@ : BBH
92
WLAN (FCH_SMB0)
nonBBH@@ : nonBBH@
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/06/30 Deciphered Date 2012/06/30 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8681P
Date: Tuesday, November 29, 2011 Sheet 3 of 48
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5 4 3 2 1
Without BACO option :
Power-Up/Down Sequence PXS_RST# : Low -> Reset dGPU ; High ->Normal operation
1. All the ASIC supplies must fully reach their respective nominal voltages within 20 ms of the start of the ramp-up PXS_PWREN : Low -> dGPU Power OFF ; High -> dGPU Power ON
sequence, though a shorter ramp-up duration is preferred.
BACO option :
2. VDDR3 should ramp-up before or simultaneously with VDDC. PXS_RST# : High ->Normal operation (dGPU is not reset on BACO mode)
PXS_PWREN : Low -> dGPU Power OFF ; High -> dGPU Power ON (always High)
3. For LVDS, DPx_VDD10 should ramp-up before DPx_VDD18 and the PCIe Reference clock should begin before
D DPx_VDD18. For power-down, DPx_VDD18 should ramp-down before DPx_VDD10. dGPU Power Pins Voltage PX 3.0 BACO Mode Max current
D
4. The external pull-ups on the DDC/AUX signals (if applicable) should ramp-up before or after both VDDC and PCIE_PVDD, PCIE_VDDR, TSVDD, VDDR4, VDD_CT, 1.8V OFF ON 1679mA
VDD_CT have ramped up. DPE_PVDD, DP[F:E]_VDD18, DP[D:A]_PVDD,
DP[D:A]_VDD18, AVDD, VDD1DI, A2VDDQ, VDD2DI,
5.VDDC and VDD_CT should not ramp-up simultaneously. (e.g., VDDC should reach 90% before VDD_CT starts to
DPLL_PVDD, MPV18, and SPV18
ramp-up (or vice versa).)
DP[F:E]_VDD10, DP[D:A]_VDD10, DPLL_VDDC, and 1.0V OFF ON 575mA
SPV10
PCIE_VDDC 1.0V OFF ON 2A
VDDR3(3.3VGS) Note: Do not drive any IOs before VDDR3 is ramped up.
VDDR3 , and A2VDD 3.3V OFF ON 190mA
BIF_VDDC (current consumption = [email protected], in Same as OFF ON 70mA
PCIE_VDDC(1.0V) BACO mode) VDDC Same as
PCIE_VDDC
BIF_VDDC=VGA_CORE When GPU enable
BIF_VDDC=1.0V When BACO
C
VDDR1(1.5VGS) VDDR1 1.5V OFF OFF 2.8A
C
VDDC/VDDCI 1.12V OFF OFF 12.9A
VDDC/VDDCI(1.12V)
VDD_CT(1.8V)
PXS_RST# PE_EN BACO Switch
iGPU dGPU
PERSTb BIF_VDDC
PXS_PWREN
REFCLK PX_mode
B +3.3VALW MOS
+3.3VGS B
Straps Reset 1
+1.5V SI4800
+1.5VGS
Straps Valid +1.0V +1.0VGS
Regulator
2 3
Global ASIC Reset
+B Regulator
+VGA_CORE
+1.8V +1.8VGS
T4+16clock
SI4800
5 4
PWRGOOD
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/06/30 Deciphered Date 2012/07/14 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
dGPU Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8681P
Date: Tuesday, November 29, 2011 Sheet 4 of 48
5 4 3 2 1
5 4 3 2 1
AAAU6 PCB@ AAAU22 E1200@ BBBU22 E1800@
PCB 0R3 LA-8681P REV0 M/B EM1200GBB22GV EM1800GBB22GV
U22B
+1.8VS
C508 1 HDMI@ 0.1U_0402_16V7K HDMI_TX2P_C DP_ZVSS R398 1 2 150_0402_1%
DISPLAYPORT 1
<23> HDMI_TX2P 2 A8 TDP1_TXP0 DP_ZVSS H3
C509 1 0.1U_0402_16V7K HDMI_TX2N_C
DP MISC
<23> HDMI_TX2N 2 B8
HDMI@ TDP1_TXN0
DP_BLON G2 APU_ENBKL <22>
R404 1 2 1K_0402_5% APU_DBREQ# C510 1 HDMI@ 0.1U_0402_16V7K
2 HDMI_TX1P_C B9 H2
<23> HDMI_TX1P TDP1_TXP1 DP_DIGON APU_ENVDD <22>
C511 1 2 0.1U_0402_16V7K HDMI_TX1N_C A9 H1
D APU_SVC <23> HDMI_TX1N TDP1_TXN1 DP_VARY_BL APU_BLPWM <22> D
R399 1 2 1K_0402_5% HDMI@
C512 1 HDMI@ 0.1U_0402_16V7K
2 HDMI_TX0P_C D10
APU_SVD <23> HDMI_TX0P HDMI_TX0N_C TDP1_TXP2
R400 1 2 1K_0402_5% C513 1 2 0.1U_0402_16V7K C10 B2
<23> HDMI_TX0N TDP1_TXN2 TDP1_AUXP HDMI_CLK <23>
HDMI@ C2
APU_RST# HDMI_CLKP_C TDP1_AUXN HDMI_DATA <23>
R405 2 1 300_0402_5% C514 1 HDMI@ 0.1U_0402_16V7K
2 A10
<23> HDMI_CLKP TDP1_TXP3
C515 1 2 0.1U_0402_16V7K HDMI_CLKN_C B10 C1
APU_PWRGD <23> HDMI_CLKN TDP1_TXN3 TDP1_HPD HDMI_DET <23>
R401 2 1 300_0402_5% HDMI@
B5 A3 EDID_CLK
<22> LVDS_A2 LTDP0_TXP0 LTDP0_AUXP EDID_CLK <22>
R402 1 2 510_0402_1% TEST_25_L EDID_DATA
DISPLAYPORT 0
<22> LVDS_A2# A5 LTDP0_TXN0 LTDP0_AUXN B3 EDID_DATA <22>
R403 1 2 1K_0402_5% TEST36 D6 D3 LTDP0_HPD R406 1 2 100K_0402_5%
<22> LVDS_A1 LTDP0_TXP1 LTDP0_HPD
<22> LVDS_A1# C6
LTDP0_TXN1
DAC_RED C12 DAC_RED <24>
A6 D13 R407 1 2 150_0402_1%
<22> LVDS_A0 LTDP0_TXP2 DAC_REDB
<22> LVDS_A0# B6 A12 DAC_GRN <24>
+3VS LTDP0_TXN2 DAC_GREEN R408 1
B12 2 150_0402_1%
DAC_GREENB
D8 A13
VGA DAC
<22> LVDS_ACLK LTDP0_TXP3 DAC_BLUE DAC_BLU <24>
C8 B13 R409 1 2 150_0402_1%
<22> LVDS_ACLK# LTDP0_TXN3 DAC_BLUEB
R510 1 2 4.7K_0402_5% EDID_CLK
<10> APU_CLK V2 E1 CRT_HSYNC <24>
R511 1 EDID_DATA CLKIN_H DAC_HSYNC
2 4.7K_0402_5% <10> APU_CLK# V1 E2 CRT_VSYNC <24>
CLKIN_L DAC_VSYNC
R410 1 2 1K_0402_5% APU_PROCHOT#
CLK
<10> APU_DISP_CLK D2 DISP_CLKIN_H DAC_SCL F2 CRT_DDC_CLK <24>
<10> APU_DISP_CLK# D1 DISP_CLKIN_L DAC_SDA D4 CRT_DDC_DATA <24>
R411 1 2 1K_0402_5% APU_ALERT#_R
J1 D12 DAC_ZVSS R413 1 2 499_0402_1%
<44> APU_SVC SVC DAC_ZVSS
<44> APU_SVD J2
SVD
SER
R1 PAD T66
R809 1 EC_SMB_CK2_R TEST4 AMD check list update
<16,29,30> EC_SMB_CK2 2 0_0402_5% P3 SIC TEST5 R2 PAD T67
TO EC R810 1 2 0_0402_5% EC_SMB_DA2_R P4 R6 20101110
<16,29,30> EC_SMB_DA2 SID TEST6
T5 PAD T68