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UM7B DISCRETE SYSTEM DIAGRAM 14.318MHz
+3V/+5V CLOCK GEN
A (RT8206BGQW) PG.3 A
PG.42
+1.05V SODIMM1 DDR3 INTEL
1.05V_PCH(RT8209A) Max. 4GB THERMAL
PG.48
PG.13
Channel A
Arrandale ATI PG.16
CPU Core PCI-E x16 PARK-S3 HDMI
(ADP3212) 37.5mm X 37.5mm HDMI PG.28
PG.45 SODIMM2 DDR3 989pin PGA 23mm X 23mm
VGA Core/+1.1V Max. 4GB CRT CRT
VGA_ATI park(RT8208A) PG.14
Channel B TDP 35W TDP 8W PG.23
PG.49 LVDS
PG.4~7 PG.15~19 LVDS PG.22
+1.5V/+0.75V DDR3 800MHz
1.5_DDR/0.75(RT8207A) DMI
B
PG.43 VRAM B
+1.05VTT/+1.8V 64Mx16x8,64bit
PG.20,21
1.05V_VTT(RT8204B) FAN & THERMAL
PG.44 GMT G990/
Charger SATA0
EMC1422-1-AIZL-TR PG.37
Charger (ISL88731)
HDD
PG.41
INTEL PCH PG.35
Ibex Peak-m
PCI-E x 1
27mm X 25mm
LANE6 LANE2
1071pin FCBGA USB2.0 Ports Webcam
C
LAN WLAN USB 2.0 TDP 5W X2
C
Atheros/AR8152 PORT4 PG.24, 33 PG.22
10/100 PG.38 PG.32 USB 2.0 PORT1,2 PORT11
PORT12 PORT8
SATA4
Card Reader BT Stackup
PG.8~12 RTS5138 BT365
USB+eSATA USB 2.0 PG.25 PG.32
TOP
Combo port PORT0 GND
PG.33 Azalia IN1
LPC Speaker IN2
PG.26
D
KBC AUDIO VCC D
ITE 8502 PG.29 CODEC BOT
HP/MIC
PG.27
ALC269-VB2-GR Quanta Computer Inc.
KB TP 1M ROM 4M ROM Analog MIC
PG.34 PG.34 PG.30 PG.30 PG.26 PG.26 PROJECT : UM7 DIS
Size Document Number Rev
3A
BLOCK DIAGRAM
Date: Wednesday, February 03, 2010 Sheet 1 of 52
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
Table of Contents Power States
CONTROL
PAGE DESCRIPTION POWER PLANE VOLTAGE PAGE DESCRIPTION ACTIVE IN
SIGNAL
1 Schematic Block Diagram
2 Front Page +PWR_SRC 10V~+19V 23,42,43,44,45,46,49,50 MAIN POWER S0~S5
3 Clock Generator
+RTC_CELL +3.0V~+3.3V 09,12,30,31 RTC S0~S5
4-7 PROCESSER Arrandale
A 8-12 PCH S0~S5 A
13-14 DDRIII SO-DIMM(204P)
+5V_ALW +5V 37,43,44,47,48 LARGE POWER ALW_ON S0~S5
15-21 ATI park
22 LCD CONN W/CCD +3.3V_ALW +3.3V 30,31,37,42,43,45,47,48 8051 POWER 3.3V_ALW_ON S0~S5
23 CRT CONN
+5V_SUS +5V 12,25,34,37,43,44,45,46,47,49,50 SLP_S5# CTRLD POWER SUS_ON
24 Right side USB
25 Cardreader (RTS5138) +3.3V_SUS +3.3V 03,08,09,10,11,12,23,35,37,39,41,46,47,50 SLP_S5# CTRLD POWER SUS_ON
26 Azalia (ALC269)
+1.5V_SUS +1.5V 04,06,14,15,44,47 SODIMM POWER SUS_ON
27 Audio Connecter
28 HDMI CONN +0.75V_DDR_VTT +0.75V 14,15,44 SODIMM POWER RUN_ON
29 SIO(ITE8502)
+5V_RUN +5V 08,12,23,24,27,28,29,35,36,3738,47 SLP_S3# CTRLD POWER RUN_ON
30 FLASH / RTC
3,4,8,9,10,11,12,14,15,23,24,26,27,28,29,30
31 Blank Page +3.3V_RUN +3.3V ,31,33,34,36,37,38,39,41,47 SLP_S3# CTRLD POWER RUN_ON
32 MINI-Card (WLAN)+BT
+1.8V_RUN +1.8V 6,12,45 SDVO POWER RUN_ON
33 ESATA & Left USB
B 34 TP / KEYBOARD +1.05V_VTT +1.1V 4,6,11,12,45,46 CPU POWER RUN_ON B
35 SATA HDD
+1.5V_RUN +1.5V 12,33,47 PCH/Min Card RUN_ON
36 SWITCH LED
37 FAN / THERMAL +1.05V_PCH +1.05V 3,8,9,10,12,49 PCH POWER RUN_ON
38 LAN(AR8152/RJ-45)
+VCC_CORE +0.7V~+1.77V 6,46 CPU CORE POWER IMVP_VR_ON
39 Blank Page
LCDVCC_TST_EN
40 System Reset Circuit +LCDVCC +3.3V 23 LCD Power & ENVDD
41 Charger (MAX8731)
42 3V/5V (RT8206BGQW)
43 1.5_DDR/0.75(RT8207A)
44 1.05V_VTT(RT8204B)
45 CPU CORE(ADP3212)
46 Run Power Switch
47 DCin & Batt
48 1.05V_PCH(RT8209A)
C C
49 GFX_VCORE (ADP3211)
50 Power Block Diagram GND PLANE PAGE DESCRIPTION
51 Power sequence Block
GND ALL
D D
Quanta Computer Inc.
PROJECT : UM7 DIS
Size Document Number Rev
3A
BLOCK DIAGRAM
Date: Wednesday, February 03, 2010 Sheet 2 of 52
1 2 3 4 5 6 7 8
5 4 3 2 1
D D
+3.3V_RUN
U9
L27 BLM21PG600SN1D
40mil +3.3V_CLK_VDD 1
805 VDD_USB
5 VDD_LCD CPU-0 23 CLK_BUF_BCLKP [9]
17 VDD_SRC CPU-0# 22 CLK_BUF_BCLKN [9]
C294 C283 C289 C191 C192 C231 24 VDD_CPU
29 20
10U/10V_8 0.1U/16V 0.1U/16V 0.1U/16V 0.1U/16V 0.1U/16V +VDDIO_CLK 15
18
VDD_REF
VDD_SRC_IO
VDD_CPU_IO
CK505 CPU-1
CPU-1# 19
9 VSS_SATA
QFN32 DOT96T_LPR 3 CLK_BUF_DREFCLKP [9]
2 VSS_USB DOT96C_LPR 4 CLK_BUF_DREFCLKN [9]
8 VSS_LCD
12 VSS_SRC SRC-1 13 CLK_BUF_PCIE_3GPLLP [9]
21 VSS_CPU SRC-1# 14 CLK_BUF_PCIE_3GPLLN [9]
26 VSS_REF
+3.3V_RUN 10
SATA CLK_BUF_DREFSSCLKP [9]
SATA# 11 CLK_BUF_DREFSSCLKN [9]
C C
R408 10K 16 6 CLK_VGA_27M_R R186 33
CPU_STOP# 27MHz_nonSS CLK_VGA_27M [16]
CK_PWRGD_R 25 7 CLK_VGA_27M_SS_R R187 *33_NC
CK_PWRGD/PD#_3.3 27MHz_SS CLK_VGA_27M_SS [16]
CLK_PCH_14M R174 33 CPU_SEL 30
[9] CLK_PCH_14M REF_0/CPU_SEL
close to CLK DIS only
XTAL_OUT 27
XTAL_IN XOUT
28 XIN
[16,29,37] SMBDAT2 31 SDATA GND 33
[16,29,37] SMBCLK2 32 SCLK
ICS9LRS3197AKLFT
AL003197000IC OTHER(32P)ICS9LRS3197AKLFT(QFN)
AL8SP585000IC OTHER(32P)SLG8SP585VTR(QFN)
C268
AL8SP590000IC OTHER(32P)SLG8SP590VTR(QFN)
+1.05V_PCH
CLK_PCH_14M
L24 BLM21PG600SN1D 8mA
*27P/50V_NC +VDDIO_CLK
EMI 805
B C244 C218 C210 B
10U/10V_8 0.1U/16V *0.1U/16V_NC
Y1
XTAL_IN 1 2 XTAL_OUT
14.318MHZ
2
C212
C232 27P Place each 0.1uF cap as close as
27P possible to each VDD IO pin. Place
+3.3V_RUN 1 the 10uF caps on the VDD_IO plane.
R147
1K
CK_PWRGD_R
+3.3V_RUN
Q2
3
2
2N7002W-7-F R152
2 *100K_NC R184
[45] VR_PWRGD_CLKEN#
*4.7K_NC
A A
1
1
CPU_SEL
PIN 30 CPU_0 CPU_1
2
R179 Quanta Computer Inc.
4.7K 0(default) 133MHz 133MHz
PROJECT : UM7 DIS
1
1(0.7V-1.5V) 100MHz 100MHz Size Document Number Rev
3A
Clock Generator
Date: Wednesday, February 03, 2010 Sheet 3 of 52
5 4 3 2 1
1 2 3 4 5 6 7 8
change PN
U16A
B26 PEG_COMP R289 49.9/F
PEG_ICOMPI
PEG_ICOMPO A26
[10] DMI_TXN0 A24 DMI_RX#[0] PEG_RCOMPO B27
[10] DMI_TXN1 C23 DMI_RX#[1] PEG_RBIAS A25 PEG_RBIAS R290 750/F PAD on trace
[10] DMI_TXN2 B22 DMI_RX#[2]
A21 K35 U16B
[10] DMI_TXN3 DMI_RX#[3] PEG_RX#[0] PEG_RXN0 [15] TP26
J34 R79 20/F H_COMP3 AT23 A16
PEG_RX#[1] PEG_RXN1 [15] COMP3 BCLK CLK_CPU_BCLKP [11]
B24 J33 R78 20/F H_COMP2 AT24 B16
[10] DMI_TXP0 DMI_RX[0] PEG_RX#[2] PEG_RXN2 [15] COMP2 BCLK# CLK_CPU_BCLKN [11]
D23 G35 R294 49.9/F H_COMP1 G16
A [10] DMI_TXP1
B23
DMI_RX[1] PEG_RX#[3]
G32
PEG_RXN3 [15]
R102 49.9/F H_COMP0 AT26 COMP1 MISC AR30 For ITP CLk
TP25 A
[10] DMI_TXP2 DMI_RX[2] PEG_RX#[4] PEG_RXN4 [15] COMP0 BCLK_ITP
[10] DMI_TXP3 A22 DMI_RX[3] PEG_RX#[5] F34 PEG_RXN5 [15] [29] H_CPUDET# AH24 SKTOCC# BCLK_ITP# AT30
PEG_RX#[6] F31 PEG_RXN6 [15]
D24 D35 E16
[10]
[10]
DMI_RXN0
DMI_RXN1 G24
DMI_TX#[0]
DMI_TX#[1] DMI PEG_RX#[7]
PEG_RX#[8] E33
PEG_RXN7 [15]
PEG_RXN8 [15]
H_CATERR# AK14 CATERR#
CLOCKSPEG_CLK#
PEG_CLK
D16
CLK_PCIE_3GPLLP [9]
CLK_PCIE_3GPLLN [9]
[10] DMI_RXN2 F23 DMI_TX#[2] PEG_RX#[9] C33 PEG_RXN9 [15] [11] H_PECI AT15 PECI
H23 D32 H_PROCHOT# AN26 THERMAL A18
[10] DMI_RXN3 DMI_TX#[3] PEG_RX#[10] PEG_RXN10 [15] PROCHOT# DPLL_REF_SSCLK
B32 PEG_RXN11 [15] [11] H_THERM AK15 A17 DIS connect GND
PEG_RX#[11] THERMTRIP# DPLL_REF_SSCLK#
[10] DMI_RXP0 D25 DMI_TX[0] PEG_RX#[12] C31 PEG_RXN12 [15]
[10] DMI_RXP1 F24 B28 PEG_RXN13 [15]
DMI_TX[1] PEG_RX#[13] H_CPURST#
[10] DMI_RXP2 E23 DMI_TX[2] PEG_RX#[14] B30 PEG_RXN14 [15] AP26 RESET_OBS# SM_DRAMRST# F6 DDR3_DRAMRST# [13,14]
[10] DMI_RXP3 G23 DMI_TX[3] PEG_RX#[15] A31 PEG_RXN15 [15] [10] PM_SYNC AL15 PM_SYNC
J35
TP8 AN14
AN27
VCCPWRGOOD_1 DDR3 SM_RCOMP[0]
AL1 SM_RCOMP_0 R353
AM1 SM_RCOMP_1 R352
100/F
24.9/F
PEG_RX[0] PEG_RXP0 [15] [11] H_PWRGOOD VCCPWRGOOD_0 SM_RCOMP[1]
PEG_RX[1]
H34
H33
PEG_RXP1 [15] [10] PM_DRAM_PWRGD
PM_DRAM_PWRGD AK13
SM_DRAMPWROK MISC SM_RCOMP[2]
AN1 SM_RCOMP_2 R351
R107
130/F
10K
PEG_RX[2] PEG_RXP2 [15] +1.05V_VTT
E22 FDI_TX#[0] PEG_RX[3] F35 PEG_RXP3 [15] TP16 AM26 TAPPWRGOOD PM_EXT_TS#[0] AN15 PM_EXTTS#0 [13]
D21 G33 PEG_RXP4 [15] AP15 PM_EXTTS#1 [14]
FDI_TX#[1] PEG_RX[4] PM_EXT_TS#[1] R108 10K
D19 E34 PEG_RXP5 [15] [40] H_VTTPWRGD AM15 +1.05V_VTT
FDI_TX#[2] PEG_RX[5] CPU_PLTRST# AL14 VTTPWRGOOD
D18 FDI_TX#[3] PEG_RX[6] F32 PEG_RXP6 [15] [10,15,29,32,38] PLTRST# RSTIN#
G21 D34 R132 1.5K AT28
FDI_TX#[4] PEG_RX[7] PEG_RXP7 [15] PRDY# TP6
Intel(R) FDI
E19 FDI_TX#[5] PEG_RX[8] F33 PEG_RXP8 [15] PREQ# AP27 TP9
R105 750/F PREQ TP not too long
F21 FDI_TX#[6] PEG_RX[9] B33 PEG_RXP9 [15] PWR MANAGEMENT TCK AN28 TP17
PCI EXPRESS -- GRAPHICS
G18 D31 PEG_RXP10 [15]
FDI_TX#[7] PEG_RX[10]
A32 PEG_RXP11 [15] TP19 AP28 TP20
PEG_RX[11] TMS
C30 PEG_RXP12 [15]
PEG_RX[12] XDP_TRST#
D22 A28 AT27
B
C21
D20
FDI_TX[0]
FDI_TX[1]
FDI_TX[2]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
B29
A30
PEG_RXP13 [15]
PEG_RXP14 [15]
PEG_RXP15 [15]
TP10
TP5
AJ22
AK22
BPM#[0]
BPM#[1]
JTAG & BPM TRST#
TDI
AT29
TP24
TP12 B
C18 TP21 AK24 AR27 TP13
FDI_TX[3] PEG_TXN0_C C505 0.1U/10V BPM#[2] TDO XDP_TDI_M
G22 FDI_TX[4] PEG_TX#[0] L33 PEG_TXN0 [15] TP2 AJ24 BPM#[3] TDI_M AR29 TP22
E20 M35 PEG_TXN1_C C500 0.1U/10V AJ25 AP29 XDP_TDO_M
FDI_TX[5] PEG_TX#[1] PEG_TXN1 [15] TP14 BPM#[4] TDO_M TP18
F20 M33 PEG_TXN2_C C499 0.1U/10V AH22
FDI_TX[6] PEG_TX#[2] PEG_TXN2 [15] TP23 BPM#[5]
G19 M30 PEG_TXN3_C C497 0.1U/10V AK23
FDI_TX[7] PEG_TX#[3] PEG_TXN3 [15] TP3 BPM#[6]
L31 PEG_TXN4_C C490 0.1U/10V AH23 AN25 2 1
PEG_TX#[4] PEG_TXN4 [15] TP15 BPM#[7] DBR# XDP_DBRESET# [10]
FDI_FSYNC0 F17 K32 PEG_TXN5_C C489 0.1U/10V *short0402_NC2 1 R370
FDI_FSYNC[0] PEG_TX#[5] PEG_TXN5 [15]
FDI_FSYNC1 E17 M29 PEG_TXN6_C C485 0.1U/10V IC,AUB_CFD_rPGA,R1P0
FDI_FSYNC[1] PEG_TX#[6] PEG_TXN6 [15]
J31 PEG_TXN7_C C483 0.1U/10V
PEG_TX#[7] PEG_TXN7 [15]
FDI_INT C17 K29 PEG_TXN8_C C475 0.1U/10V
FDI_INT PEG_TX#[8] PEG_TXN8 [15]
H30 PEG_TXN9_C C474 0.1U/10V
PEG_TX#[9] PEG_TXN9 [15]
FDI_LSYNC0 F18 H29 PEG_TXN10_C C471 0.1U/10V
FDI_LSYNC[0] PEG_TX#[10] PEG_TXN10 [15]
FDI_LSYNC1 D17 F29 PEG_TXN11_C C470 0.1U/10V
FDI_LSYNC[1] PEG_TX#[11] PEG_TXN11 [15]
E28 PEG_TXN12_C C467 0.1U/10V
PEG_TX#[12] PEG_TXN12 [15]
D29 PEG_TXN13_C C465 0.1U/10V
PEG_TX