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A B C D E
Last Schematic Update Date:
TITLE SHEET
4
03/01/2001 COVER SHEET 1 4
AMD-K7 SOCKET-A 2,3
MS-6378
NORTH BRIDGE (VIA VT8361) 4,5,6
Version 1.0 SOUTH BRIDGE (VIA VT82C686B) 7,8
CPU: AMD Socket-462 Processor CLOCK SYNTHESIZER 9
SDRAM DIMMS 10
System Chipset: VIA KLE133(North) PCI SLOTS 11
+ 686B (South) AMR/CNR & ISA SLOT 12
3 3
AC'97 CODEC 13
Expansion: PCI * 3 AUDIO/GAME PORT 14
CNR * 1 USB, PS2 K/B & MOUSE 15
On Board Device:
IDE CONNECTORS 16
COM/LPT PORTS, RI, WOL, WOM & FAN 17
AC97 Codec ALC100P VGA CONNECTOR 18
Optional: ISA * 1
VRM SC1155 19
2
LINEAR REGULATOR & STR 20 2
ERP BOM Function Description FRONT PANEL 21
601-6378-04S MSI Standard: With CNR.
W/O ISA,LAN,STR. RTL8100 LAN CHIPSET 22
601-6378-03S MSI Option:A With ISA,LAN,CNR.
W/O STR. BYPASS CAPACITORS 23
601-6378-05S For Legend: With ISA,CNR,STR. W/O Lan.
Special Request:Legend SPEC. BLOCK DIAGRAM 24
601-6378-010
from 04S
MSI Standard: With CNR,STR.
W/O ISA,LAN. GPIO SPEC 25
601-6378-020 MSI Option:A With
from 03S ISA,LAN,CNR,STR. History I 26
1 1
For Actebis: w/o ISA,w/o LAN. Micro Star Restricted Secret
Title Rev
Special Request:I/O with Shield. Cover Page
Document Number 100
MS-6378
MICRO-STAR INT'L CO.,LTD. Last Revision Date:
Friday, March 23, 2001
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan Sheet
http://www.msi.com.tw 1 of 28
A B C D E
A B C D E
VCC_CORE VCC3
CPU1A VCC_CORE
-SDATA0 AA35 AE1 -A20M R39 R20
{4} -SDATA[0:63] -SDATA1 SDATA0 A20M -A20M {8}
W37 AG1 FERR 680 4.7K
-SDATA2 SDATA1 FERR -INIT
W35 AJ3 -INIT {8}
-SDATA3 SDATA2 INIT INTR -FERR R89 R90
Y35 AL1 INTR {8} -FERR {8}
-SDATA4 SDATA3 INTR -IGNNE 60.4RST 60.4RST
U35 AJ1 -IGNNE {8}
-SDATA5 SDATA4 IGNNE NMI
U33 AN3 NMI {8} C
-SDATA6 SDATA5 NMI -CPURST FERR R88
S37 AG3 -CPURST {8} B
-SDATA7 SDATA6 RESET -SMI
S33 AN5 -SMI {8} E Near socket-A
-SDATA8 SDATA7 SMI -STPCLK Q11
4 AA33 AC1 -STPCLK {8} 4
-SDATA9 SDATA8 STPCLK 2N3904S X_301RST
AE37
-SDATA10 SDATA9
AC33 AE3 CPU_PG {21}
-SDATA11 SDATA10 PWROK CPUCK C101 104P
AC37 CPUCLK {9}
-SDATA12 SDATA11
Y37
-SDATA13 SDATA12 APICCLK -CPUCK C100 104P
AA37 N1 -CPUCLK {9}
-SDATA14 SDATA13 PICCLK APICD0
AC35 N3
-SDATA15 SDATA14 PICD0/BYPASSCLK APICD1
S35 N5
-SDATA16 SDATA15 PICD1/BYPASSCLK
Q37
-SDATA17 SDATA16 COREFB- VCC3
Q35 AG13 COREFB- {19}
-SDATA18 SDATA17 COREFB- COREFB+ RN8
-SDATA19
N37
SDATA18 COREFB+
AG11 COREFB+ {19} Pull to 2.5V
J33 APICD0 1 2 VCC_CORE
-SDATA20 SDATA19 CPUCK APICCLK
G33 AN17 3 4
-SDATA21 SDATA20 CLKIN -CPUCK APICD1
G37 AL17 5 6
-SDATA22 SDATA21 CLKIN R77
E37 7 8
-SDATA23 SDATA22 X_1K
G35 AN19
-SDATA24 SDATA23 RSTCLK VREFMODE
Q33
SDATA24 RSTCLK
AL19
8P4R-330 NOPOP
2
4
6
8
-SDATA25 N33
-SDATA26 SDATA25 CLKOUT RN7 R78
L33 AL21
-SDATA27 SDATA26 K7CLKOUT -CLKOUT 8P4R-1K 270
N35 AN21
-SDATA28 SDATA27 K7CLKOUT
L37
-SDATA29 SDATA28
1
3
5
7
J37
-SDATA30 SDATA29
A37 AJ13 VREFMODE=Low=No voltage scaling
-SDATA31 SDATA30 ANALOG
E35
-SDATA32 SDATA31 VREFMODE
E31 AA5
-SDATA33 SDATA32 SYSVREFMODE VREF_SYS
E29 W5
-SDATA34 SDATA33 VREF_SYS
A27
-SDATA35 SDATA34 ZN VCC_CORE
A25 AC5
3
-SDATA36 SDATA35 ZN ZP RN6 VCC_CORE
3
E21 AE5
-SDATA37 SDATA36 ZP 8P4R-680 ZN R76 40.2RST
C23
-SDATA38 SDATA37 -PLLBP -STPCLK
C27 AJ25 1 2
-SDATA39 SDATA38 PLLBYPASS PLLBPCLK -A20M
A23 AN15 3 4
-SDATA40 SDATA39 PLLBYPASSCLK -PLLBPCLK -IGNNE ZP R54 40.2RST
A35 AL15 5 6
-SDATA41 SDATA40 PLLBYPASSCLK -CPURST
C35 7 8
-SDATA42 SDATA41 PLLMON1
C33 AN13
-SDATA43 SDATA42 PLLMON1 PLLMON2 RN10
-SDATA44
C31
SDATA43 PLLMON2
AL13 Push-pull compensation circuit
A29 AC3 -PLLTEST 8P4R-680
-SDATA45 SDATA44 PLLTEST INTR
C29 1 2
-SDATA46 SDATA45 -INIT
E23 3 4
-SDATA47 SDATA46 SCANCLK1 NMI
C25 S1 5 6
-SDATA48 SDATA47 SCANCLK1 SCANCLK2 -SMI VCC_CORE
E17 S5 7 8
-SDATA49 SDATA48 SCANCLK2 SINTVAL
E13 S3
-SDATA50 SDATA49 SCANINTEVAL SSHIFTEN
E11 Q5
-SDATA51 SDATA50 SCANSHIFTEN RN17
C15
-SDATA52 SDATA51 -FLUSH R53 680
E9 AA1 1 2
-SDATA53 SDATA52 DBRDY -DBREQ -PLLBP R104 680 -CLKOUT
A13 AA3 3 4
-SDATA54 SDATA53 DBREQ -FLUSH CLKOUT
C9 AL3 5 6
-SDATA55 SDATA54 FLUSH
A9 7 8
-SDATA56 SDATA55 TCK PLLMON1 R81 56
C21 Q1
-SDATA57 SDATA56 TCK TDI PLLMON2 R82 56
A21 U1
-SDATA58 SDATA57 TDI 8P4R-100
E19 U5
-SDATA59 SDATA58 TDO TMS TMS
C19 Q3 1 2
-SDATA60 SDATA59 TMS -TRST TCK RN18
C17 U3 3 4 Trace lengths of CLKOUT and
-SDATA61 SDATA60 TRST TDI 8P4R-510
A11 5 6
-SDATA62 SDATA61 -TRST -CLKOUT are between 2" and
A17 7 8
2
-SDATA63 SDATA62 VID0 2
A15
SDATA63 VID0
L1 VID0 {19} -PLLTEST
3"
L3 VID1 R19 510
VID1 VID1 {19}
L5 VID2
-DICLK0 VID2 VID2 {19} -DBREQ
W33 L7 VID3 R18 510 VREF_SYS is set at 50% VCC_CORE
{4} -DICLK[0:3] SDATAINCLK0 VID3 VID3 {19}
-DICLK1 J35 J7 VID4
-DICLK2 SDATAINCLK1 VID4 VID4 {19} COREFB+ of VCC_CORE ot CPU
E27 R79 10K
-DICLK3 SDATAINCLK2 R91
E15
SDATAINCLK3 FID0 100RST
W1 FID0 {3}
-DIVAL FID0 FID1 COREFB- R80 10K
AN33 W3 FID1 {3}
{4} -DIVAL SDATAINVAL FID1 FID2 VREF_SYS
Y1 FID2 {3}
-DOCLK0 FID2 FID3 -AIN0 R106 270
{4} -DOCLK[0..3] AE35 Y3 FID3 {3}
-DOCLK1 SDATAOUTCLK0 FID3 CB2 CM1
C37
-DOCLK2 SDATAOUTCLK1 -AIN1 R105 270 R92
A33
-DOCLK3 SDATAOUTCLK2 104P 105P 100RST
C11 U37
SDATAOUTCLK3 SCHECK0 -AOUT0 R55 X_1K
Y33
-DOVAL SCHECK1
AL31 L35
SDTATOUTVAL SCHECK2 -AOUT1 R56 X_1K
E33
-AIN0 SCHECK3
AJ29 E25
-AIN1 SADDIN0 SCHECK4 -DOVAL R116 270 VCC_CORE
AL29 A31
-AIN2 SADDIN1 SCHECK5
{4} -AIN[2:14] AG33 C13
-AIN3 SADDIN2 SCHECK6 -FILVAL R115 270
AJ37 A19
-AIN4 SADDIN3 SCHECK7 RN15
AL35
-AIN5 SADDIN4 -AOUT0 SSHIFTEN
AE33 J1 1 2 1 2
-AIN6 SADDIN5 SADDOUT0 -AOUT1 SINTVAL RN12 PLLBPCLK
AJ35 J3 3 4 3 4
-AIN7 SADDIN6 SADDOUT1 -AOUT2 SCANCLK1 8P4R-270 -PLLBPCLK
AG37 C7 5 6 5 6
-AIN8 SADDIN7 SADDOUT2 -AOUT3 -AOUT[2:14] {4} SCANCLK2
AL33 A7 7 8 7 8
-AIN9 SADDIN8 SADDOUT3 -AOUT4
AN37 E5
-AIN10 SADDIN9 SADDOUT4 -AOUT5
1
AL37 A5 8P4R-100
1
-AIN11 SADDIN10 SADDOUT5 -AOUT6
AG35 E7
-AIN12 SADDIN11 SADDOUT6 -AOUT7
AN29 C1
SADDIN12 SADDOUT7
-AIN13
-AIN14
AN35
AN31
SADDIN13 SADDOUT8
C5
C3
-AOUT8
-AOUT9
-CPURST CB1 104P
Micro Star Restricted Secret
SADDIN14 SADDOUT9 -AOUT10 Title Rev
G1
SADDOUT10 -AOUT11 PPGA_462 CPU (Signals)
{4} -AICLK AJ33 E1
SADDINCLK SADDOUT11 -AOUT12 Document Number 100
A3
CFWDRST SADDOUT12 -AOUT13 MS-6378
{4} CFWDRST AJ21 G5
CONNECT CLKFWDRST SADDOUT13 -AOUT14
{4} CONNECT AL23 G3 MICRO-STAR INT'L CO.,LTD. Last Revision Date:
PROCRDY CONNECT SADDOUT14 Friday, March 23, 2001
{4} PROCDRY AN23
-FILVAL PROCRDY -AOCLK No. 69, Li-De St, Jung-He City,
AJ31 E3
SFILLVAL SADDOUTCLK -AOCLK {4} Taipei Hsien, Taiwan Sheet
YSKT462P-I http://www.msi.com.tw 2 of 28
A B C D E
1
2
3
4
VCC3
8
6
4
2
A
A
2
4
6
8
RN20
RN21
for processor type
8P4R-680
treated as NC pins.
7
5
3
1
8P4R-4.7K
1
3
5
7
These 16 locations are
keying for forwards and
These key pins should be
backwards compatibility.
AJ7
AJ9
AA7
AK8
Y7
K8
AM8
AL7
K30
AL9
AH6
AN7
AH8
AH30
AD8
AD30
H32
H30
H28
H10
AF8
AF6
AF32
AF30
AF28
AF10
AG27
AG17
AG29
AG15
N7
H8
H6
F30
G23
G15
G17
G25
F8
AG9
AG7