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A8T/M SCHEMATIC R2.1
1 1
PAGE Content PAGE Content
SYSTEM PAGE REF. POWER PAGE REF.
4 AMD S1 CPU--HT 61 POWER_VCORE
5 AMD S1 CPU--CNTL 62 POWER_SYSTEM
6 AMD S1 CPU--DDR2 63 POWER_I/O_1.2VO & 1.0VO
7 AMD S1 CPU--PWR/GND 64 POWER_I/O_LDO
8 DDR2 SO-DIMM_0 65 POWER_I/O_DDR2
9 DDR2 SO-DIMM_1 66 POWER_VGA_CORE(Empty)
10 DDR2 ADDRESS TERMINATION 67 POWER_LOAD_SYSTEM
11 C51M--HT TO CPU 68 POWER_CHARGER
2 12 C51M--HT TO MCP 69 POWER_PIC 2


13 C51M--PCI-E 70 POWER_PROTECT
14 C51M--CRT & LVDS 71 POWER_SWITCH_+5VLCM
15 C51M--PWR/GND 72 POWER_DIAGRAM
16 VGA CONN
17 LVDS & INVERTER CONN
18 CRT & TV_OUT
19 MCP51--HT
20 MCP51--PCI
21 MCP51--IDE
22 MCP51--USB & HDA & GPIO
3
23 MCP51--PWR/GND 3
24 HDD & CD-ROM CONN
25 USB PORTS
26 SUPER I/O LPC47N217
27 BIOS & FIR
28 KBC 38857
29 SM BUS & POWER PORT
30 PCI-E--MINI CARD
31 PCI-E--NEW CARD
32 PCI--LAN RTL8110CL
33 RJ45 & RJ11
34 PCI--1394,CardReader R5C832
4 35 PCI--4 IN1 CON 4


36 AUDIO CODEC ALC660
37 AUDIO AMP G1420
38 MDC,B/T,TPM & DISCHG,HOLE
39 DVI CONN
40 ACIN, BAT, FAN, I/O PORT
41 SW & LED & TP
42 POWER-ON SEQUENCE
43 HISTORY
44 I/O PORT

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REVISION DATE: Friday, July 21, 2006 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: A8T 2.1 SHEET 1 OF 55 PAGE REF. RELEASE DATE : Albert Su
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A8T/M AMD S1/C51MV BLOCK DIAGRAM
BATTERY
1
TYPE IO PORT 1




3S2P
1394 USB MIC LINE_IN
40,44



AMD
638 POWER
4,5,6,7
SEQENCE RESET SM_BUS
LFB LFB LFB LFB 42 42 29
LVDS & INV
2 CON 17
HT X16 2


DDR2 533/667
Nvidia PCI-E DDR
CRT & TV
VGA VGA x16
DDR2 SDRAM 533/667MHz
SODIMM X2
+1.8V
.... CAP/RES
10
CON 18
CON G7x series CON
C51MV +0.9V
8,9


16 16 11,12,13,14,15 PCI EXPRESS X1
VGA BAORD
DVI Dual
CH. 39
HT X8
VCORE 61 USB2.0 MINI CARD NEW
USB x5 CARD
3 25 30 31 3
SYSTEM 62 PCI_BUS 3.3V, 33MHz
PATA BUS
MCP51
1.2VO & 1.0VO B/T ACZ
63 38
ODD 19,20,21,22,23
(Secondary) HDD CARDBUS LAN 1G
I/O LDO (Primary) 24
64
24 4 IN 1 RICOH RTL8110SBL
Camera R5C832
CARD 34 32
38
+1.8V & +0.9V READER
65 LPC, 33MHz 35
RJ11,RJ45
LOAD SYSTEM LAN IO CON
67 Codec
4 ADI1986A 1394 33 33
4
36 SLOT
SUPER I/O KEYBOARD TPM FWH 40
CHARGER BIOS
68 47N217 26 CONTROLLER
M38857 SW & LED &
28 38 27 AUDIO AMP MDC TOUCHPAD
G1420 CON DCIN
PIC CON
69
37 38 41 RTC
FAN CON. 40
PROTECT FIR INTERNAL
70 KEYBOARD LINE AC & BAT CON
27 30 OUT 40 H/W MONITOR
FAN CTRL 40
SWITCH 5VLCM THERMAL 70
71
MIC AMP
LM358 MIC_IN
5 DIAGRAM 37 40
5

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REVISION DATE: Friday, July 21, 2006 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: A8T 2.1 SHEET 2 OF 55 BLOCK DAIGRAM RELEASE DATE : Albert Su
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PCI Device IDSEL# REQ/GNT# Interrupts PC/PCI
SM_BUS ADDRESS : Thermal MAX6657 = 1001100x ( 98h )
Chipset (Host to PCI) (AD30 internal) n/a DDR_SODIMM0 = 1010000x ( A0h )
1 LAN -- Realtek AD17 1 C DDR_SODIMM1 = 1010001x ( A2h ) 1




1394 AD16 0 A
4 IN 1 0 B


MCP51_GPIO Use As Signal Name Power
MCP51_GPIO Use As Signal Name Power M38857_GPIO USE_AS SIGNAL_NAME Power
GPIO_47 GPI LOAD_TEST +3VS
GPIO_1 GPI PCB_ID2 +3VS P23 GPO MSK_INSTKEY# +3V
GPIO_48
GPIO_2 GPI KB_SCI# +3VSUS P22 GPO BAT_LEARN +3V
GPIO_49 GPO FWH_WP# +3VS
GPIO_3 GPI PWRLMT# +3VSUS P21 GPO +3V
GPIO_50 GPO LCD_VDD_EN_GM +3VS
GPIO_4 SUS_STAT# +3VSUS P20 GPO KBCRSM +3V
GPIO_51 GPO LCD_BACKEN_GM +3VS
2 GPIO_5 GPO 802_LED_EN# +3VSUS P42 GPO WATCHDOG +3V 2
GPIO_52 EDID_CLK_C51M +3VS
GPIO_6 GPO MCP_TV_EN +3VSUS P43 GPI SWDJ_EN +3V
GPIO_53 EDID_DATA_C51M +3VS
GPIO_7 GPO CB_SD# +3VSUS P44 GPO KBCPURST_3Q +3V
GPIO_54 GPO GPU_ON +3VS
GPIO_8 CR_VID0 +3VSUS P45 GPO KBC_GA20 +3V
GPIO_55 HA20GATE +3VS
GPIO_9 CR_VID1 +3VSUS P46 GPO KBSCI_3Q +3V
GPIO_56 KBDCPURST +3VS
GPIO_10 (CR_VID2) +3VSUS P47 GPI PM_CLKRUN# +3V
GPIO_57 SATA_LED# +3VS
GPIO_[11:16] (CPU_VID[0:5]) +3VSUS P50 GPI BAT_LLOW#_OC +3V
GPIO_58 CPU_THERMTRIP# +3VS
GPIO_17 (LID#) +3VSUS P51 GPI FAN1_TACH +3V
GPIO_59 PM_THERM# +3VS
GPIO_18 BATT_TALARM# +3VSUS P52 GPO KBDDT0 +3V
GPIO_60 GPI PCB_ID0 +3VS
GPIO_19 USB_OC#1 +3VSUS P53 GPO KBDDT1 +3V
GPIO_61 GPI PCB_ID1 +3VS
GPIO_20 GPO 1 Hz +3VSUS P54 GPI LID_KBC# +3V
GPIO_62 GPO IGP_SELECT +3VS
GPIO_21 GPO IGP_DDC_SELECT +3VSUS P55 GPI BAT_IN_OC# +3V
3 GPIO_63 (CABLE_DET_P) +3VS 3
GPIO_22 ACZ_SDIN0_AUD +3VSUS P56 GPO FAN1_DC +3V
GPIO_64 (CABLE_DET_S) +3VS
GPIO_23 ACZ_SDIN1_MDC +3VSUS P57 GPO ADJ_BL +3V
GPIO_24 GPI CHG_FULL_OC +3VSUS P67 GPI NEWCARD_OFF# +3V
GPIO_25 SMB_MEM_SCL +3VSUS P66 GPI PANLOCK_# +3V
GPIO_26 SMB_MEM_SDA +3VSUS P65 GPI MARATHON_# +3V
GPIO_27 SMB_CLK_SB +3VSUS 47N217_GPIO USE_AS SIGNAL_NAME Power P64 GPI ACIN_OC# +3V
GPIO_28 SMB_DAT_SB +3VSUS GPIO10 GPI +3VS P63 GPI NEWCARD_DET# +3V
GPIO_29 (SMB_ALERT#) +3VSUS GPIO[11:12] GPO +3VS P62 GPI WIRELESS_# +3V
GPIO_30 PCI_PME# +3VSUS GPIO[13:14] GPI +3VS P61 GPI INTERNET_# +3V
GPIO_31 GPI SIO_SMI# +3VSUS GPIO23 GPO +3VS P60 GPI BLUETOOTH_# +3V
GPIO_32 EXTSMI#_3A +3VSUS GPIO[40:45] GPI +3VS P76 GPIO SMD_BAT +3V
4 GPIO_33 GPI (RI#) +3VSUS GPIO46 GPI +3VS P77 GPIO SMC_BAT +3V 4


GPIO_34 SUS_CLK +3VSUS GPIO47 GPI +3VS P27 GPO SCR_LED# +3V
GPIO_35 GPO WLAN_ON# +3VSUS P26 GPO NUM_LED# +3V
GPIO_36 +3VSUS P25 GPO CAP_LED# +3V
GPIO_37 GPO OP_SD# +3VSUS P24 GPO SET_PCIRSTNS# +3V
GPIO_38 GPO MXM_PWR_ON +3VS P40 GPO KBC_EXTSMI +3V
GPIO_39 GPI VGA_DETECT# +3VS P41 GPO PANLOCK_LED +3V
GPIO_40 GPO BACK_OFF# +3VS
GPIO_41 GPI VGA_PWRGD +3VS
GPIO_42 PM_CLKRUN# +3VS
GPIO_43 PCI_PERR# +3VS
GPIO_44 ACZ_SYNC +3VS
5 5
GPIO_45 ACZ_SDOUT +3VS
GPIO_46 GPO BT_ON/OFF# +3VS


REVISION DATE: Friday, July 21, 2006 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: A8T 2.1 SHEET 3 OF 55 SCHEMATICS REF. RELEASE DATE : Albert Su
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5 4 3 2 1




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U1A

11 HTCPU_TXCLK1 J5 L0_CLKIN_H1 L0_CLKOUT_H1 Y4 HTCPU_RXCLK1 11
11 HTCPU_TXCLK1# K5 L0_CLKIN_L1 L0_CLKOUT_L1 Y3 HTCPU_RXCLK1# 11
11 HTCPU_TXCLK0 J3 L0_CLKIN_H0 L0_CLKOUT_H0 Y1 HTCPU_RXCLK0 11
11 HTCPU_TXCLK0# J2 L0_CLKIN_L0 L0_CLKOUT_L0 W1 HTCPU_RXCLK0# 11
HT_TXCTL P3 T5 1 T221
HT_TXCTL# L0_CTLIN_H1 L0_CTLOUT_H1 T222
P4 R5 1
L0_CTLIN_L1 L0_CTLOUT_L1
11 HTCPU_TXCTL N1 L0_CTLIN_H0 L0_CTLOUT_H0 R2 HTCPU_RXCTL 11
11 HTCPU_TXCTL# P1 L0_CTLIN_L0 L0_CTLOUT_L0 R3 HTCPU_RXCTL# 11
HTCPU_TXDP15 N5 T4 HTCPU_RXDP15
+1.2VS_HT HTCPU_TXDN15 L0_CADIN_H15 L0_CADOUT_H15 HTCPU_RXDN15
P5 L0_CADIN_L15 L0_CADOUT_L15 T3
HTCPU_TXDP14 M3 V5 HTCPU_RXDP14
HTCPU_TXDN14 L0_CADIN_H14 L0_CADOUT_H14 HTCPU_RXDN14
M4 L0_CADIN_L14 L0_CADOUT_L14 U5
HTCPU_TXDP13 L5 V4 HTCPU_RXDP13
R772 HTCPU_TXDN13 L0_CADIN_H13 L0_CADOUT_H13 HTCPU_RXDN13
M5 L0_CADIN_L13 L0_CADOUT_L13 V3
HTCPU_TXDP12 K3 Y5 HTCPU_RXDP12
C 49.9Ohm HTCPU_TXDN12 L0_CADIN_H12 L0_CADOUT_H12 HTCPU_RXDN12 C
K4 L0_CADIN_L12 L0_CADOUT_L12 W5
HTCPU_TXDP11 H3 AB5 HTCPU_RXDP11
HT_TXCTL HTCPU_TXDN11 L0_CADIN_H11 L0_CADOUT_H11 HTCPU_RXDN11
H4 L0_CADIN_L11 L0_CADOUT_L11 AA5
HTCPU_TXDP10 G5 AB4 HTCPU_RXDP10
HTCPU_TXDN10 L0_CADIN_H10 L0_CADOUT_H10 HTCPU_RXDN10
H5 L0_CADIN_L10 L0_CADOUT_L10 AB3
HT_TXCTL# HTCPU_TXDP9 F3 AD5 HTCPU_RXDP9
HTCPU_TXDN9 L0_CADIN_H9 L0_CADOUT_H9 HTCPU_RXDN9
F4 L0_CADIN_L9 L0_CADOUT_L9 AC5 HTCPU_RXDP[0..15] 11
HTCPU_TXDP8 E5 AD4 HTCPU_RXDP8
11 HTCPU_TXDP[0..15] HTCPU_TXDN8 L0_CADIN_H8 L0_CADOUT_H8 HTCPU_RXDN8
R773 F5 AD3
L0_CADIN_L8 L0_CADOUT_L8
HTCPU_TXDP7 HYPERTRANSPORT
HTCPU_RXDP7 HTCPU_RXDN[0..15] 11
49.9Ohm N3 T1
11 HTCPU_TXDN[0..15] HTCPU_TXDN7 L0_CADIN_H7 L0_CADOUT_H7 HTCPU_RXDN7
N2 L0_CADIN_L7 L0_CADOUT_L7 R1
HTCPU_TXDP6 L1 U2 HTCPU_RXDP6
HTCPU_TXDN6 L0_CADIN_H6 L0_CADOUT_H6 HTCPU_RXDN6
M1 L0_CADIN_L6 L0_CADOUT_L6 U3
HTCPU_TXDP5 L3 V1 HTCPU_RXDP5
HTCPU_TXDN5 L0_CADIN_H5 L0_CADOUT_H5 HTCPU_RXDN5
L2 L0_CADIN_L5 L0_CADOUT_L5 U1
HTCPU_TXDP4 J1 W2 HTCPU_RXDP4
HTCPU_TXDN4 L0_CADIN_H4 L0_CADOUT_H4 HTCPU_RXDN4
K1 L0_CADIN_L4 L0_CADOUT_L4 W3
HTCPU_TXDP3 G1 AA2 HTCPU_RXDP3
HTCPU_TXDN3 L0_CADIN_H3 L0_CADOUT_H3 HTCPU_RXDN3
H1 L0_CADIN_L3 L0_CADOUT_L3 AA3
HTCPU_TXDP2 G3 AB1 HTCPU_RXDP2
HTCPU_TXDN2 L0_CADIN_H2 L0_CADOUT_H2 HTCPU_RXDN2
G2 AA1
HTCPU_TXDP1 L0_CADIN_L2 L0_CADOUT_L2 HTCPU_RXDP1
E1 L0_CADIN_H1 L0_CADOUT_H1 AC2
HTCPU_TXDN1 F1 AC3 HTCPU_RXDN1
HTCPU_TXDP0 L0_CADIN_L1 L0_CADOUT_L1 HTCPU_RXDP0
E3 L0_CADIN_H0 L0_CADOUT_H0 AD1
HTCPU_TXDN0 E2 AC1 HTCPU_RXDN0
L0_CADIN_L0 L0_CADOUT_L0
SOCKET638
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REVISION DATE: Friday, July 21, 2006 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: A8T 2.1 SHEET 4 OF 55 S1 CPU HT RELEASE DATE : Albert Su
5 4 3 2 1
5 4 3 2 1



+2.5VS
L100
1 2 VDDA

+ 180NH C701 C702 C703
CE7
4.7UF/6.3V 0.22UF/6.3V3300PF/25V +3VS
100UF/6.3V U1D
R19 200
+3VS
F8 VDDA1
F9 C13 R20 R795
VDDA2
11 CLK_CPU 2 1
D C704 3900PF/50V 1 2 CLKIN A9 0.1U 10K 4.7KOhm D
R774 169Ohm CLKIN# CLKIN_H U2
A8 CLKIN_L CPU_VID[0..5] 61
11 CLK_CPU# 2 1 1 VCC SCLK 8 SCL_3S 16,29
C705 3900PF/50V CPU_PWRGD A7 A5 CPU_VID5 H_THERMDA 2 7
R < 600 mils from CPU CPU_STP# PWROK VID5 CPU_VID4 DXP SDA SDA_3S 16,29
F10 C6 H_THERMDC 3 6 PM_THRM#
CPU_RST# LDTSTOP_L VID4 CPU_VID3 DXN ALERT# PM_THRM# 22
AC caps < 1250 mils B7 VID3 A6 4 5
RESET_L CPU_VID2 OVERT# GND
VID2 A4
1 2 AC6 C5 CPU_VID1 MAX6657MSA
+1.8V CPU_PRESENT_L VID1 CPU_VID0
R775 1KOhm B5
VID0 C34 1000P
1 300Ohm 2 AF4 AF6 H_THRMTRIP#
R777 T7128 1 SIC THERMTRIP_L H_PROCHOT#
AF5 SID PROCHOT_L AC7

T223 1 AF9 AE9 1 T224
TDI TDO OTP_RESET# 42
T225 1 AD9
+1.8V T226 TRST_L Q102
1 AC9 TCK MISC
T227 1 AA9 2N7002
TMS
T228 1 E10 G10 1 T229
DBREQ_L DBRDY
CPU_VDDIO_FB 1 20,31 PCIRST_NEWC#
R779 F6 W9 T7129
61 CPU_VDD_FB VDD_FB_H VDDIO_FB_H
E6 Y9 1 T7130
61 CPU_VDD_FB# VDD_FB_L VDDIO_FB_L CPU_PSI# 61
2KOhm
T7131 1 VTT_SENSE Y10 A3 +1.2VS_HT
CPU_MVREF +1.8V VTT_SENSE PSI_L
39.2Ohm CPU_MVREF W17 P6 HT_REF1 1 2
M_VREF HTREF1
1 2 MEM_ZN AE10 R6 HT_REF0R780
1 44.2Ohm
2
M_ZN HTREF0
R783 C706 C707 R781
1 2 MEM_ZP AF10 M_ZP
R782 44.2Ohm
R784 39.2Ohm
C 2KOhm 0.1UF/16V 1000PF/50V 1 2 E9 C9 FBCLKOUT 1 2 C
R785 TEST25_H TEST29_H FBCLKOUT#
1 2510Ohm E8 C8 R786 80.6Ohm +1.8VS
R787 TEST25_L TEST29_L < 1" from CPU
1 2510Ohm G9
R788 TEST19 +3VS
1 2300Ohm H10 TEST18 80 ohm diff impedence +1.8V
R789 300Ohm AA7
TEST13 R22
C2 TEST9
AE7 1 T230
T231 TEST24 T232 R23 10KOhm R27
1 D7 TEST17 TEST23 AD7 1
Place near CPU socket T233 1 E7 AE8 1 T234
T235 TEST16 TEST22 300Ohm 4.7KOhm
1 F7 AB8 1 2
T236 TEST15 TEST21 R790 1 300Ohm
1 C7 TEST14 TEST20 AF7
T238 1 AC8 T237
TEST12 +1.8V
TEST28_H J7
C3 H8 H_THRMTRIP#
TEST7 TEST28_L CPU_THRMTRIP# 19
AA6 AF8
H_THERMDC TEST6 TEST27 Q1
W7 THERMDC TEST26 AE6 1 2
H_THERMDA W8 K8 R791 300Ohm PMBS3904
THERMDA TEST10
Y6 TEST3 TEST8 C4
AB6 TEST2
SOCKET638 +1.8VS

+1.8V
+2.5VS +1.8V
R792
1 1KOhm 2 RN34A 1 300Ohm 2
RN35A +1.8V
3 1KOhm 4 RN34B 3 300Ohm 4
RN35B R794 10KOhm
5 1KOhm 6 RN34C 5 300Ohm 6
RN35C For future processors
7 1KOhm 8 RN34D U52A 7 300Ohm 8
RN35D 300Ohm
B VCC B
1 2 CPU_RST# CPU_VID1 1 2
11 HTCPU_RST#
R793 300Ohm
GND H_PROCHOT# PROCHOT#
PROCHOT# 28
74LVC07AD
Q109
U52B
VCC