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1 2 3 4 5 6 7 8
01
ZGA Block Diagram
A A
CK505
P2
DDR SYSTEM MEMORY
Pineview
Graphics Interfaces
667 MT/s INT_LVDS
DDRIII-SODIMM 11.6"Panel
CPU CH7036 Up to 1280*800 or 1366*768
P3
P24 P15
P5,6,7,8
DMI
N475 1.83G: AJ0Q4KSUT03
N455 1.66G: AJ0Q4L5VT03 HDMI
P25
DMI(x2) Charger
P27
B B
+3VPCU
SATA 0 DMI +5VPCU
SATA - SSD SATA PCIE-4
P20 SIM Card +3V_S5
USB-5 3G/WiMAX
P21 USB-1
P21 +5V_S5
+3VSUS
+3V
PCI-Express(Port1~4) +5V P28
Tigerpoint
VCC_CORE
USB-2 USB 2.0 (Port0~7) P29
CCD PCIE-2
USB PCI-E
P15
SB USB-7 WLAN/WiMAX +1.5VSUS
P21 +SMDDR_VREF
4 in 1 Card Reader USB-4 P9,10,11,12,13,14
Realtek RTS5138 P22 +0.75V_DDR_VTT
RTC +1.5V P30
USB-0,3 SMBUS
C
USB port*2 C
P18 PN : AJ0QMJN0T07
BATTERY +1.05V
P31
USB-6
Bluetooth module P12
P16
+1.5V
Intel High Definition Audio SPI Flash
IHDA P12
Discharge
LPC VCCGFX
P32
LPC
TPM P26
ST19NP18ER28PVLR
Audio Codec Realtek ALC271 EC NPCE781L
P17 P23
D D
Touch Pad /B
K/B Con. SPI Flash Charger Light Sensor
Int. SPK Int. DMIC MIC HP Con.
CONN CONN Jack Jack P15 P15 P22 P23 TSL2561FN P26
Quanta Computer Inc.
PROJECT : ZGA
Size Document Number Rev
Block Diagram 1B
Date: Wednesday, July 07, 2010 Sheet 1 of 38
1 2 3 4 5 6 7 8
5 4 3 2 1
Clock Generator(CLK) The Beads for power 3.3V/1.05 are for EMI solution.
It is recommended to add it for better power/EMI performance. 0.08A +1.05V_VDD
02
PBY160808T-301Y-N/2A/300ohm_6 L31 +1.05V
C346 PBY160808T-301Y-N/2A/300ohm_6 <20090721(B2A)_Intel MOW WW28,2009>
+3V +3V
L32 *0.1u/10V_4 C378 C379 C360 C369 C375 C376 C371 C367 Stuff R56,R60 to solve system maybe boot failure issue
C356
*0.1u/10V_4 *10u/10V_8 10u/10V_8 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 *0.1u/10V_4
C350 PM_STPPCI#_R R419 10K_4
*10u/10V_8
C364 U25
0.1u/10V_4 9 55 1/19 : 439549_439549_CorbettPark_Schm_Rev0.5: If this pin is PM_STPCPU# R418 10K_4
C348 VDD_PCI NC used as PCI_STOP#, it is required to provide a 10-k pull-up to
D
16 VDD_48 D
0.1u/10V_4 23 7 SMBCK1 Vcc3_3. It is not recommended to connect this signal to the
C377 VDD_CK_VDD_REF VDD_PLL3 SCLK SMBDT1 Tiger Point(NM10) as it may cause unexpected system behavior. CLKREQ_WLAN#_R R411 10K_4
4 VDD_REF SDA 6
0.1u/10V_4 0.25A CK505
C361 46 45 PM_STPPCI#_R R420 *0_4 PM_STPPCI# PM_STPPCI# (12)
0.1u/10V_4 VDD_SRC PCI_STOP# PM_STPCPU#
62 VDD_CPU CPU_STOP# 44 PM_STPCPU# (12) To SB
+1.05V_VDD
C380 19 61
VDD_96_IO CPU0 CLK_CPU_BCLK (5)
27 60 To CPU (Core CLK) CLKREQ_Dec#_R R417 10K_4
VDD_PLL3_IO CPU0# CLK_CPU_BCLK# (5)
10u/10V_8 33 VDD_SRC_IO_1
52 VDD_SRC_IO_3 CPU1 58 CLK_MCH_BCLK (5)
43 57 To CPU (Host CLK) CLKREQ_3G#_R R406 10K_4
VDD_SRC_IO_2 CPU1# CLK_MCH_BCLK# (5)
56 VDD_CPU_IO
SRC8/ITP 54 CLK_PCIE_DMIP (5)
<20090527(A1A)_Silego suggestion>
SRC8#/ITP# 53 CLK_PCIE_DMIN (5) To CPU (DMI CLK) The EMI capacitor should be placed
between pin and series resistor for
T53 8 41
PCI0/CR#_A SRC10 CLK_PCIE_Dec (26) good EMI and SI
SRC10# 42 CLK_PCIE_Dec# (26) To Decoder
R367 33_4 PCLK_DEBUG_R 10
(21) PCLK_DEBUG PCI1/CR#_B
40 CLKREQ_Dec#_R R416 475/F_4 CLKREQ_Dec# (26)
PCLK_2 SRC11/CR#_H
11 PCI2/TME SRC11#/CR#_G 39 T62
R374 33_4 PCLK_TPM_R 12 37
(26) PCLK_TPM PCI3 SRC9 T63
38 PCLK_DEBUG_R C343 *22p/50V_4
SRC9# T64
R371 33_4 PCLK_EC_R 13
(23) LCLK_EC PCI4/27M_Select
SRC7/CR#_F 51 CLK_PCIE_ICH (9)
PCLK_ICH R379 33_4 PCLK_ICH_R 14 50 To SB (DMI CLK) PCLK_EC_R C340 *33p/50V_4
(11) PCLK_ICH PCI_F5/ITP_EN SRC7#/CR#_E CLK_PCIE_ICH# (9)
CG_XIN 3 48
XTAL_IN SRC6 CLK_PCIE_SATA (10)
47 To SB (SATA CLK) PCLK_ICH_R C351 *33p/50V_4
SRC6# CLK_PCIE_SATA# (10)
C CG_XOUT 2 C
XTAL_OUT
SRC4 34 PE2CLK+ (21)
R385 22_4 FSA 17 35 To Mini Card 1 (WLAN) FSA C362 *22p/50V_4
(22) CLK_Card48 USB_48/FSA SRC4# PE2CLK- (21)
R384 22_4
(9) CLKUSB_48 CLK_BSEL0 R393 2.2K_4 FSB CLKREQ_3G#_R R404 475/F_4
64 FSB/TEST_MODE SRC3/CR#_C 31 CLKREQ_3G# (21)
32 CLKREQ_WLAN#_R R409 475/F_4 CLKREQ_WLAN# (21) FSC C347 *33p/50V_4
FSC SRC3#/CR#_D
5 REF0/FSC/TESTSEL
CLK_BSEL1 R386 1K_4 65 28
VSS_BODY SRC2/SATA PE4CLK+ (21)
15 29 To Mini Card 2 (3G/Wimax) PCLK_TPM_R C345 *33p/50V_4
VSS_PCI SRC2#/SATA# PE4CLK- (21)
18 VSS_48
CLK_BSEL2 R376 10K_4 22 24
VSS_IO 27M_NosSS/SRC1(LCDCLK) DREFSSCLK (5)
R375 33_4 26 25 To CPU (SS CLK)
(12) 14M_ICH VSS_PLL3 27M_SS/SRC1#(LCDCLK# DREFSSCLK# (5)
59 VSS_CPU
30 VSS_SRC1 SRC0/DOT96 20 DREFCLK (5)
36 VSS_SRC2 SRC0#/DOT96# 21 DREFCLK# (5) To CPU (PLL CLK)
C349 49
33p/50V_4 CG_XIN VSS_SRC3 VR_PWRGD_CK410
1 63
VSS_REF CKPW RGD/PW RDW N# VR PWRGD
2
Y4 SLG8SP513
CL=20p SLG8SP513VTR ,ICS9LPRS365BKLFT (29) VR_PWRGD_CK410#
14.318MHZ
C354 : SLG8SP513VTR(AL8SP513000) R400 *10K_4
1
33p/50V_4 CG_XOUT : ICS9LRS3165BKLFT(AL003165000)
: ICS9LPRS365BKLFT(ALPRS365000)
2
Crystal place within 500mil of CK505 CLKREQA# CONTROL SRC0(default) or SRC2 1 3 R394 10K_4
+3V
CLKREQB# CONTROL SRC1(default) or SRC4
B
CLKREQC# CONTROL SRC2 +1.05V R392 *1K_4 2N7002K VR_PWRGD_CK410
VR_PWRGD_CK410 (12) B
CLKREQD# CONTROL SRC4 Q25
R391 0_4 CLK_BSEL0
(5) CPU_BSEL0
CLKREQE# CONTROL SRC6
CLKREQF# CONTROL SRC8 R395 *0_4
R365 10K_4 PCLK_2 <20090721(B2A)>
+3V CLKREQG# CONTROL SRC9 Change Q3,Q5,Q6 from BAM700200F6 to BAM70020002 (with ESD protection function)
CLKREQH# CONTROL SRC10 +1.05V R388 *1K_4
R366 *10K_4
R389 0_4 CLK_BSEL1 +3V
(5) CPU_BSEL1
R363 *10K_4 PCLK_EC_R R387 *0_4
+3V
Clock Gen I2C R359
R361 10K_4 +1.05V R369 *1K_4 2.2K_4
2
R370 0_4 CLK_BSEL2
(5) CPU_BSEL2
+3V R378 *10K_4 PCLK_ICH_R 3 1 SMBCK1
(12,21) PCLK_SMB SMBCK1 (3,21,25,26)
R368 *0_4
R377 10K_4 2N7002K
Q23 +3V
FSC FSB FSA
BSEL2 BSEL1 BSEL0 CPU SRC PCI REF USB DOT
R360
SLG8SP513VTR ICS9LPRS365 0 0 0 266.66 100 33.33 14.318 48 96 2.2K_4
2
(AL8SP513000) (ALPRS365000) PULL HIGH PULL DOWN
0 0 1 133.33 100 33.33 14.318 48 96
3 1 SMBDT1
Pin 11 PCI2 PCI2/TME NO OVERCLOCKING (default) NORMAL RUN (12,21) PDAT_SMB SMBDT1 (3,21,25,26)
A 0 1 0 200.00 100 33.33 14.318 48 96 A
0 1 1 166.66 100 33.33 14.318 48 96 2N7002K
Q24
Pin 13 PCI4/ PCI4/ PIN 20/21 IS SRC0 PIN 20/21 IS DOT96 (default) 1 0 0
SEL_LCDCLK# 27_Select PIN 24/25 IS 27MHz PIN 24/25 IS LCDCLK
333.33 100 33.33 14.318 48 96
1 0 1 100.00 100 33.33 14.318 48 96
Pin 14 PCIF5/ITP_EN PCIF5/ITP_EN PIN 53/54 IS CPUITP PIN 53/54 IS SRC8 (default)
Quanta Computer Inc.
1 1 0 400.00 100 33.33 14.318 48 96
1 1 1 RESERVED
PROJECT : ZGA
Size Document Number Rev
1B
CLOCK GENERATOR
Date: Wednesday, July 07, 2010 Sheet 2 of 38
5 4 3 2 1
5 4 3 2 1
DDR_STD(DDR) +1.5VSUS
JDIM1B
JDIM1A M_A_DQ[63:0] (6)
(6) M_A_A[14:0] 75 VDD1 VSS16 44
M_A_A0 98 5 M_A_DQ5 76 48
M_A_A1 97
A0 DQ0
7 M_A_DQ1
2.48A 81
VDD2 VSS17
49
M_A_A2 A1 DQ1 M_A_DQ7 VDD3 VSS18
96 A2 DQ2 15 82 VDD4 VSS19 54
M_A_A3 95 17 M_A_DQ6 87 55
M_A_A4 A3 DQ3 M_A_DQ4 VDD5 VSS20
92 A4 DQ4 4 88 VDD6 VSS21 60
M_A_A5 91 6 M_A_DQ0 93 61
M_A_A6 A5 DQ5 M_A_DQ2 VDD7 VSS22
90 A6 DQ6 16 94 VDD8 VSS23 65
M_A_A7 86 18 M_A_DQ3 99 66
M_A_A8 A7 DQ7 M_A_DQ8 VDD9 VSS24
D 89 A8 DQ8 21 100 VDD10 VSS25 71 D
M_A_A9 85 23 M_A_DQ9 105 72
M_A_A10 A9 DQ9 M_A_DQ10 VDD11 VSS26
PC2100 DDR3 SDRAM SO-DIMM
107 A10/AP DQ10 33 106 VDD12 VSS27 127
M_A_A11 84 35 M_A_DQ11 111 128
M_A_A12 A11 DQ11 M_A_DQ12 VDD13 VSS28
83 A12/BC# DQ12 22 112 VDD14 VSS29 133
M_A_A13 119 24 M_A_DQ13 117 134
M_A_A14 A13 DQ13 M_A_DQ14 VDD15 VSS30
80 A14 DQ14 34 118 VDD16 VSS31 138
78 36 M_A_DQ15 123 139
A15 DQ15 M_A_DQ24 VDD17 VSS32
PC2100 DDR3 SDRAM SO-DIMM
DQ16 39 124 VDD18 VSS33 144
109 41 M_A_DQ28 145
(6) M_A_BS0 BA0 DQ17 VSS34
108 51 M_A_DQ27 199 150
(6) M_A_BS1 BA1 DQ18 +3V VDDSPD VSS35
79 53 M_A_DQ26 151
(6) M_A_BS2 BA2 DQ19 VSS36
114 40 M_A_DQ29 77 155
(6) M_CS#0 S0# DQ20 NC1 VSS37
121 42 M_A_DQ25 122 156
(6) M_CS#1 S1# DQ21 NC2 VSS38
101 50 M_A_DQ30 R381 *10K_4 125 161
(6) M_CLK0 CK0 DQ22 +3V NCTEST VSS39
103 52 M_A_DQ31 162
(6) M_CLK0# CK0# DQ23 VSS40