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Cover Sheet




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2 2




888Z3 LA-1044 REV2.0 SCHEMATIC DOCUMENT
Intel (Tualatin) with VIA(VT8606-TwisterT + VT8231)

3 3




BOM : PCB Layer
Structure:
LN_ SKU W/SS JOPEN1 TOP
L@ SKU WO/SS JOPEN8
1394@ SKU W/1394 JOPEN9 GND1
TV@ SKU W/TVOUT JOPEN10 IN1
GND2
4
DJ@ SKU W/AUDIO DJ VCC
4


DJN_ SKU WO/AUDIO DJ IN2
EQ@ SKU W/EQ GND3
EQN_ SKU WO/EQ BOT
F@ SKU W/FPR Title
Compal Electronics, Inc.
FN_ SKU WO/FPR THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
SCHEMATIC, M/B LA-1044
SPR@ SKU W/DOCKING CONN. DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Size
B
Document Number Rev
2A
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC. 401196
Date: , 17, 2002 Sheet 1 of 44
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Compal confidential Block Diagram
Model Name : 888Z3/LA-1044 (Intel Tualatin)
Intel
Tualatin Micro-FCPGA
page 3,4,5
1 1
SpeedStep VID
Logic SELECT
page 6 page 7
Y1
14.318MHZ

CRT Connector 14M_3V
page 14 VIA North Bridge Clock Generator 14M_5V

Power On/Off Twister-T CY28317-2 PCLK_DOCK
DCLKWR
Reset Circuit page 8,9,10 page 11 +3VSUS PCLK_PCM
DCLKO +3VRUN
page 32 TFT/HPA Panel
Interface CLK_SDRAM0,1




MA(0..13)
page 15




MD(0..63)
CLK_SDRAM1,2



DC/DC Interface TV Encoder




AD(0..31)
RTC Battery TV/Out SO-DIMM 0 SO-DIMM 1
Connector CH7005 (Bank 0,1) (Bank 2,3) USB
page 33 page 14
page 14 page 12 page 13
Port 3




PCLK_PIIX4
2 2
FingerPR
page 36
PCI BUS
AC Link
USB
Mini PCI PCMCIA VIA VT6306 AC97 HUB
VIA South Bridge CLK_48MHZ page 37
Socket ENE CB1410 1394 Controller Codec 14M_3V

page 36 page 16 page 18
page 24 VT8231
page 19,20,21


* HSP Modem Card Slot 0 Audio AMP USB USB USB
page 17
* Combo for HSP Modem and Speaker EQ Jack Port 0,1 Port 2 Port 3
802.11b page 26 page 28 page 27
* Controllerless Modem page 25 page 26 Bluetooth
page 37
* Combo for Controllerless
3 Modem and 802.11b 3
LPC BUS

14M_5V
IDE Damping PIO Docking Connector
KeyBoard Resistor
page 28
* DC-IN
RJ45/RJ11 LAN NS87591 * 2 USB Port
Jack page 22
RTL8100 * TV Out (S Video)
page 30 page 29 page 31 * VGA Out
FIR * 2 PS/2
page 27 * LAN
HDD CD Player * Parallel Port
Touch Pad KBD Connector OZ163 * Serial Port
page 33 page 32 page 22 page 23 * Line Out
* Headphone
* Microphone
Power Circuit I/O Buffer
DC/DC page 32 page 35

page 37,38,39,40
BIOS CD-ROM
page 32 Connector
4
page 22 4
PCB1




LA-1044 PCB

Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
SCHEMATIC, M/B LA-1044
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Size Document Number Rev
B 2A
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC. 401196
Date: , 17, 2002 Sheet 2 of 44
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A B C D E



Tualatin/Celeron-T CPU


+CPU_CORE



1 1




AC21




AC19




AC17




AC15




AC13




AC11
AB22
AA21




AB20
AA19




AB18
AA17




AB16
AA15




AB14
AA13




AB12
AA11




AB10
W21
M22




AC9




AC7
G21




AA9




AB8
AA7
D22


H22




N21

R21

U21




D20




D18




D16




D14




D12




D10
E21


K22



P22



V22

Y22




E19




E17




E15




E13




E11
F22




T22




F20




F18




F16




F14




F12




F10
L21
J21




G5
D8




D6


H6



N5
E9




E7




E5


K6



V6
F8




F6




T6
J5
H_A#[3..31] U8A H_D#[0..63]
8 H_A#[3..31] H_D#[0..63] 8




VCC_0
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72
H_A#3 K1 A16 H_D#0
H_A#4 A#3 D#0 H_D#1
J1 A#4 D#1 B17
H_A#5 G2 A17 H_D#2
H_A#6 A#5 D#2 H_D#3
K3 A#6 D#3 D23
H_A#7 J2 B19 H_D#4
H_A#8 A#7 D#4 H_D#5
H3 A#8 D#5 C20
H_A#9 G1 VCC C16 H_D#6
H_A#10 A#9 D#6 H_D#7
A3 A#10 D#7 A20
H_A#11 J3 A22 H_D#8
H_A#12 A#11 D#8 H_D#9
H1 A#12 D#9 A19
H_A#13 D3 A23 H_D#10
H_A#14 A#13 D#10 H_D#11
F3 A#14 D#11 A24
H_A#15 G3 C18 H_D#12
H_A#16 A#15 D#12 H_D#13
C2 A#16 D#13 D24
H_A#17 B5 B24 H_D#14
H_A#18 A#17 D#14 H_D#15
B11 A#18 D#15 A18
H_A#19 C6 E23 H_D#16
H_A#20 A#19 D#16 H_D#17
B9 A#20 D#17 B21
H_A#21 B7 B23 H_D#18
H_A#22 A#21 D#18 H_D#19
C8 A#22 D#19 E26
H_A#23 A8 C24 H_D#20
H_A#24 A#23 D#20 H_D#21
2 A10 A#24 Address D#21 F24 2
H_A#25 B3 Lines D25 H_D#22
H_A#26 A#25 D#22 H_D#23
A13 A#26 D#23 E24
H_A#27 A9 B25 H_D#24
H_A#28 A#27 D#24 H_D#25
C3 A#28 D#25 G24
H_A#29 C12 H24 H_D#26
H_A#30 A#29 D#26 H_D#27
C10 A#30 D#27 F26
H_A#31 A6 L24 H_D#28
A#31 D#28 H_D#29
A15 H25
A14
B13
A12
A#32
A#33
A#34
Mobile Data
Signals
D#29
D#30
D#31
C26
K24
G26
H_D#30
H_D#31
H_D#32
8 H_REQ#[0..4]
H_REQ#[0..4]

H_REQ#0 R1
A#35


REQ#0
Tualatin D#32
D#33
D#34
D#35
K25
J24
K26
H_D#33
H_D#34
H_D#35
H_REQ#1 L3 F25 H_D#36
H_REQ#2 REQ#1 D#36 H_D#37
T1 REQ#2 Request D#37 N26
H_REQ#3 U1 Signals J26 H_D#38
H_REQ#4 REQ#3 D#38 H_D#39
L1 REQ#4 D#39 M24
T4 U26 H_D#40
RP# D#40 H_D#41
8 H_ADS# AA3 ADS# D#41 P25
L26 H_D#42
D#42 H_D#43
D#43 R24
W2 R26 H_D#44
AERR# D#44 H_D#45
AB3 AP#0 D#45 M25
P3 Error V25 H_D#46
+1.5VS AP#1 D#46 H_D#47
C14 BERR# Interface D#47 T24
R229 1.5K_0402 AF23 M26 H_D#48
BINIT# D#48 H_D#49
1 2 AF4 IERR# D#49 P24
3 H_D#50 3
D#50 AA26
1 2 T26 H_D#51
8 H_BREQ0# R249 @0_0402 D#51 H_D#52
A7 BREQ0# D#52 U24
1 2 C4 Arbitration Y25 H_D#53
R250 10_0402 NC D#53 H_D#54
PIR(37) C22 NC Signals D#54 W26
AD23 V26 H_D#55
NC D#55 H_D#56
8 H_BPRI# R2 BPRI# D#56 AB25
L2 T25 H_D#57
8 H_BNR# BNR# D#57
V3 Snoop VSS VCC Y24 H_D#58
8 H_LOCK# LOCK# D#58
Signals W24 H_D#59
D#59 H_D#60
D#60 Y26
AA2 AB24 H_D#61
8 H_HIT# HIT# D#61
U2 AA24 H_D#62
8 H_HITM# HITM# D#62
T3 V24 H_D#63
8 H_DEFER# DEFER# D#63




VCC_80
VCC_79
VCC_78
VCC_77
VCC_76
VCC_75
VCC_74
VCC_73
AA25 VSS_10
AC25VSS_11
AF25 VSS_12
AE26 VSS_13
C23 VSS_14
F23 VSS_15
H23 VSS_16
K23 VSS_17
M23 VSS_18
P23 VSS_19
T23 VSS_20
V23 VSS_21
Y23 VSS_22
AB23 VSS_23
AE23 VSS_24
B22 VSS_25
D21 VSS_26
F21 VSS_27
E22 VSS_28
H21 VSS_29
G22 VSS_30
K21 VSS_31
J22 VSS_32
M21 VSS_33
L22 VSS_34
P21 VSS_35
N22 VSS_36
T21 VSS_37
R22 VSS_38
V21 VSS_39
U22 VSS_40
Y21 VSS_41
W22 VSS_42
AB21 VSS_43
AA22 VSS_44
AC22VSS_45
AE21 VSS_46
B20 VSS_47
D19 VSS_48
AB19 VSS_49
AA20 VSS_50
AC20VSS_51
AE19 VSS_52
B18 VSS_53
D17 VSS_54
F17 VSS_55
E18 VSS_56
AB17 VSS_57
E16 VSS_0
R4 VSS_1
E25 VSS_2
G25 VSS_3
J25 VSS_4
L25 VSS_5
N25 VSS_6
R25 VSS_7
U25 VSS_8
W25 VSS_9




AC5