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PCB STACK UP
LAYER 1 : TOP
LAYER 2 : GND1
LAYER 3 : IN1
TE4 Block Diagram
LAYER 4 : VCC
A LAYER 5 : IN2 A



LAYER 6 : IN3
LAYER 7 : GND2 USB-0
LCD/CCD Con. P26
LAYER 8 : BOT
DDRIII-SODIMM1
DDRIII-SODIMM2 Arrandale (UMA+VGA) INT_LVDS
P14,15 CRT Con.




DDR SYSTEM MEMORY
PCI-E
INT_CRT daughter board
Dual Channel DDR III P26




Graphics Interfaces
800/1066/1333 MHZ INT_HDMI

rPGA 989 HDMI Con.
P25
SATA - HDD Re-Driver P4, 5, 6,7
P29 P29
FDI
DMI


DMI(x4)
SATA - ODD
P29 SATA 0
B FDI B
DMI
SATA 1
SATA
PCI-Express
PCI-E


PCIE-3 CK505
P3
USB-10 3G
USB Con.(Right) daughter board P27
USB-8 POWER SYSTEM
P26 Ibex Peak-M ISL88731C P36
USB 2.0 (Port0~13) PM6686TR P37
USB-3 PCIE-5
USB RT8207L P38
Cardreader PCH USB-5 WLAN G5602R41U P39
USB-4
SIM CARD. P27 RT8152C P40
P27 P9, 10, 11,12,13
P32 ISL62882HRTZ-T P41
PCIE-6 G966A P42
RTC Giga/10/100 Lan
USB Con.(Left) USB-13
P31
Cardreader Con. P28
C
3 IN 1 P32 BATTERY +VCC_CORE C



USB Con.(Left) USB-9
P9
P28
+1.5V
Azalia +1.5VSUS
IHDA
NVRAM
LPC
+VTT
+1.05V
LPC

+1.8V

Audio Codec EC +1.5V_S5
P30 P33 +3VPCU
+3V_S5
Port-B




Port-A




+3V
FAN K/B Con. HALL Sensor SPI Flash Touch Pad /B Power /B +5VPCU
MIC JACK HP SPK Con. Con. Con. +5V_S5
D MDC Con. D
P30 P30 P30 P30 P4 P34 P4 P33 P34 P34 +5V
+SMDDR_VTERM
+SMDDR_VREF


Quanta Computer Inc.
PROJECT : TE4
Size Document Number Rev
1A
Block Diagram
Date: Friday, November 12, 2010 Sheet 1 of 46
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CONTROL Power States
02
Table of Contents POWER PLANE VOLTAGE SIGNAL ACTIVE IN
PAGE DESCRIPTION
VIN 10V~+19V S0~S5

1 Schematic Block Diagram +VCCRTC +3.0V~+3.3V S0~S5
A 2 Front Page A
+3V +3.3V MAIN_ON S0
3 Clock Gen
4-7 Processor +3V_S5 +3.3V S5_ON S0~S5
8 S3 Power Reduction
+3V_HDP +3.3V MAIN_ON S0
9-13 PCH
9 RTC +3VPCU +3.3V AC/DC Insert enable S0
14-15 DDRIII SO-DIMM
+5V +5V MAIN_ON S0
25 HDMI comm part
26 LCD Panel +5V_S5 +5V S5_ON S0~S5
CRT & CRT BUS SWITCH
+5VPCU +5V AC/DC Insert enable S0~S5
CCD
HALL SENSOR&BACK LIGHT SWITCH WIMAX_P +3.3V WMAX_P for WLAN
27 MINI Card (Wi-Fi & WIMAX)
+1.8V +1.8V MAIN_ON S0
MINI Card 2nd
MINI Card 3nd +1.5V +1.5V MAIN_ON S0
28 USB 2.0
+1.5V_SUS +1.5V SUSON S0~S3
29 SATA ODD
Main SATA HDD & 2nd SATA HDD +VCC_CORE VRON S0
30 Codec (CX20587)
+VTT +1.05V MAIN_ON S0
31 Atheros LAN
B 32 3 IN 1 Card reader +1.05V +1.05V MAIN_ON S0 B


33 EC NPCE791L
+VAXG MPWROK S0
34 INT KeyBoard & K/B LED Power
TP board
Power SW
HOLE
35 LED / EMI
36 Charger (ISL88731C) GND PLANE PAGE
37 System 5V/3V (PM6686TR)
8769AGND
38 DDR1.5V(RT8207L)/1.05VSUS 33
39 +VTT/+1.05V (G5602R41U) Audio_GND
30
40 VAXG_CORE RT8152C FOR UMA
Shield_GND
41 +VCC_CORE(ISL62882HRTZ-T) 30
42 +1.8V (G966A)/Discharge
GND ALL

ISL95870A_AGND 30




C C




D D




Quanta Computer Inc.
PROJECT : TE4
Size Document Number Rev
1A
POWER STAGE AND BOI-FUNCTION
Date: Friday, November 12, 2010 Sheet 2 of 46
1 2 3 4 5 6 7 8




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03
CLOCK Gen [CLK] Pin1/17/24
Sligo595 =>1.5V (AL000595000)
+3V Sligo590 =>3.3V (AL8SP590000)
+1.05V
+VDDIO_CLK 80mA(20mils)
L17 PBY160808T-601Y-N_1A 250mA(20mils) +3V_CK505_VDD L8 PBY160808T-601Y-N_1A

D C249 C246 C7354 C240 D
C435 C239 C229
10U/6.3V_8X 0.1U/10V_4X 0.1U/10V_4X U9 *10U/6.3V_8X 10U/6.3V_8X 0.1U/10V_4X 0.1U/10V_4X
R397
+1.5V *590@0_6 5 VDD_27
29 VDD_REF VDD_SRC_I/O 15
VDD_CPU_I/O 18

L7 595@PBY160808T-601Y-N_1A 150mA(20mils) +1.5V_CK505_VDD 1 VDD_DOT_1.5 DOT_96 3 DREFCLK_R RP3
2 1 *short_4P2R
CLK_BUF_DREFCLKP {10}
17 4 DREFCLK#_R 4 3
VDD_SRC_1.5 DOT_96# CLK_BUF_DREFCLKN {10}
24 VDD_CPU_1.5
6 CLK_VGA_27M_R R186 *EV@33_4
27M PCH_CLK_27M
C233 C7335 C234 C243 XTAL_OUT 27 7 CLK_VGA_27M#_R R190 EV@33_4
595@10U/6.3V_8X *0.1U/10V_4X *0.1U/10V_4X *0.1U/10V_4X XTAL_IN XTAL_OUT 27M_SS R197 *33_4 TP35
28 XTAL_IN
10 DREFSSCLK_R RP4 2 1 *short_4P2R
SRC_1/SATA CLK_BUF_DREFSSCLKP {10}
CPU_SEL 30 11 DREFSSCLK#_R 4 3
REF_0/CPU_SEL SRC_1#/SATA# CLK_BUF_DREFSSCLKN {10}
13 PCIE_3GPLL_R RP5 2 1 *short_4P2R
SRC_2 CLK_BUF_PCIE_3GPLLP {10}
14 PCIE_3GPLL#_R 4 3
SRC_2# CLK_BUF_PCIE_3GPLLN {10}
CGDAT_SMB 31
CGCLK_SMB SDA ICS_CPU_STOP# R411 10K_4
32 SCL *CPU_STOP# 16 +3V
C CLK_PCH_14M R133 33_4 2 C
{10} CLK_PCH_14M VSS_DOT
8 20 CLK_BUF_BCLK1_P_R TP31
VSS_27 CPU_1 CLK_BUF_BCLK1_N_R TP30
9 VSS_SATA CPU_1# 19
C225 12 23 CLK_BUF_BCLK0_P_R RP2 4 3 *short_4P2R
VSS_SRC CPU_0 CLK_BUF_BCLKP {10}
21 22 CLK_BUF_BCLK0_N_R 2 1
VSS_CPU CPU_0# CLK_BUF_BCLKN {10}
*15P/50V_4C 26 VSS_REF VR_PWRGD_CLKEN
CKPWRGD/PD# 25
33 GND
SLG8LV595VTR




CLK CRYSTAL CLK CPU_SEL CLK I2C CLK POWERGOOD

+3V

B B


+3V

R378
+3VPCU R138 10K_4 VR_PWRGD_CLKEN




2
R134 10K_4




3
*10K_4 3 1 CGDAT_SMB
{10,31} SDATA CGDAT_SMB {14,15,27}
R137
2 Q12 100K/F_4
{41} VR_PWRGD_CK505#
Y2 CPU_SEL 2N7002_200MA
XTAL_IN XTAL_OUT 2N7002_200MA
1 2 Q32
14.318MHZ_30 R136




1
C230 C231
10K_4
33P/50V_4N 33P/50V_4N R398

+3V 10K_4




2
A A

0 1 3 1 CGCLK_SMB
{10,31} SCLK CGCLK_SMB {14,15,27}

2N7002_200MA
Quanta Computer Inc.
CPU =133MHz CPU=100MHz
CPU_SEL (default)
Q34 PROJECT : TE4
Size Document Number Rev
A1A
CLOCK GENERATOR
Date: Monday, January 24, 2011 Sheet 3 of 46
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U19A
B26 PEG_COMP R7350 49.9/F_4 R83 20/F_4 H_COMP3 AT23
U19B
A16 CLK_CPU_BCLKP {12}
04
PEG_ICOMPI R87 20/F_4 H_COMP2 AT24 COMP3 BCLK
A26 B16 CLK_CPU_BCLKN {12}
PEG_ICOMPO R55 49.9/F_4 H_COMP1 G16 COMP2 BCLK#
{11} DMI_TXN0 A24
C23
DMI_RX#[0] PEG_RCOMPO
B27
A25 PEG_RBIAS R7351 750/F_4 R89 49.9/F_4 H_COMP0 AT26 COMP1 MISC AR30
{11} DMI_TXN1 DMI_RX#[1] PEG_RBIAS COMP0 BCLK_ITP TP17
{11} DMI_TXN2 B22 AH24 AT30 TP19
DMI_RX#[2] TP7 SKTOCC# BCLK_ITP#
{11} DMI_TXN3 A21 K35 CLK_PCIE_3GPLLP {10}
DMI_RX#[3] PEG_RX#[0] del in UMA
J34 E16
{11} DMI_TXP0 B24
PEG_RX#[1]
J33 H_CATERR# AK14
CLOCKS PEG_CLK D16 R326 EV@0_4
CLK_PCIE_3GPLLN {10}
DMI_RX[0] PEG_RX#[2] CATERR# PEG_CLK#
{11} DMI_TXP1 D23 G35 {12} H_PECI AT15
DMI_RX[1] PEG_RX#[3] H_PROCHOT#_D PECI
{11} DMI_TXP2 B23 G32 AN26 THERMAL A18 CLK_DREFSSCLKP_R R323 3 4 *IV@0X2 CLK_DREFSSCLKP {10}
DMI_RX[2] PEG_RX#[4] CPU_PM_THRMTRIP# AK15 PROCHOT# DPLL_REF_SSCLK
{11} DMI_TXP3 A22 F34 A17 CLK_DREFSSCLKN_R 1 2 CLK_DREFSSCLKN {10} For EDP
DMI_RX[3] PEG_RX#[5] THERMTRIP# DPLL_REF_SSCLK#
F31
A PEG_RX#[6] R325 EV@0_4 A
D24 D35
{11}
{11}
DMI_RXN0
DMI_RXN1 G24
F23
DMI_TX#[0]
DMI_TX#[1]
DMI PEG_RX#[7]
PEG_RX#[8]
E33
C33
H_CPURST#_R AP26
AL15
RESET_OBS# SM_DRAMRST#
F6 DDR3_DRAMRST#_C DDR3_DRAMRST#_C {8}
{11} DMI_RXN2 DMI_TX#[2] PEG_RX#[9] {11} PM_SYNC PM_SYNC
{11} DMI_RXN3 H23
DMI_TX#[3] PEG_RX#[10]
D32 AN14
VCCPWRGOOD_1 DDR3 SM_RCOMP[0] AL1 SM_RCOMP_0 R353 100/F_4