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Sens Q 20
1.
2.
3.
4.
5.
6.
7.
CETUS 8.
9.
10.
11.
CPU :BANIAS LV 12.
13.
Chip Set :855GM 14.
15.
Remarks : 16.
17.
18.
This Document can not be used without Samsung's authorization.
19.
20.
21.
22.
Model Name : CETUS Main 23.
PCB Code : BA41-00377A 24.
5-1 System Main Board Schematic Diagrams
25.
Dev. Step : MP 26.
27.
Revision : 1.0 28.
29.
T.R. Date : 2003. 4. 24 30.
31.
5 System Schematic Diagrams and PCB Silkscreen
DRAW CHECK APPROVAL
WS JUNG HJ KIM Kevin
5-1
5-2
THERMISTER On Board
Clocking p4 ADM1032
p5
CPU 256MB/128MB
p11,p13,p14
Clock generator BaniasLVp5,p6
400MHZ
Docking (100MHZ, 4*)
LCD
p19
GMCH-M SODIMM
CRT Max 1GB
855GM 266DDR p12
CRT p7,p8,p9,p10 (1.2V)
p19
HI 1.5
RJ-11 #1 USB USB (port 1) Docking
MDC p24 p28
p24
BLUETOOTH
SPKR AMP
#0 port3 p30
ICH4 - M
5 System Schematic Diagrams and PCB Silkscreen
SPDIF AC LINK 82801 DBM 1.5V
CS4202 (AC97 2.2)
HP JACK p24
p24 p15,p16,p17 LPC FWH
p18 82802A 2 USB (port4,5)
MIC JACK EEPROM
p24 p22
PS/2
MICOM
Hitachi 2160 p29 Internal KBD
RJ-45(10/100) p25
p23 p29 Touch Pad
LOM p22
PCI BUS
RJ-45(10/100) LAN switch KINNERITH+
p23
82562EZ 87391 SIO
FDD/ODD p29
Mini PCI
/2ND HDD IDE0 PIO
(FACTORY OPTION) CardBus + CONN
1394 (port 0) p30
p20 1394 Lynx+PHY HDD p29 FIR(Option)
5-1-1(a) System Main Board Schematic Sheet 2 of 40(BLOCK DIAGRAM)
WLAN/Bluetooth p28
1394 (port 1) R5C591
p20,p21
EEPROM
p20
SD(MMC) + MS CARD BUS
p21 p21
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Sens Q 20
Sens Q 20
SCHEMATIC ANNOTATIONS AND BOARD INFORMATION
PCI Devices Voltage Rails
Devices IDSEL# REQ/GNT# Interrupts
Cardbus AD19 0 A,B,C VDC Primary DC system power supply (9 to 12V)
LAN AD21 1 D VCC_CORE Core voltage for BANIAS CPU (1.356 - 0.844V)
MiniPCI SLOT1 AD20 2 E,F VCCP BANIAS/MGM Processor System Bus(PSB) Termination (1.05V)
USB AD29(internal) - USB2.0 : H VCC_MCH MCH-M Core Voltage (1.2V)
#0 : A P1.5V 1.5V switched power rail (off in S3-S5)
#1 : D P1.8V 1.8V switched power rail (off in S3-S5) 5C591
#2 : C P2.5V 2.5V switched power rail (off in S3-S5)
P2.5V_AUX 2.5V power rail (off in S4-S5)
Hub to PCI AD30(internal) - -
LPC bridge/IDE/AC97/SMBUS AD31(internal) - B P1.25V 1.25V power rail (off in S4-S5)
MICOM_P3V 3.3V always on power rail for MICOM
AGP AD17(internal) - A,B
Internal MAC AD24(internal) - E P3.3V 3.3V switched power rail (off in S3-S5)
P3.3V_AUX 3.3V power rail (off in S4-S5)
AC Link - - B
I2 C / SMB Address P5V 5.0V switched power rail (off in S3-S5)
Devices Address Hex Bus P5V_AUX 5.0V power rail ( off in S4-S5)
ICH4M Master - SMBUS Master
CK-408 (Clock Generator) 1101 001x D2h Clock, Unused Clock Output Disable CPU Core Voltage Table
SODIMM0 1010 001x A2h -
TSL2550 0111 001x 72h Photo snesor VID5 VID4 VID3 VID2 VID1 VID0 Voltage VID5 VID4 VID3 VID2 VID1 VID0 Voltage
MICOM Master - SMBUS Master 0 0 0 0 0 0 1.708 V 1 0 0 0 0 0 1.196 V
0 0 0 0 0 1 1.692 V 1 0 0 0 0 1 1.180 V Low Voltage Banias
ADM1032 0100 110x 4Ch Thermal Sensor ( CPU ) 0 0 0 0 1 0 1.676 V 1 0 0 0 1 0 1.164 V VCC (HFM = 1.1/1.2GHz)
Battery 0001 011x 16h System Battery 0 0 0 0 1 1 1.660 V 1 0 0 0 1 1 1.148 V
0 0 0 1 0 0 1.644 V 1 0 0 1 0 0 1.132 V
0 0 0 1 0 1 1.628 V 1 0 0 1 0 1 1.116 V
0 0 0 1 1 0 1.612 V 1 0 0 1 1 0 1.100 V
0
- 0
- 0 1 1 1 1.596 V 1 0
- 0 1 1 1 1.084 V
0 0 1 0 0 0 1.580 V 1 0 1 0 0 0 1.068 V
This Document can not be used without Samsung's authorization.
0 0 1 0 0 1 1.564 V 1 0 1 0 0 1 1.052 V
0 0 1 0 1 0 1.548 V 1 0 1 0 1 0 1.036 V
0 0 1 0 1 1 1.532 V 1 0 1 0 1 1 1.020 V
0 0 1 1 0 0 1.516 V 1 0 1 1 0 0 1.004 V Ultra Low Voltage Banias
0 0 1 1 0 1 1.500 V 1 0 1 1 0 1 0.988 V VCC (HFM = 900MHz)
0 0 1 1 1 0 1.484 V 1 0 1 1 1 0 0.972 V
Highest Freq. 0 0 1 1 1 1 1.468 V 1 0 1 1 1 1 0.956 V Low Voltage Banias
0 1 0 0 0 0 1.452 V 1 1 0 0 0 0 0.940 V VCC (LFM = 600MHz)
0 1 0 0 0 1 1.436 V 1 1 0 0 0 1 0.924 V
0 1 0 0 1 0 1.420 V 1 1 0 0 1 0 0.908 V
USB PORT Assign 0 1 0 0 1 1 1.404 V 1 1 0 0 1 1 0.892 V
0 1 0 1 0 0 1.388 V 1 1 0 1 0 0 0.876 V
PORT NUMBER ASSIGNED TO 0 1 0 1 0 1 1.372 V 1 1 0 1 0 1 0.860 V
0 1 0 1 1 0 1.356 V 1 1 0 1 1 0 0.844 V Ultra Low Voltage Banias
0 SYSTEM PORT LEFT -
0 1 0 1 1 1 1.340 V 1 1 0 1 1 1 0.828 V VCC (LFM = 600MHz)
1 SYSTEM PORT RIGHT 0 1 1 0 0 0 1.324 V 1 1 1 0 0 0 0.812 V
2 Docking 0 1 1 0 0 1 1.308 V 1 1 1 0 0 1 0.796 V
3 BLUETOOTH 0 1 1 0 1 0 1.292 V 1 1 1 0 1 0 0.780 V
4 Docking 0 1 1 0 1 1 1.276 V 1 1 1 0 1 1 0.764 V
5 Docking 0 1 1 1 0 0 1.260 V 1 1 1 1 0 0 0.748 V Deeper Sleep
0 1 1 1 0 1 1.244 V 1 1 1 1 0 1 0.732 V
0 1 1 1 1 0 1.228 V 1 1 1 1 1 0 0.716 V
0 1 1 1 1 1 1.212 V 1 1 1 1 1 1 0.700 V
Low Voltage CPU Ultra Low Voltage CPU
POWER - Vcc (HFM = 1.1/1.2GHz) = 1.180V - Vcc (HFM = 900MHz) = 1.004V
- Vcc (LFM = 600MHz) = 0.956V - Vcc (LFM = 600MHz) = 0.844V
- 100MHz Geyserville III steps supported - 100MHz Geyserville III steps supported
- GV III points for LV Banias 1.1/1.2GHz = 600MHz, 800MHz, 900MHz, 1GHz, 1.1/1.2GHz- GV III points for LV Banias 1.1GHz = 600MHz, 800MHz, 900MHz
- 700MHz point not supported - 700MHz point not supported
MICOM_P3V P5V_AUX P3.3V_AUX P2.5V_AUX P1.5V_AUX P3.3V P1.8V P1.5V P5V VCC_CORE VCCP VCC_MCH - TDP = 12W, Iccmax = 12A - TDP = 7W, Iccmax = 9A
MICOM ICH4 ICH4 MGM ICH4 ICH4 CPU MGM ICH4 CPU CPU CPU
MINI-PCI SODIMM 5C591 5C591 ICH4 5C591 MGM MGM
MINI-PCI
MDC MINI-PCI
SODIMM STAC9750
MICOM MDC
S/IO
MICOM
FWH
HDD HDD
FIR
5-1-1(b) System Main Board Schematic Sheet 3 of 40(BOARD INFORMATION)
CLOCK
THERMISTER
BLUETOOTH
5-3
5 System Schematic Diagrams and PCB Silkscreen
5-4
HCB3216K-601T20
Be sure to follow A/W guide line!
CHP3_CPUSTP*
CHP3_PCISTP*
CHP3_SLPS1*
SMB3_CLK
SMB3_DATA
CLK_CPU* CLK3_DREFSSCLK 48Mhz
CLK_CPU CLK3_ICH66
CLK3_MCH66
5 System Schematic Diagrams and PCB Silkscreen
CLK_MCH*
CLK_MCH
CLK_CPUITP* CLK3_PCLKICH
CLK_CPUITP
CLK3_PCLKCB
CLK3_PCLKFWH
CLK3_PCLKSIO
CLK3_PCLKMICOM
CLK3_PCLKMIN
IMVP4_PWRGD
682088
CLK3_DREF
CLK3_ICH48
CLK3_ICH14
CLK3_SIO14
Close to chip
5-1-1(c) System Main Board Schematic Sheet 4 of 40(CLOCK GENERATOR)
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Sens Q 20
Sens Q 20
CPU1_D*(15:0) CPU1_D*(47:32)
CPU1_A*(16:3)
CPU1_ADS*
CPU1_BNR*
CPU1_BPRI*
CPU1_BREQ*
CPU1_DBSY*
CPU1_DEFER*
CPU1_DRDY*
CPU1_HIT*
CPU1_ADSTB0* CPU1_HITM*
CPU1_REQ*(4:0)
CPU1_DBI0* CPU1_DBI2*
CPU1_DSTBN0* CPU1_DSTBN2*
CPU1_INIT* CPU1_DSTBP0* CPU1_DSTBP2*
CPU1_LOCK*
CPU1_TRDY* CPU1_D*(31:16) CPU1_D*(63:48)
CPU1_A*(31:17)
CPU1_CPURST*
This Document can not be used without Samsung's authorization.
CPU1_RS2*
CPU1_RS1*
CPU1_RS0*
CPU1_A20M*
CPU1_FERR*
CPU1_IGNNE*
CPU1_INTR
CPU1_NMI
CPU1_SMI*
CPU1_ADSTB1* CPU1_STPCLK* CPU1_DBI1* CPU1_DBI3*
CPU1_DSTBN1* CPU1_DSTBN3*
CPU1_DSTBP1* CPU1_DSTBP3*
5-1-1(d) System Main Board Schematic Sheet 5 of 40(BANIAS CPU)
KBC3_THERM_SMCLK CPU2_THERMDA
KBC3_THERM_SMDATA
SMB3_ALERT* CPU2_THERMDC
CHP3_OVERT*
5-5
5 System Schematic Diagrams and PCB Silkscreen
5-6
CLK_CPU
CLK_CPU*
CLK_CPUITP
CLK_CPUITP*
CPU1_SLP*
CPU1_DPSLP*
CPU1_DPWR*
CPU1_PWRGDCPU
CPU1_PROCHOT*
CPU3_VID(5:0)
Placed as close as possible to
each of the four VCCA pins.
CPU1_GTLREF0
CPU2_THERMDA
CPU2_THERMDC
CPU1_THRMTRIP*
GTLREF : Keep the Voltage divider within 0.5"
of the First GTLREF0 with Z0= 55 ohm trace
Minimize coupling of any switching signals to this net
TEST3
CPU1_PSI* PSI*
5 System Schematic Diagrams and PCB Silkscreen
STUFFING OPTION
"ALL ITP I/F signals" must have T.P.
PREQ,PRDY,BPM(0:3),TCK,TDI,TDO,TMS,TRST
"Mobile Platform Design Checklist rev. 0.94 page19"
220uF * 4, 10uF *35 220uF = 12mohm(Max/4) 3.5nH/4
10uF = 5mohm(typ/35) 0.6nH/4
COMP 0 , 2 <(COMP 1,3) should be connected
Z0=27.4 ohm (55 ohm) trace shorter than
VOS-
1/2 " to their respective Banias Pins
5-1-1(e) System Main Board Schematic Sheet 6 of 40(BANIAS CPU)
This Document can not be used without Samsung's authorization.
Sens Q 20
Sens Q 20
CPU1_ADS*
CPU1_TRDY*
CPU1_DRDY*
CPU1_DEFER*
CPU1_HITM*
CPU1_HIT*
CPU1_LOCK*
CPU1_BREQ*
CPU1_BNR*
CPU1_BPRI*
CPU1_DBSY* GMCH1_HAVREF GMCH1_HCCVREF
CPU1_RS0*
CPU1_RS1*
CPU1_RS2*
CPU1_A*(31:3)
CPU1_D*(63:0)
Trace should be 10 mil,20mil spacing.
GMCH1_HYSWING
GMCH1_HDVREF
Trace should be 10 mil,20mil spacing.
GMCH1_HXSWING
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CPU1_REQ*(4:0)
CPU1_ADSTB0*
CPU1_ADSTB1*
RCOMP reference voltage
Routing : 10 mil trace, 20 mil space CLK_MCH* Checklist rev0.94
CLK_MCH
GMCH1_HYSWING
800mV +/- 8%
GMCH1_HXSWING GMCH1_PSWING
CPU1_DSTBP0*
CPU1_DSTBN0* near component
near divider
CPU1_DBI0*
CPU1_DSTBP1*
CPU1_DSTBN1*
CPU1_DBI1*
CPU1_DSTBP2*
350mV +/- 8%
5-1-1(f) System Main Board Schematic Sheet 7 of 40(GMCH-M)
CPU1_DSTBN2* HUB1_REF_GMCH
CPU1_DBI2*
CPU1_DSTBP3*
CPU1_DSTBN3* near component near divider
CPU1_DBI3*
CPURST* Length CPU1_CPURST*
HLZCOMP
GMCH-CPU : 1.0" ~ 6.0" GMCH1_HDVREF
GMCH-R-ITP : 12.0" max
GMCH1_HCCVREF
GMCH1_HAVREF
HUB1_REF_GMCH
GMCH1_PSWING
HUB1_STB*
HUB1_HL(0:10) HUB1_STB
5-7
5 System Schematic Diagrams and PCB Silkscreen
5-8
MEM2_MD(63:0)
MEM2_DQS(7:0)
MEM2_MAA(12:0)
MEM2_MAB(2:1)
MEM2_MAB(5:4)
MEM2_CKE0 SODIMM 0 GMCH1_SMRCOMP
MEM2_CKE1 SODIMM 0
MEM2_CKE2 On Board : 256MB
MEM2_CSA0* SODIMM 0
MEM2_CSA1* SODIMM 0
MEM2_CSA2* On Board : 256MB
5 System Schematic Diagrams and PCB Silkscreen
MEM2_BS0
MEM2_BS1
MEM2_SRASA*
MEM2_SCASA*
MEM2_SWEA*
CLK2_MCLK0
CLK2_MCLK0*
CLK2_MCLK1
CLK2_MCLK1*
SODIMM0 GMCH1_SMVSWINGL
CLK2_MCLK3
CLK2_MCLK3* ON BOARD
CLK2_MCLK4
CLK2_MCLK4*
MEM2_DM(7:0)
5-1-1(g) System Main Board Schematic Sheet 8 of 40(GMCH-M)
If ECC support is not implemented, GMCH1_SMVSWINGH
SDQ[71:64], SDM8, SDQS8 GMCH1_SMRCOMP
SCK2/2*, SCK5/5*, these signal are NC. GMCH1_SMVSWINGL
GMCH1_SMVSWINGH
Used to measure timing for the read data
Both signals should have vias located adjacent to the package
This Document can not be used without Samsung's authorization.
Sens Q 20
Sens Q 20
As short as possible
T-topology
DCK_VGA3_BLUE
DCK_VGA3_GREEN
DCK_VGA3_RED
VGA3_HSYNC VGA3_BLUE
VGA3_VSYNC VGA3_GREEN
VGA3_RED
VGA3_DDCC
VGA3_DDCD CHP3_DCKIN*
VGA3_CLK-
VGA3_CLK+
VGA3_A0-
VGA3_A0+
VGA3_A1-
VGA3_A1+
VGA3_A2-
VGA3_A2+
DVO1_DPMS
CHP3_SUSCLK
This Document can not be used without Samsung's authorization.
VGA3_BKLTON
VGA3_LCDVDDON
CLK3_DREF
CLK3_DREFSSCLK
DVO1_DPMS CPU1_DPWR*
CPU1_DPSLP*
PCI3_RST*
AGP3_BUSY* IMVP4_PWRGD
CLK3_MCH66
5-1-1(h) System Main Board Schematic Sheet 9 of 40(GMCH-M)
Place near GMCH -10mil wide
-20mil spacing
GST2
5-9
5 System Schematic Diagrams and PCB Silkscreen
5 System Schematic Diagrams and PCB Silkscreen This Document can not be used without Samsung's authorization.
5-1-1(i) System Main Board Schematic Sheet 10 of 40(GMCH-M)
VCCQSM
VCCASM
Place two caps near MGM ACAP
VCCADPLLA
VCCADPLLB
VCCADPLLB
VCCQSM
VCCADPLLA
VCCASM
5-10 Sens Q 20
D0 D1
MEM2_RMAA(0) MEM2_RMAA(0)
MEM2_MAB(2:1) MEM2_MAB(2:1)
Sens Q 20
MEM2_RMAA(3) MEM2_RMAA(3)
MEM2_MAB(5:4) MEM2_MAB(5:4)
MEM2_RMAA(12:6) MEM2_RMAA(12:6)
MEM2_RMD(15:0) MEM2_RMD(31:16)
MEM2_RBS0 MEM2_RBS0
MEM2_RBS1 MEM2_RBS1
MEM2_RSWEA* MEM2_RSWEA*
MEM2_RSCASA* MEM2_RSCASA*
MEM2_RSRASA* MEM2_RSRASA*
MEM2_CSA2* MEM2_CSA2*
MEM2_RDM(1) MEM2_RDM(3)
MEM2_RDM(0) MEM2_RDM(2)
MEM2_RDQS(1) MEM2_RDQS(3)
MEM2_RDQS(0) MEM2_RDQS(2)
MEM2_CKE2 MEM2_CKE2
CLK2_MCLK3
Close to memory as you can!
Close to memory as you can!
CLK2_MCLK3* D2 D3
This Document can not be used without Samsung's authorization.
MEM2_RMAA(0) MEM2_RMAA(0)
MEM2_MAB(2:1) MEM2_MAB(2:1)
MEM2_RMAA(3) MEM2_RMAA(3)
MEM2_MAB(5:4) MEM2_MAB(5:4)
MEM2_RMAA(12:6) MEM2_RMAA(12:6)
MEM2_RMD(47:32) MEM2_RMD(63:48)
MEM2_RBS0 MEM2_RBS0
MEM2_RBS1 MEM2_RBS1
MEM2_RSWEA* MEM2_RSWEA*
MEM2_RSCASA* MEM2_RSCASA*
MEM2_RSRASA* MEM2_RSRASA*
MEM2_CSA2* MEM2_CSA2*
MEM2_RDM(5) MEM2_RDM(7)
MEM2_RDM(4) MEM2_RDM(6)
MEM2_RDQS(5) MEM2_RDQS(7)
MEM2_RDQS(4) MEM2_RDQS(6)
MEM2_CKE2 MEM2_CKE2
5-1-1(j) System Main Board Schematic Sheet 11 of 40(DDR-ON BOARD)
Close to memory as you can! Close to memory as you can!
CLK2_MCLK4
CLK2_MCLK4*
5-11
5 System Schematic Diagrams and PCB Silkscreen
5-12
MEM2_MAA(0)
MEM2_MAA(2:1) MEM2_MD(63:0)
MEM2_MAA(3)
MEM2_MAA(5:4)
MEM2_MAA(12:6)
MEM2_BS0
MEM2_BS1
CLK2_MCLK0
CLK2_MCLK0*
CLK2_MCLK1*
CLK2_MCLK1
5 System Schematic Diagrams and PCB Silkscreen
MEM2_CKE0
MEM2_CKE1
MEM2_SCASA*
MEM2_SRASA*
MEM2_SWEA*
MEM2_CSA0*
MEM2_CSA1*
SMB3_CLK
SMB3_DATA
MEM2_DM(7:0)
MEM2_DQS(7:0)
5-1-1(k) System Main Board Schematic Sheet 12 of 40(DDR-SODIMM)
P/N : 3709-001193
SMBUS Addr : 1010000X
This Document can not be used without Samsung's authorization.
Sens Q 20
Sens Q 20
DATA Signal Routing Topology SDQ[63:0] : DATA BUS
Vtt
SDQ[71:64] : CHECK BITS FOR ECC
SDQS[8:0] : DATA STROBE
GMCH L1 L2 Rs L3 L4 Rt SDM[8:0] : DATA MASK
SODIMM Pad On Board
MEM2_MD(63:0)
MEM2_RMD(63:0)
MEM2_RMD(63:0)
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MEM2_DQS(7:0) MEM2_RDQS(7:0) MEM2_RDQS(7:0)
5-1-1(l) System Main Board Schematic Sheet 13 of 40(SERIES & TERMINATION)
5-13
5 System Schematic Diagrams and PCB Silkscreen
5-14
Command Signals Control Signal Routing Topology
SMA[12:6,3,0], SBS[1:0], RAS*, CAS*,WE* SCKE[3:0], SCS#[3:0]
Vtt CPC signals
SMA[5,4],[2,1] SMB[5,4],[2,1] Vtt
GMCH L1 L2 Rs L3 L4 Rt
GMCH L1 L2 Rt
SODIMM 0 Pad On Board
SODIMM 0 Pad / On Board
Command Signal can not be placed within the R-packs as data, strobe or control signals
MEM2_MAB(1)
MEM2_MAB(2)
MEM2_MAB(4)
MEM2_BS0 MEM2_RBS0 MEM2_MAA(1) MEM2_MAB(5)
MEM2_BS1 MEM2_RBS1 MEM2_MAA(2)
MEM2_SWEA* MEM2_RSWEA* MEM2_MAA(4)
MEM2_SCASA* MEM2_RSCASA* MEM2_MAA(5) MEM2_CSA0*
MEM2_SRASA* MEM2_RSRASA* MEM2_CSA1*
MEM2_CSA2*