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1 2 3 4 5 6 7 8
PCB STACK UP
6L QT6 BLOCK DIAGRAM 01
CPU CPU THERMAL
SENSOR
LAYER 1 : TOP Penryn 14.318MHz
A PAGE 4 A
LAYER 2 : SGND
478P (uPGA)/35W
LAYER 3 : IN1 PAGE 3,4 CLK_CPU_BCLK,CLK_CPU_BCLK#
CLK_MCH_BCLK,CLK_MCH_BCLK# CLOCK GEN
LAYER 4 : IN2 DREFCLK,DREFCLK# ALPRS355B MLF64PIN
FSB 667/800/1066
LAYER 5 : VCC DREFSSCLK,DREFSSCLK#
PAGE 2
LAYER 6 : BOT
PS8101
HDMI CON
NORTH BRIDGE PAGE 20 PAGE 20
DDRII-SODIMM1 DDRII 667/800 MHz
PAGE 12,13 CRT
Cable VGA Cantiga
PAGE 20
Docking RJ-45 DDRII 667/800 MHz
DDRII-SODIMM2
B
CIR/Pwr btn Dual Link B
LCD CONN
SPDIF Out PAGE 12,13 PAGE 5~9
Stereo MIC PAGE 19
Mini PCI-E Card x2
Headphone Jack Express Card x1
USB Port DMI LINK 32.768KHz
NBSRCCLK, NBSRCCLK# Cable Docking x1
PAGE 37 VOL Cntr
TWO SATA - HDD
SATA0,1 150MB USB2.0 4,7,10,11
PAGE 33 0,1,8,9 5 3 2 12MHz 6
SYSTEM CHARGER(ISL6251AHAZ-T)
SOUTH BRIDGE USB2.0 Ports BlueTooth Webcam Fingerprint
PAGE 38
SATA - CD-ROM
SATA4 150MB X4 PAGE 30 PAGE 30 PAGE 30 PAGE 30
Card Reader
PAGE 33 RTS5158
SYSTEM POWER ISL6237IRZ-T PAGE 25
ICH-9M
PAGE 39
E-SATA
SATA5 150MB PCI-E
PAGE 30 X3 X1 X1
C DDR II SMDDR_VTERM Azalia C
1.8V/1.8VSUS(TPS51116REGR) Mini PCI-E
PAGE 43
Accelerometer
PAGE 28
SMBUS PAGE 21,22,23,24 LAN Express
LIS3LV02DL Card Realtek Card
IDT PCIE-LAN (NEW CARD)
VCCP +1.5V AND GMCH (Wireless RTL8101E/8111C
1.05V(RT8204) 32.768KHz LPC 92HP61B7X5NLGXA1
LAN/ROBSON/TV) (10/100/GagaLAN) PAGE 33
PAGE 40 MDC CONN PAGE 27
PAGE 36
PAGE 31,32
PAGE 29
CPU CORE ISL6266A
PAGE 41 Keyboard ENE KBC
RJ45 25MHz
Touch Pad PAGE 35 KB3926 B1 SPI for AUDIO
Amplifier
KB3926 C0 HDCP
TPA6017A2 PAGE 31
Capacitive Sense PAGE 22
PAGE 28
SW PAGE 34 PAGE 35
D
microphone Audio Jacks Jack to D
(Phone/ MIC) Speaker
PAGE 27 PAGE 27 PAGE 28
GMT G9931P1U
SPI PROJECT : QT6
FAN PAGE 35 Quanta Computer Inc.
PAGE 37
Size Document Number Rev
Custom
NB5 Block Diagram 2A
Date: Monday, October 29, 2007 Sheet 1 of 44
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
3,4,6,9,10,11,19,20,21,22,23,24,27,28,29,30,31,33,35,36,37,41,44 +3V
02
3,4,5,6,8,9,21,24,34,40,41 +1.05V
+3V
L38
1 2 +3V_CK_MAIN
HCB1608KF-181T15 U21
C513
C562 C511 C509 C541 C508 +3V_CK_MAIN 23 61
VDDPLL3 CPUCLKT0 CLK_CPU_BCLK 3
10U/6.3V_8 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 16 60
A VDD48 CPUCLKC0 CLK_CPU_BCLK# 3 A
9 SRC8 RP49 4 3 *4P2R-S-0
4
VDDPCI
VDDREF
CK505 CPUCLKT1 58 CLK_MCH_BCLK 5
SRC8# 2 1
CLK_CPU_ITP 3
CLK_CPU_ITP# 3
L42 46 57
VDDSRC CPUCLKC1 CLK_MCH_BCLK# 5
1 2 +3V_CK_CPU +3V_CK_CPU 62
HCB1608KF-181T15 VDDCPU SRC8
CPUT2_ITP/SRCT8 54 modify for SI Build
+3V_CK_MAIN2 19 53 SRC8#
C542 C530 VDD96I/O CPUC2_ITP/SRCC8
27 VDDPLL3I/O
10U/6.3V_8 .1U/10V_4 33 20 SRC0
VDDSRCI/O DOTT_96/SRCT0 SRC0#
43 VDDSRCI/O DOTC_96/SRCC0 21 int
52 SRC0 RP47 2 1 4P2R-S-0
VDDSRCI/O DREFCLK 6
24 SRC1 SRC0# 4 3
27MHz_Nonss/SRCCLK1/SE1 DREFCLK# 6
L43 56 25 SRC1#
+3V_CK_MAIN2 VDDCPU_IO 27Mhz_ss/SRCCLC1/SE2
1 2 55 NC
HCB1608KF-181T15 28 int
SRCCLKT2/SATACL CLK_PCIE_NEW 33
29 SRC1 RP50 2 1 4P2R-S-0
SRCCLKC2/SATACL CLK_PCIE_NEW# 33 DREFSSCLK 6
C554 C549 C561 C529 C566 C547 C539 CG_XIN 3 SRC1# 4 3
X1 DREFSSCLK# 6
10U/6.3V_8 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 CG_XOUT 2 31
X2 SRCCLKT3/CR#_C
SRCCLKC3/CR#_D 32
*100K/F_4 R317 34
SRCCLKT4 CLK_PCIE_3GPLL 6
SRCCLKC4 35 CLK_PCIE_3GPLL# 6
23 CK_PWG 63 CK_PWRGD/PD# PCI_STOP# 45 PM_STPPCI# 23
+3V CPU_BSEL1 R312 2.2K_4 FSB 64 44
+3V FSLB/TEST_MODE CPU_STOP# PM_STPCPU# 23
SRCCLKT6 48 CLK_PCIE_ICH 22
SRCCLKC6 47 CLK_PCIE_ICH# 22
2
7 SCLK SRCCLKT7/CR#_F 51 CLK_PCIE_WLAN 36
Q15 R297 R296 10,11,28,33,36 CGCLK_SMB 6 50
SDATA SRCCLKC7/CR#_E CLK_PCIE_WLAN# 36
2
B R279 10K/F_4 10K/F_4 10,11,28,33,36 CGDAT_SMB B
10K/F_4 2N7002 37
SRCCLKT9 CLK_PCIE_LAN 31
3 1 CGDAT_SMB 22 38
23 PDAT_SMB CLK_PCIE_LAN# 31
1
GND SRCCLKC9
26 GND
TME 18 41
GND48 SRCCLKT10 CLK_PCIE_SATA 21
59 GNDCPU SRCCLKC10 42 CLK_PCIE_SATA# 21
15 GNDPCI
+3V 1 40
GNDREF SRCCLKT11/CR#_H CLK_PCIE_TVC 36
30 GNDSRC SRCCLKC11/CR#_G 39 CLK_PCIE_TVC# 36
Q16 36 GNDSRC
2
49 GNDSRC
2N7002 8 R_CLK_NEWCARD_OE# R295 475/F_4
PCICLK0/CR#_A CLK_NEWCARD_OE# 33
3 1 CGCLK_SMB 10 R_CLK_MCH_OE# R280 475/F_4
23 PCLK_SMB PCICLK1/CR#_B CLK_MCH_OE# 6
11 TME R276 33_4
PCICLK2/TME PCLK_DEBUG 36
12 R_PCLK_KBC R288 33_4
PCICLK3 PCLK_KBC 35
13 27M_SEL
PCICLK4/27_SELECT
0=overclocking ITP_EN R285 33_4
Y3 65 PCLK_ICH 22
of CPU and EPAD
SRC Allowed CG_XIN 1 2 CG_XOUT 14 R308 22_4
PCI_F5/ITP_EN CLK_48M_USB 23
R303 22_4
CLK_48M_CR 25
1 = overclocking 17 FSA R315 2.2K_4 CPU_BSEL0
14.318MHZ USB_48MHZ/FSLA
1
1
FSC R289 10K/F_4 CPU_BSEL2
of CPU and SRC C507 C512 5 FSLC R298 33_4
FSLC/TST_SL/REF CLK_14M_ICH 23
not Allowed 30P/50V_4 30P/50V_4
2
2
ICS9LPRS355BKLF MLF64
C C
modify for SI Build
CK505 QFN64
ICS ICS9LPRS355BKLF ALPRS355000 +3V
27M_SEL
PIN20 PIN21 PIN24 PIN25 Silego SLG8SP513VTR AL8SP513000
27M_SEL PIN13 CLK_MCH_OE# R277 2 1 10K/F_4
Realtek RTM875N-606-VD-GR AL000875000
2
0=UMA DOT96T DOT96C SRCT1/LCDT_100 SRCT1/LCDT_100 CLK_NEWCARD_OE# R294 2 1 10K/F_4
int R299
10K/F_4
1 = External
1
VGA SRCT0 SRCC0 27Mout-NSS 27Mout-SS
0=UMA modify for SI Build
PCLK_KBC
1 = External VGA C501 *33P/50V_4
FSC FSB FSA CPU SRC PCI C503 *27P/50V_4 PCLK_ICH
CPU Clock select
+3V C495 *33P/50V_4 PCLK_DEBUG
CPU_BSEL0 R321 1K/F_4
1 0 1 100 100 33
3 CPU_BSEL0 MCH_BSEL0 6
0 0 1 133 100 33 C518 10P/50V_4 CLK_48M_USB
2
0 1 1 166 100 33 C514 10P/50V_4 CLK_48M_CR
*10K/F_4 R314 1K/F_4
R291 0 1 0 200 100 33 C506 *33P/50V_4 CLK_14M_ICH
R_PCLK_KBC CPU_BSEL1 R316 1K/F_4
3 CPU_BSEL1 MCH_BSEL1 6
1
D D
0 0 0 266 100 33 for EMI
ITP_EN
1 0 0 333 100 33
2
2
+1.05V R322 1K/F_4
R283 1 1 0 400 100 33
10K/F_4 *10K/F_4 CPU_BSEL2 R278 1K/F_4
PROJECT : QT6
3 CPU_BSEL2 MCH_BSEL2 6
R292 1 1 1 RSVD 100 33
1K to NB only when
Quanta Computer Inc.
1
1
XDP is implement.No
+1.05V R281 1K/F_4 XDP can use 0 ohm
Enable ITP CLK
Size Document Number Rev
Custom
NB5 Clock Generator 2A
Date: Monday, October 29, 2007 Sheet 2 of 44
1 2 3 4 5 6 7 8
5 4 3 2 1
2,4,5,6,8,9,21,24,34,40,41 +1.05V
5 H_A#[35:3]
H_A#3
H_A#4
J4
U34A
A[3]# ADS# H1 H_ADS# 5 5 H_D#[63:0]
U34B H_D#[63:0]
03
L5 A[4]# BNR# E2 H_BNR# 5
ADDR GROUP 0
H_A#5 L4 G5 H_D#0 E22 Y22 H_D#32
A[5]# BPRI# H_BPRI# 5 D[0]# D[32]#
H_A#6 K5 H_D#1 F24 AB24 H_D#33
H_A#7 A[6]# H_D#2 D[1]# D[33]# H_D#34
M3 A[7]# DEFER# H5 H_DEFER# 5 E26 D[2]# D[34]# V24
H_A#8 N2 F21 H_D#3 G22 V26 H_D#35
A[8]# DRDY# H_DRDY# 5 D[3]# D[35]#
H_A#9 J1 E1 H_D#4 F23 V23 H_D#36
D A[9]# DBSY# H_DBSY# 5 D[4]# D[36]# D
H_A#10 N3 H_D#5 G25 T22 H_D#37
H_A#11 A[10]# H_D#6 D[5]# D[37]# H_D#38
P5 A[11]# BR0# F1 HBREQ#0 5 E25 D[6]# D[38]# U25
DATA GRP 0
DATA GRP 2
DATA GRP 2
H_A#12 P2 H_D#7 E23 U23 H_D#39
A[12]# D[7]# D[39]#
CONTROL
H_A#13 L2 D20 H_IERR# R138 56.2/F_4 +1.05V H_D#8 K24 Y25 H_D#40
H_A#14 A[13]# IERR# H_D#9 D[8]# D[40]# H_D#41
P4 A[14]# INIT# B3 H_INIT# 21 G24 D[9]# D[41]# W22
H_A#15 P1 H_D#10 J24 Y23 H_D#42
H_A#16 A[15]# H_D#11 D[10]# D[42]# H_D#43
R1 A[16]# LOCK# H4 H_LOCK# 5 J23 D[11]# D[43]# W24
M1 H_D#12 H22 W25 H_D#44
5 H_ADSTB#0 ADSTB[0]# H_CPURST# 5 D[12]#