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A B C D E
1 1
2
HTW2E 2
LA-3201P REV 1.0 Schematic
3 3
UFC-PGA Yonah/ RC410MD(ME)/ SB450
2006-04-18 Rev. 1.0
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/11/01 Deciphered Date 2006/11/01 Title
Black Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B HTW2E(LA-3201P) 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 21, 2006 Sheet 1 of 46
A B C D E
A B C D E
HTW2E LA-3201P FUNCTION BLOCK DIAGRAM
4
Mobile Yonah 4
uFCPGA-479 Pin Thermal Sensor Clock Generator
CPU VID
FANController PAGE 33
ICS951411AGT
ADM1032ARM
PAGE 4,5,6 PAGE 5 PAGE 11 PAGE 5 RTC Battery PAGE 15
CRT Conn.
FSB
533 MHz DC/DC Interface
page 14 PAGE 34
Power Buttom
LCD Conn
page 13 PAGE 31
ATI-RC410MD 400/533/667MHz
(1.8V) SO-DIMM x 2(DDRII)
Memory Bus BANK 0,1,2,3 PAGE 10,11
LVDS & TV-OUT Conn. VGA M10P Embeded
page 13 DCIN&DETECTOR
3 PAGE 35 3
PCI-E X1 707 pin BGA
PAGE 7,8,9
BATT CONN/OTP
A-Link Express x 4
PAGE 36
Bandwidth 500MB
2.5GHz(1.2V)
Mini Card
CHARGER PAGE 37
FOR WLAN
PAGE 24 480MHz(5V) USB 2.0 Port *3
0,2,4 PAGE 28
3V/5V/12V PAGE 38
Primary SATA DDR_1.8V/0.9VEP
3.3V,5V 1.5GHz(150MB/s) PAGE 39
SATA HDD
PCI BUS
33MHz (3.3V) ATI-SB450 PAGE 17
1.8VCORE PAGE 39
564 pin BGA Secondary
2 ATA-100 (5V) 2
IDE ODD 1.5V/PROCHOT PAGE 40
PAGE 15,16,17,18,19 PAGE 27
CARDBUS VIA6311S LAN
CB1410
RTL8100CL
PAGE 23 PAGE 20 LPC BUS 33MHz (3.3V) CPU_CORE PAGE 41
PAGE 21
Embedded AZALIA
TPM 24MHz(3.3V) HD CODEC Audio Amplifier
CARD BUS 1394-Port RJ-45 SLB 9635
Controller ALC 861
PAGE 23 PAGE 20 PAGE 25 APA2068 PAGE 26
SOCKET PAGE 27
ENE KB910PAGE 29
PAGE 22
MOM
BIOS(1M) Scan KB PAGE 43,43
& I/O PORT PAGE 32
1 1
PAGE 30
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/11/01 Deciphered Date 2006/11/01 Title
Black Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS CustomHTW2E(LA-3201P) 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 21, 2006 Sheet 2 of 46
A B C D E
A B C D E
SIGNAL
Voltage Rails STATE SLP_S3# SLP_S5# +VALW +V +VS Clock
Full ON HIGH HIGH ON ON ON ON
Power Plane Description S1 S3 S5
S1(Power On Suspend) HIGH HIGH ON ON ON LOW
VIN Adapter power supply (19V) ON ON ON
1 B+ AC or battery power rail for power circuit. ON ON ON S3 (Suspend to RAM) LOW HIGH ON ON OFF OFF 1
+CPU_CORE Core voltage for CPU ON OFF OFF
S4 (Suspend to Disk) LOW HIGH ON OFF OFF OFF
+CPUVID 1.2V switched power rail for CPU AGTL Bus ON OFF OFF
+VGA_CORE 1.0V/1.2V switched power rail for VGA chip ON OFF OFF S5 (Soft OFF) LOW LOW ON OFF OFF OFF
+1.2VS 1.2VS for PCI-Express ON OFF OFF
+0.9VS 0.9V switched power rail ON OFF OFF
+1.5VS DOTHAN B ON OFF OFF
Board ID Table for AD channel
+1.8VS 1.8VS switched power rail ON OFF OFF
+1.8VALW 1.8V always on power rail ON ON ON* Vcc 3.3V +/- 5%
+1.8V 1.8V power rail ON ON OFF Ra 100K +/- 5%
+3VALW 3.3V always on power rail ON ON ON* Board ID Rb V AD_BID min V AD_BID typ V AD_BID max
+3VS 3.3V switched power rail ON OFF OFF 0 0 0 V 0 V 0 V
+5VALW 5V always on power rail ON ON ON* 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+5VS 5V switched power rail ON OFF OFF 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+12VALW 12V always on power rail ON ON ON* 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
2 2
+RTCVCC RTC power ON ON ON 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
5 100K +/- 5% 1.453 V 1.650 V 1.759 V
6 200K +/- 5% 1.935 V 2.200 V 2.341 V
7 NC 2.500 V 3.300 V 3.300 V
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
External PCI Devices
Device IDSEL# REQ#/GNT# Interrupts Board ID PCB Revision BTO BOM STURCTURE
TI 1410 AD20 2 PIRQB 0 0.1 WIRELESS WLAN@
LAN A D22 1 PIRQG 1 0.2 1394 1394@
1394 AD16 0 PIRQA 2 0.3
3 1.0
4
5
3 3
6
7
EC SM Bus1 address EC SM Bus2 address SKU ID BTN_ID SKU_ID
Device Address Device Address
0 1 Buttons 0 WW
Smart Battery 0001 011X b ADM1032 1001 110X b
1 7 Buttons 1 JP
2 2
3 3
4 4
5 5
6 6
7 7
SB450 SM Bus address
Device Address
4 4
Clock Generator 1101 001Xb
(ICS951413BGLFT)
DDR DIMM0 1010 0100b A4
DDR DIMM1 1010 0110b A6 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title
Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B HTW2E(LA-3201P) 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 21, 2006 Sheet 3 of 46
A B C D E
5 4 3 2 1
7 H_A#[3..31] H_D#[0..63] 7
JCPU1A
+3VS
H_A#3 J4 E22 H_D#0
H_A#4
H_A#5
L4
A3#
A4#
YONAH D0#
D1# F24 H_D#1
H_D#2 +1.05VS +CPU_CORE
M3 A5# D2# E26
H_A#6 K5 H22 H_D#3
H_A#7 A6# D3# H_D#4
M1 A7# D4# F23 1
1
1
1
H_A#8 N2 G25 H_D#5
H_A#9 A8# D5# H_D#6 R463 R464 C663 R465
D J1 A9# D6# E25 D
H_A#10 N3 E23 H_D#7 0.1U_0402_16V4Z @ 10K_0402_5%
H_A#11 A10# D7# H_D#8 @ 47K_0402_5% 47K_0402_5% 2
P5 A11# D8# K24
H_A#12 P2 G24 H_D#9 1
MAINPWON 16,35,36,38
2
2
2
H_A#13 A12# D9# H_D#10 C664 U26
L1 A13# D10# J24
1
H_A#14 P4 J23 H_D#11 C H_THERMDA 2 1
H_A#15 A14# D11# H_D#12 2200P_0402_50V7K D+ VDD1
P1 A15# D12# H26 1 2 2
H_A#16 H_D#13 @ 0.1U_0402_16V4Z B Q53 2 H_THERMDC 3
R1 A16# D13# F26 D- ALERT# 6
H_A#17 Y2 K22 H_D#14 C665 E 2SC2411K_SC59
3
H_A#18 A17# D14# H_D#15
U5 A18# D15# H25 29 EC_SMB_CK2 8 SCLK THERM# 4
H_A#19 R3 N22 H_D#16
H_A#20 A19# D16# H_D#17
W6 A20# D17# K25 29 EC_SMB_DA2 7 SDATA GND 5
H_A#21 U4 P26 H_D#18 +1.05VS 1 2
H_A#22 A21# D18# H_D#19 R466
Y5 R23
H_A#23
H_A#24
H_A#25
U2
R4
A22#
A23#
A24#
D19#
D20#
D21#
L25
L22
H_D#20
H_D#21
H_D#22
A H_THERMTRIP#
56_0402_5% ADM1032ARM_RM8
T5 A25# ADDR GROUP DATA GROUP D22# L23
H_A#26 T3 M23 H_D#23
H_A#27 A26# D23# H_D#24
W3 A27# D24# P25
H_A#28 W5 P22 H_D#25
H_A#29 A28# D25# H_D#26
Y4 A29# D26# P23
H_A#30 W2 T24 H_D#27
H_A#31 A30# D27# H_D#28
7 H_REQ#[0..4] Y1 A31# D28# R24
L26 H_D#29
H_REQ#0 D29# H_D#30
K3 REQ0# D30# T25
H_REQ#1 H2 N24 H_D#31
H_REQ#2 REQ1# D31# H_D#32 +3VALW
K2 REQ2# D32# AA23
H_REQ#3 J3 AB24 H_D#33 +1.05VS
H_REQ#4 REQ3# D33# H_D#34
L5 REQ4# D34# V24
1
V26 H_D#35 +1.05VS
H_ADSTB#0 D35# H_D#36
7 H_ADSTB#0 L2 ADSTB0# D36# W25
H_ADSTB#1 V4 U23 H_D#37 R467
7 H_ADSTB#1 ADSTB1# D37#
2
C H_D#38 330_0402_5% C
D38# U25
1
1
U22 H_D#39
2
D39# H_D#40 R468 R469 R470
D40# AB25
W22 H_D#41 470_0402_5% 75_0402_5% @ 56_0402_5%
D41# H_PROCHOT# 16
Y23 H_D#42
1
CLK_BCLK D42# H_D#43 H_DPRSTP# 2
12 CLK_BCLK A22 AA26 1
2
2
BCLK0 D43#
1
CLK_BCLK# A21 HOST CLK Y26 H_D#44 R471 0_0402_5% C
12 CLK_BCLK# BCLK1 D44#
B
1
Y22 H_D#45 2 Q54
D45# H_D#46 Q55 B @ PMBT3904_SOT23
D46# AC26 2 1 2 DPRSLPVR 15,41
AA24 H_D#47 MMBT3904_SOT23 R472 470_0402_5% E
3
H_ADS# D47# H_D#48
H1 AC22
7 H_ADS#
C
3
H_BNR# ADS# D48# H_D#49 PROCHOT#
7 H_BNR# E2 BNR# D49# AC23
H_BPRI# G5 AB22 H_D#50
7 H_BPRI# H_BR0# BPRI# D50# H_D#51
7 H_BR0# F1 BR0# D51# AA21
H_DEFER# H5 AB21 H_D#52
7 H_DEFER# H _DRDY# DEFER# D52# H_D#53
7 H_DRDY# F21 DRDY# D53# AC25
H_HIT# G6 AD20 H_D#54
7 H_HIT# HIT# D54#
H_HITM# E4 CONTROL AE22 H_D#55
7 H_HITM# HITM# D55#
H_IERR# D20 AF23 H_D#56
H_LOCK# IERR# D56# H_D#57 +1.05VS
7 H_LOCK# H4 LOCK# D57# AD24
H_RESET# B1 AE21 H_D#58
7,15 H_RESET# RESET# D58# H_D#59
D59# AD21
AE25 H_D#60
7 H_RS#[0..2] D60#
H_RS#0 F3 AF25 H_D#61
H_RS#1 RS0# D61# H_D#62
F4 RS1# D62# AF22
H_RS#2 G3 AF26 H_D#63
H_TRDY# RS2# D63# H_DPRSTP# R473 2
7 H_TRDY# G2 TRDY# 1 @ 56_0402_5%
J26 H_RESET# R474 2 1 @ 54.9_0402_1%
DINV0# H_DINV#0 7
DINV1# M26 H_DINV#1 7
AD4 V23 ITP_TMS R475 2 1 40.2_0402_1%
BPM0# DINV2# H_DINV#2 7
B AD3 AC20 B
BPM1# DINV3# H_DINV#3 7
AD1 ITP_TDI R476 2 1 150_0402_5%
BPM2#
AC4 BPM3# H_DSTBN#[0..3] 7
H23 H_DSTBN#0 ITP_TDO R477 2 1 @ 54.9_0402_1%
ITP_DBRESET# DSTBN0# H_DSTBN#1
C20 DBR# DSTBN1# M24
H_DBSY# E1 W24 H_DSTBN#2
7 H_DBSY# DBSY# DSTBN2#
H_DPSLP# B5 AD23 H_DSTBN#3 H_BR0# R478 1 2 200_0402_5%
B 15
41
7
H_DPSLP#
H_DPRSTP#
H_DPWR#