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1 1




2
Compal Confidential 2




Intel Haswell rPGA Processor with Lynx Point-H
Viper MXM
Date : 2012/12/20
3
Version 0.5 3




4 4




Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9241P
Date: Thursday, December 20, 2012 Sheet 1 of 56
A B C D E
A B C D E




Compal Confidential
Model Name :
File Name :
1 1




LVDS Panel Conn. DDR3-SO-DIMM2, 4
Ch B BANK 0, 1, 2, 3 Page 12


eDP to LVDS eDP Panel Conn. eDP DeMUX eDP
RTD 2136 Page 22
PS8321 Page 36 Intel
DDR3-SO-DIMM1, 3
DP Conn DPC eDPF Haswell DDR3L 1333MHz 1.35V Ch A BANK 0, 1, 2, 3 Page 11
Page 39 DP MUX
PS8338 Page rPGA Processor
36
MXM3.0 Conn PEGx16 rPGA947
Dock Conn DPD AMD:
Page 33 37.5mm*37.5mm
DPE nVidia: Page 4,5,6,7,8,9,10
Page 35 X4
USB3.0 x3
CRT FDI x2 DMI x4 X4
100MHz 100MHz
Dock x1 Page 33

Dock Conn CRT 2.7GT/s 5GT/s
2

Mini DP Conn. ThunderBolt Page 33 VGA Switch X1 Smart card Controller 2



Cactus Ridge 2 to 2 AU9540A51 Page 37
Page 39 CRT MAX14885EETL CRT USB 3.0 x4
VGA Conn X1
Page 36 Page 36 Intel WWANPage 25 SIM Card Page 25
USB 2.0 x 11
X4 Lynx Point
PCI-Express x 8 (ARD PCIE2.0 2.5GT/s) 100MHz
PCH X1 FPR Validity VFM471
Digital MIC Page 28
SATAx4 Page 22
695pin BGA HDA Codec
Port 8 Port 6 Port 5 Port 7 Port 1 Port 2 Port 0 20mm*20mm HD Audio X1
IDT 92HD91 26 Combo Jack Webcam
(GEN1 1.5Gb/S Page 13,14,15,16,17,18,19,20,21 Page Page 22
Page 39
GEN2 3Gb/S




SPI
X1
GEN3 6Gb/S) USB2.0
Page 39
SPK conn




LPC BUS
Page 27
BIOS SPI ROM x1, X1
Card Reader GLAN WLAN ODD mSATA SATA HDD WLAN Page
16 MB Page 30 25
Controller Intel Expresscard (MINI card) Conn. Conn.23 Conn. Page 23
Page 39 Page 23 Page
Clarkville X1
Page 39 Page 25
Page 29 Dock Page 33




33MHz
3 Port 6 Port 13 3


USB 2.0 Bus
SD/MMC Slot RJ45 Conn.
Page 29
Docking connector:
RJ45
USB30*1
USB20*1
Accelerometer Super I/O TPM1.2 DP*2
ST HP3DC2 Page KBC Page 30 EC ROM
28 Parallel port
SMSC LPC47N217 Infineon SLB9656/9635 SMSC KBC1126 SPI(PCH) 2MB Page 30
Page 32
Page 28
Serial port
CPU FAN1 conn. PS2 PS2
Page 24
Line in/Line out
Touch pad daughter board
SATAx2
SMBus (PCH) VGA
Touch Pad Int.KBD
Page 38 Page 38
RTC CKT. Page 13
4 4




Power On/Off CKT.

DC/DC interface CKT. Page 34
Security Classification Compal Secret Data Compal Electronics, Inc.
2012/03/23 2011/06/29 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9241P
Date: Thursday, December 20, 2012 Sheet 2 of 56
A B C D E
5 4 3 2 1




D D




C C




B B




A A




Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/03/23 Deciphered Date 2011/06/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SMBus block diagram_DSC
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9241P
Date: Thursday, December 20, 2012 Sheet 3 of 56
5 4 3 2 1
5 4 3 2 1




+VCCIOA_OUT

PEG_COMP 2 1
D 24.9_0402_1% RC1 D


CAD Note:
Trace width=12 mils ,Spacing=15mil
Max length= 400 mils.

Haswell rPGA EDS
JCPU1A

E23 PEG_COMP
PEG_RCOMP M29 PEG_CRX_GTX_N[0..15] [35] PEG_CTX_GRX_P[0..15]
PEG_CRX_GTX_N0
DMI_CRX_PTX_N0 D21 PEG_RXN_0 K28 PEG_CRX_GTX_N1 PEG_CTX_GRX_P[0..15] [35]
[14] DMI_CRX_PTX_N0 DMI_RXN_0 PEG_RXN_1
DMI_CRX_PTX_N1 C21 M31 PEG_CRX_GTX_N2 PEG_CTX_GRX_N[0..15]
[14] DMI_CRX_PTX_N1 DMI_RXN_1 PEG_RXN_2 PEG_CTX_GRX_N[0..15] [35]
DMI_CRX_PTX_N2 B21 L30 PEG_CRX_GTX_N3
[14] DMI_CRX_PTX_N2 DMI_RXN_2 PEG_RXN_3
DMI_CRX_PTX_N3 A21 M33 PEG_CRX_GTX_N4
[14] DMI_CRX_PTX_N3 DMI_RXN_3 PEG_RXN_4 L32 PEG_CRX_GTX_N5
DMI_CRX_PTX_P0 D20 PEG_RXN_5 M35 PEG_CRX_GTX_N6
[14] DMI_CRX_PTX_P0




PEG
DMI_CRX_PTX_P1 C20 DMI_RXP_0 PEG_RXN_6 L34 PEG_CRX_GTX_N7
[14] DMI_CRX_PTX_P1 DMI_RXP_1 PEG_RXN_7
DMI_CRX_PTX_P2 B20 E29 PEG_CRX_GTX_N8
[14] DMI_CRX_PTX_P2 DMI_RXP_2 PEG_RXN_8
DMI_CRX_PTX_P3 A20 D28 PEG_CRX_GTX_N9
[14] DMI_CRX_PTX_P3




DMI
DMI
DMI_RXP_3 PEG_RXN_9 E31 PEG_CRX_GTX_N10
DMI_CTX_PRX_N0 D18 PEG_RXN_10 D30 PEG_CRX_GTX_N11
[14] DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 C17 DMI_TXN_0 PEG_RXN_11 E35 PEG_CRX_GTX_N12 PEG_CTX_GRX_C_P0 2 1 0.22U_0402_6.3V6K PEG_CTX_GRX_P0
CC1
[14] DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 B17 DMI_TXN_1 PEG_RXN_12 D34 PEG_CRX_GTX_N13 PEG_CTX_GRX_C_N0 2 1 0.22U_0402_6.3V6K PEG_CTX_GRX_N0
CC2
[14] DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 A17 DMI_TXN_2 PEG_RXN_13 E33 PEG_CRX_GTX_N14
[14] DMI_CTX_PRX_N3 DMI_TXN_3 PEG_RXN_14 E32 PEG_CRX_GTX_N15 PEG_CTX_GRX_C_P1 2 1 0.22U_0402_6.3V6K PEG_CTX_GRX_P1
CC3
D17 PEG_RXN_15 L29 PEG_CRX_GTX_P[0..15] [35] 2 1 0.22U_0402_6.3V6K
DMI_CTX_PRX_P0 PEG_CRX_GTX_P0 PEG_CTX_GRX_C_N1 CC4 PEG_CTX_GRX_N1
[14] DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 C18 DMI_TXP_0 PEG_RXP_0 L28 PEG_CRX_GTX_P1
[14] DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 B18 DMI_TXP_1 PEG_RXP_1 L31 PEG_CRX_GTX_P2 PEG_CTX_GRX_C_P2 2 1 0.22U_0402_6.3V6K PEG_CTX_GRX_P2
CC5
C [14] DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 A18 DMI_TXP_2 PEG_RXP_2 K30 PEG_CRX_GTX_P3 PEG_CTX_GRX_C_N2 2 1 0.22U_0402_6.3V6K PEG_CTX_GRX_N2 C
CC6
[14] DMI_CTX_PRX_P3 DMI_TXP_3 PEG_RXP_3 L33 PEG_CRX_GTX_P4
PEG_RXP_4 K32 PEG_CRX_GTX_P5 PEG_CTX_GRX_C_P3 CC7 2 1 0.22U_0402_6.3V6K PEG_CTX_GRX_P3
PEG_RXP_5 L35 PEG_CRX_GTX_P6 PEG_CTX_GRX_C_N3 CC8 2 1 0.22U_0402_6.3V6K PEG_CTX_GRX_N3
PEG_RXP_6 K34 PEG_CRX_GTX_P7
PEG_RXP_7 F29 PEG_CRX_GTX_P8 PEG_CTX_GRX_C_P4 CC9 2 1 0.22U_0402_6.3V6K PEG_CTX_GRX_P4
FDI_CSYNC H29 PEG_RXP_8 E28 PEG_CRX_GTX_P9 PEG_CTX_GRX_C_N4 CC10 2 1 0.22U_0402_6.3V6K PEG_CTX_GRX_N4
[14] FDI_CSYNC




FDI
FDI
FDI_INT J29 FDI_CSYNC PEG_RXP_9 F31 PEG_CRX_GTX_P10
[14] FDI_INT DISP_INT PEG_RXP_10 E30 PEG_CRX_GTX_P11 PEG_CTX_GRX_C_P5 CC11 2 1 0.22U_0402_6.3V6K PEG_CTX_GRX_P5
PEG_RXP_11 F35 PEG_CRX_GTX_P12 PEG_CTX_GRX_C_N5 CC12 2 1 0.22U_0402_6.3V6K PEG_CTX_GRX_N5
PEG_RXP_12 E34 PEG_CRX_GTX_P13
PEG_RXP_13 F33 PEG_CRX_GTX_P14 PEG_CTX_GRX_C_P6 CC13 2 1 0.22U_0402_6.3V6K PEG_CTX_GRX_P6
PEG_RXP_14 D32 PEG_CRX_GTX_P15 PEG_CTX_GRX_C_N6 CC14 2 1 0.22U_0402_6.3V6K PEG_CTX_GRX_N6
PEG_RXP_15 H35 PEG_CTX_GRX_C_N0
PEG_TXN_0 H34 PEG_CTX_GRX_C_N1 PEG_CTX_GRX_C_P7 CC15 2 1 0.22U_0402_6.3V6K PEG_CTX_GRX_P7
PEG_TXN_1 J33 PEG_CTX_GRX_C_N2 PEG_CTX_GRX_C_N7 CC16 2 1 0.22U_0402_6.3V6K PEG_CTX_GRX_N7
PEG_TXN_2 H32 PEG_CTX_GRX_C_N3
PEG_TXN_3 J31 PEG_CTX_GRX_C_N4 PEG_CTX_GRX_C_P8 CC17 1 2 0.22U_0402_6.3V6K PEG_CTX_GRX_P8
PEG_TXN_4 G30 PEG_CTX_GRX_C_N5 PEG_CTX_GRX_C_N8 CC18 1 2 0.22U_0402_6.3V6K PEG_CTX_GRX_N8
PEG_TXN_5 C33 PEG_CTX_GRX_C_N6
PEG_TXN_6 B32 PEG_CTX_GRX_C_N7 PEG_CTX_GRX_C_P9 CC19 1 2 0.22U_0402_6.3V6K PEG_CTX_GRX_P9
PEG_TXN_7 B31 PEG_CTX_GRX_C_N8 PEG_CTX_GRX_C_N9 CC20 1 2 0.22U_0402_6.3V6K PEG_CTX_GRX_N9
PEG_TXN_8 A30 PEG_CTX_GRX_C_N9
PEG_TXN_9 B29 PEG_CTX_GRX_C_N10 PEG_CTX_GRX_C_P10 CC21 1 2 0.22U_0402_6.3V6K PEG_CTX_GRX_P10
PEG_TXN_10 A28 PEG_CTX_GRX_C_N11 PEG_CTX_GRX_C_N10 CC22 1 2 0.22U_0402_6.3V6K PEG_CTX_GRX_N10
PEG_TXN_11 B27 PEG_CTX_GRX_C_N12
PEG_TXN_12 A26 PEG_CTX_GRX_C_N13 PEG_CTX_GRX_C_P11 CC23 1 2 0.22U_0402_6.3V6K PEG_CTX_GRX_P11
PEG_TXN_13 B25 PEG_CTX_GRX_C_N14 PEG_CTX_GRX_C_N11 CC24 1 2 0.22U_0402_6.3V6K PEG_CTX_GRX_N11
PEG_TXN_14 A24 PEG_CTX_GRX_C_N15
PEG_TXN_15 J35 PEG_CTX_GRX_C_P0 PEG_CTX_GRX_C_P12 CC25 1 2 0.22U_0402_6.3V6K PEG_CTX_GRX_P12
PEG_TXP_0 G34 PEG_CTX_GRX_C_P1 PEG_CTX_GRX_C_N12 CC26 1 2 0.22U_0402_6.3V6K PEG_CTX_GRX_N12
PEG_TXP_1 H33 PEG_CTX_GRX_C_P2
B PEG_TXP_2 G32 PEG_CTX_GRX_C_P3 PEG_CTX_GRX_C_P13 CC27 1 2 0.22U_0402_6.3V6K PEG_CTX_GRX_P13 B
PEG_TXP_3 H31 PEG_CTX_GRX_C_P4 PEG_CTX_GRX_C_N13 CC28 1 2 0.22U_0402_6.3V6K PEG_CTX_GRX_N13
PEG_TXP_4 H30 PEG_CTX_GRX_C_P5
PEG_TXP_5 B33 PEG_CTX_GRX_C_P6 PEG_CTX_GRX_C_P14 CC29 1 2 0.22U_0402_6.3V6K PEG_CTX_GRX_P14
PEG_TXP_6 A32 PEG_CTX_GRX_C_P7 PEG_CTX_GRX_C_N14 CC30 1 2 0.22U_0402_6.3V6K PEG_CTX_GRX_N14
PEG_TXP_7 C31 PEG_CTX_GRX_C_P8
PEG_TXP_8 B30 PEG_CTX_GRX_C_P9 PEG_CTX_GRX_C_P15 CC31 1 2 0.22U_0402_6.3V6K PEG_CTX_GRX_P15
PEG_TXP_9 C29 PEG_CTX_GRX_C_P10 PEG_CTX_GRX_C_N15 CC32 1 2 0.22U_0402_6.3V6K PEG_CTX_GRX_N15
PEG_TXP_10 B28 PEG_CTX_GRX_C_P11
PEG_TXP_11 C27 PEG_CTX_GRX_C_P12
PEG_TXP_12 B26 PEG_CTX_GRX_C_P13
PEG_TXP_13 C25 PEG_CTX_GRX_C_P14
PEG_TXP_14 B24 PEG_CTX_GRX_C_P15
PEG_TXP_15


INTEL_HASWELL_HASWELL 1 OF 9




A A




Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/03/23 Deciphered Date 2011/06/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DMI,PEG
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9241P
Date: Thursday, December 20, 2012 Sheet 4 of 56
5 4 3 2 1
5 4 3 2 1



+VCCIO_OUT

SM_DRAMPWROK with DDR Power Gating Topology




0.1U_0402_16V4Z
0.1U_0402_16V4Z




0.1U_0402_16V4Z
1 1
+VCCIO_OUT +VCCIO_OUT




CC33




CC34
+1.35VS
+5VDS 2 2 JXDP1
1 2
GND0 GND1




1
CC35 XDP_PREQ# 3 4 CFG17
1 2 XDP_PRDY# 5 OBSFN_A0 OBSFN_C0 6 CFG16 CFG17 [8]
RC5
7 OBSFN_A1 OBSFN_C1 8 CFG16 [8]
1.8K_0402_1% GND2 GND3
08/10 Add RC106 and change UC1.1 connection to VR_ON 0.1U_0402_10V6K Place near JXDP1 CFG0 9 10 CFG8
[8] CFG0 11 OBSDATA_A0 OBSDATA_C0 12 CFG8 [8]
9/11 Delete RC106 UC1 CFG1 CFG9




2
[8] CFG1 OBSDATA_A1 OBSDATA_C1 CFG9 [8]




5
09/23 Change netname to PWR_GD 13 14
1 CFG2 15 GND4 GND5 16 CFG10




P
[30,31,47] PWR_GD B [8] CFG2 OBSDATA_A2 OBSDATA_C2 CFG10 [8]
4 PM_DRAM_PWRGD_CPU CFG3 17 18 CFG11
D
2 O [8] CFG3 19 OBSDATA_A3 OBSDATA_C3 20 CFG11 [8] D
[14] PM_DRAM_PWRGD A GND6 GND7




G
XDP_OBS0 21 22 CFG19
OBSFN_B0 OBSFN_D0 CFG19 [8]




1
1 2 74AHC1G09GW_TSSOP5 XDP_OBS1 23 24 CFG18
+3VS




3
25 OBSFN_B1 OBSFN_D1 26 CFG18 [8]
RC9 100K_0402_1% Part Number = SA00003Y000 RC10
3.3K_0402_1% CFG4 27 GND8 GND9 28 CFG12
[8] CFG4 29 OBSDATA_B0 OBSDATA_D0 30 CFG12 [8]