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DJ1 Calpella UMA Schematics Document
Arrandale
C
Intel PCH C
2010-04-23
REV : X01
B B
DY : Nopop Component
A A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size Document Number
Cover Page Rev
A3
DJ1 Calpella UMA X01
Date: Monday, April 26, 2010 Sheet 1 of 90
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CPU DC/DC
DJ1 UMA Block Diagram INPUTS
ISL62882
OUTPUTS
47,48
+PWR_SRC +VCC_CORE 39
Project code : 91.4EK01.001
SYSTEM DC/DC
PCB P/N : 48.4EK19.0SB TPS51218 49
INPUTS OUTPUTS
D
Revision : 10212-SB +PWR_SRC +1.05V_VTT
D
Clock Generator
SLG8SP585 SYSTEM DC/DC
RT8205BGQW 46
7 Intel CPU INPUTS OUTPUTS
DDRIII 800/1066 Channel A DDRIII Slot 0 +5V_ALW2
+PWR_SRC +3.3V_RTC_LDO
18
800/1066 +5V_ALW
Arrandale +3.3V_ALW
+15V_ALW
DDRIII 800/1066 Channel B DDRIII Slot 1 SYSTEM DC/DC
19
800/1066 RT8207GQW 50
INPUTS OUTPUTS
+1.5V_SUS
8,9,10,11,12,13,14 +PWR_SRC +0.75V_DDR_VTT
+V_DDR_REF
10/100 NIC RJ45
ATHEROS CONN SYSTEM DC/DC
PCIE x 1 AR8152/AR8151 TPS51611 53
C C
DMIx4 FDIx4x2(UMA) INPUTS OUTPUTS
I/O Board
Connector
CRT RGB CRT
Left Side: +PWR_SRC +CPU_GFX_CORE
55 PCIE x 1
USB x 1
MAXIM CHARGER
LCD LVDS(Dual Channel) BQ24745
54 USB 2.0 x 2 INPUTS OUTPUTS
Intel Mini-Card +DC_IN +PWR_SRC
76 802.11a/b/g +PBATT
PCIE 26
PCH SYSTEM DC/DC
APL5930 51
CardReader
INPUTS OUTPUTS
SD/MMC/MS/ 14 USB 2.0/1.1 ports
Realtek USB2.0 +3.3V_ALW +1.8V_RUN
MS Pro/xD High Definition Audio
71 RTS5138 USB 2.0 x 1
SATA ports (6) USB 2.0 CAMERA 54
32
PCIE ports (8) SYSTEM DC/DC
Switches 42
LPC I/F
B
USB 2.0 x 1
INPUTS
26 OUTPUTS B
ACPI 1.1 Bluetooth 73 +1.5V_SUS +1.5V_RUN
PCI/PCI BRIDGE +5V_ALW +5V_RUN
Azalia AZALIA +3.3V_ALW +3.3V_RUN
CODEC USB 2.0 x 2 Right Side:
Internal Analog MIC
92HD79B1 LPC Bus USB x 2 63
PCB LAYER
20,21,22,23,24,25,26,27,28
L1: Top
30 L2: VCC
L3: Signal
KBC L4: Signal
HP1 SPI L5 GND
NUVOTON
SATA
SATA
L6: Bottom
SPI
NPCE781BA0DX 37
MIC IN
A A
2CH SPEAKER
Flash ROM Flash ROM Touch Int. Thermal
HDD ODD
4MB 62 256kB 62 PAD KB EMC2102 Wistron Corporation
59 59 39 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
68 68 25 Taipei Hsien 221, Taiwan, R.O.C.
Title
Block Diagram
Size Document Number Rev
Fan A3 X01
58 DJ1 Calpella UMA
Date: Monday, April 19, 2010 Sheet 2 of 90
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+PWR_SRC TPS51116
Adapter
1000mA 16825mA
ISL62882 TPS51218 TPS51611
AO4407A +V_DDR_REF +0.75V_DDR_VTT +1.5V_SUS
Charger 48000mA 24800mA 22000mA
BQ24745 +VCC_CORE +1.05V_VTT +CPU_GFX_CORE
Battery +PBATT
AO4468
3500mA
+1.5V_RUN
C C
TPS51125
11145mA
82mA 10330mA
+3.3V_RTC_LDO
+3.3V_ALW
+15V_ALW +5V_ALW2 +5V_ALW
AO4468
G547F2P81U-GP AO4468 G547F2P81U-GP AO3403 APL5930
6661mA
2000mA 6330mA 2000mA 300mA 1761mA
+3.3V_RUN
+5V_USB1 +5V_RUN +5V_USB2 +3.3V_LAN +1.8V_RUN
B B
SI3456DDV RTS5159
2000mA 300mA
+LCDVDD +3.3V_RUN_CARD
Power Shape
Regulator LDO Switch
A A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size Document Number
Power Block Diagram Rev
A3
DJ1 Calpella UMA X01
Date: Friday, April 16, 2010 Sheet 3 of 90
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PCH SMBus Block Diagram
KBC SMBus Block Diagram
+5V_RUN
+3.3V_ALW +3.3V_RUN
SRN10KJ-5-GP
+3.3V_RUN
1
SRN2K2J-1-GP
SRN2K2J-1-GP
TouchPad Conn. 1
PSDAT1 TPDATA
TPDATA TPDATA
DIMM 1 PSCLK1 TPCLK
TPCLK TPCLK
SMBCLK PCH_SMB_CLK
PCH_SMBCLK SCL
SMBDATA PCH_SMB_DATA
PCH_SMBDATA SDA
+KBC_PWR
18
SMBus Address:A0
DMN66D0LDW-7-GP
DIMM 2 SRN4K7J-8-GP
PCH_SMBCLK SCL
PCH_SMBDATA SDA 19 SRN100J-3-GP Battery Conn.
SCL1 BAT_SCL PBAT_SMBCLK1 CLK_SMB
SMBus Address:A4 SDA1 BAT_SDA PBAT_SMBDAT1 DAT_SMB SMBus address:16
Clock
Generator BQ24745
PCH_SMBCLK
PCH_SMBDATA
SCLK
SDATA
KBC SCL
SDA SMBus address:12
7
SMBus address:D2
NPCE781BA0DX
2 +3.3V_RUN 2
PCH +3.3V_ALW Minicard
+3.3V_ALW
PCH_SMBCLK
WLAN
SMB_CLK
+3.3V_RUN
SRN4K7J-8-GP
PCH_SMBDATA SRN4K7J-8-GP
SMB_DATA 76
Thermal
SRN2K2J-1-GP
THERM_SCL SCL
SMBus address:7A
THERM_SDA SDA
SML0CLK SML0_CLK
SML0DATA SML0_DATA
XDP GPIO61/SCL2 KBC_SCL1
DMN66D0LDW-7-GP
GPIO62/SDA2 KBC_SDA1
+3.3V_RUN
PCH
SML1DATA/GPIO75
SRN2K2J-1-GP SML1CLK/GPIO58
L_DDC_CLK LDDC_CLK
L_DDC_DATA LDDC_DATA
LCD CONN 23
3 3
+3.3V_RUN +5V_CRT_RUN
+3.3V_RUN
SRN2K2J-1-GP SRN2K2J-1-GP
CRT_DDC_CLK GMCH_DDCCLK
DDC_CLK_CON
CRT_DDC_DATA GMCH_DDCDATA
DDC_DATA_CON CRT CONN
DMN66D0LDW-7-GP
23
4 4
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
SMBUS Block Diagram
Size Document Number Rev
A2 DJ1 Calpella UMA X01
Date: Friday, April 16, 2010 Sheet 4 of 90
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A B C D E
Thermal Block Diagram Audio Block Diagram
1 1
SPKR_PORT_D_L-
SPKR_PORT_D_R+ SPEAKER
Codec
DP1 EMC2102_DP1
ALC269Q_VB5
SC470P50V3JN-2GP
MMBT3904-3-GP HP1_PORT_B_L HP
HP1_PORT_B_R
2
DN1 EMC2102_DN1
OUT 2
Place near CPU
Thermal and PCH.
EMC2102
DP2 EMC2102_DP1
MMBT3904-3-GP
HP0_PORT_A_L MIC
HP0_PORT_A_R
DN2 EMC2102_DN1 VREFOUT_A_OR_F IN
System Sensor(UMA only)
3 3
DP3 EMC2102_DP3
MMBT3904-3-GP
SC470P50V3JN-2GP
DN3 EMC2102_DN3
Put under CPU. PORTC_L
PORTC_R
Analog
VREFOUT_C MIC
4 4
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
Thermal/Audio Block Diagram
Document Number Rev
Custom
DJ1 Calpella UMA X01
Date: Friday, April 16, 2010 Sheet 5 of 90
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A B C D E
PCH Strapping Processor Strapping
Calpella Schematic Checklist Rev.0_7 Calpella Schematic Checklist Rev.0_7
Name Schematics Notes Pin Name Strap Description Configuration (Default value for each bit is Default
SPKR Reboot option at power-up 1 unless specified otherwise) Value
Default Mode: Internal weak Pull-down.
CFG[4] Embedded 1: Disabled - No Physical Display Port attached to 1
No Reboot Mode with TCO Disabled: Connect to Vcc3_3 with Embedded DisplayPort.
8.2-k- 10-k weak pull-up resistor. DisplayPort
4 Presence 0: Enabled - An external Display Port device is
4
INIT3_3V# Weak internal pull-down. Do not pull high. connected to the Embedded Display Port.
GNT3#/ Default Mode: Internal pull-up. CFG[3] PCI-Express Static 1: Normal Operation. 1
GPIO55 Low (0) = Top Block Swap Mode (Connect to ground with 4.7-k weak Lane Reversal 0: Lane Numbers Reversed 15 -> 0, 14 -> 1, ...
pull-down resistor).
CFG[0] PCI-Express 1: Single PCI-Express Graphics 1
INTVRMEN High (1) = Integrated VRM is enabled Configuration 0: Bifurcation enabled
Low (0) = Integrated VRM is disabled Select
GNT0#, Default (SPI): Left both GNT0# and GNT1# floating. No pull up
GNT1#/GPIO51 required. CFG[7] Reserved - Clarksfield (only for early samples pre-ES1) - 0
Temporarily used Connect to GND with 3.01K Ohm/5% resistor
Boot from PCI: Connect GNT1# to ground with 1-k
pull-down resistor. Leave GNT0# Floating. for early Note: Only temporary for early CFD samples
Clarksfield (rPGA/BGA) [For details please refer to the WW33
Boot from LPC: Connect both GNT0# and GNT1# to ground with samples. MoW and sighting report].
1-k pull-down resistor. For a common motherboard design (for AUB and CFD),
GNT2#/ Default - Internal pull-up. the pull-down resistor should be used. Does not
GPIO53 Low (0)= Configures DMI for ESI compatible operation (for servers impact AUB functionality.
only. Not for mobile/desktops).
GPIO33 Default: Do not pull low.
Disable ME in Manufacturing Mode: Connect to ground with 1-k
pull-down resistor.
3 3
SPI_MOSI Enable iTPM: Connect to Vcc3_3 with 8.2-k weak pull- up resistor.
Disable iTPM: Left floating, no pull-down required.
NV_ALE Enable Danbury: Connect to Vcc3_3 with 8.2-k weak pull-up
resistor.
Disable Danbury: Connect to ground with 4.7-k weak pull-down
resistor.
NC_CLE Weak internal pull-up. Do not pull low.
HAD_DOCK_EN# Low (0): Flash Descriptor Security will be overridden.
/GPIO[33] High (1) : Flash Descriptor Security will be in effect.
HDA_SDO Weak internal pull-down. Do not pull high.
HDA_SYNC Weak internal pull-down. Do not pull high.
GPIO15 Weak internal pull-down. Do not pull high.
GPIO8 Weak internal pull-up. Do not pull low.
GPIO27 Default = Do not connect (floating)
High(1) = Enables the internal VccVRM to have a clean supply for
analog rails. No need to use on-board filter circuit.
Low (0) = Disables the VccVRM. Need to use on-board filter
circuits for analog rails.
2 2
PCIE Routing USB Table
USB
Pair Device
LANE2 MiniCard WLAN 0 USB0 (I/O Board)
1 X
LANE3 LAN 2 USB2
3 USB3
4 X
5 WLAN (I/O Board)
6 X
7 X
8 X
1
1
9 BLUETOOTH
10 CARD READER Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
11 CAMERA Taipei Hsien 221, Taiwan, R.O.C.
12 X Title
13 X
Size Document Number
Table of Content Rev
A3
DJ1 Calpella UMA X01
Date: Friday, April 16, 2010 Sheet 6 of 90
A B C D E
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