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5 4 3 2 1
Xtal 14.318Mhz
300~400mA
SNIPE Block Diagram
VLDT 1.2V S0
VDD 2.5V S3
Vref DDR 1.25V S3
200Mhz
CPU clk VTT 1.25V S3
100/133Mhz
CLK GEN
100Mhz
NB clk Mem Ref 1.25V fr S3 AMD CPU DDR 333/400
DDR x2
ICS 951412 SB clk VDDA 2.5V S0 200-PIN DDR SODIMM
D IDT CV137 100/133Mhz Sempron / Athlon K8 PCB Layer Stackup D
VGA clk VDD VCC_core S0 8,9,10
3
VDDIO 2.5V S3
L1: Signal 1
48Mhz for USB/ Cardbus
4,5,6,7 L2: GND
UMA SVIDEO/COMP
TVOUT 16 L3: Signal 2
HyperTransport L4: Signal 3
Vcore 1.2V S0 6.4GB/S 16b/8b L5: VCC
VDD HT 1.2V S0
Discrete
ATI M26/M24 LVDS L6: Signal 4
VDD 1.8V S0
VDD mem 2.5V S3 ATI RS480M 0.11um, CSP/ BGA 708Pin LCD 17
AGTL+ CPU I/F + UMA PCI Express x16 , 31mmx 31mm
AVDD 3.3 S0( CRT/TV) 1.0~1.3V CMOS technology
AVDDDI , AVDDQ 1.8V S0 ( CRT/TV) 0.13um, 706 BGA package
LVDS 1.8V S0 48
31mmx 31mm
1.0~1.2V CMOS technology 50,51,52 Battery Charger
PLL 1.8V S0
RGB CRT MAX1909ETI
Clock 3.3V S0 11,12,13,14
CRT 16 INPUTS OUTPUTS
AD+ DCBATOUT
Xtal 32.768 Khz BAT+
C
PCI-Express TMDS C
PWR SW TI DVI-D 15 SYSTEM DC/DC 44
PCMCIA x2 VRAM x4
TPS2224AP PCI 7421 MAX1999EEI
SLOT PCIE 1.8V S0
HY5DS573222F 4Mx 32 bit x4= 64MB
8Mx 32 bit x4= 128MB INPUT OUTPUT
28 2* Slot Cardbus 53,54
16Mx 32 bit x4= 256MB
Support
TypeII PCMCIA I/F
1* 1394
VDDQ 3.3V S0 ATI DCBATOUT 5V_S5 ,
3D3V_S5
28
VDD 1.8V S0
SB400 SYSTEM DC/DC
USB x 4
PCI
ACPI 2.0 6xUSB 2.0
24
CODEC TPS 5130 45,46
1394 26,27 3.3 S5, 1.8 S5 INPUT OUTPUT
ALC655 Line In 33
Conn
28 AC97 MIC In DCBATOUT 2D5V_S3
32 1D8V_S5
6-CH 1D2V_S0
AC97 2.2
Line Out
MODEM RJ11
OP AMP
MDC Card CONN 33
29 G1421 CPU V_CORE 42,43
Mini-PCI PCI Bus / 33MHz 24 33
ISL6559CR
802.11a/b/g Int. SPKR
B INPUT OUTPUT B
31 33
LPC Bus / 33MHz
LPC I/F DCBATOUT VCC_CORE_S0
ATA 133 18,19,20,21,22 SYSTEM POWER 47
RJ45 TXFM 1000Mb PCI LAN
30 30 Realtek LP2951ACM/APL5331KAC-TR
RTL8110SBL Thermal
NS SIO KBC XBUS INPUT OUTPUT
1000/100/10 & Fan
PIDE
SIDE
TXFM 10/100Mb PC87381 KB3910
RTL8100C G791 23
30 37 34 2D5V_S3 1D25V_S3
100/10 29 DVD/ DCBATOUT 5V_AUX_S5
HDD
CD-RW
25 25
FIR Touch Int.
ISA ROM
TFDU6102 Pad KB
37 35 35 36
A A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
BLOCK DIAGRAM
Size Document Number Rev
A3 SA
SNIPE
Date: Monday, November 22, 2004 Sheet 1 of 56
5 4 3 2 1
5 4 3 2 1
SA to SB need to check
1. connect G781 Thermal Alert pin to VGA_GPIO14
2. ene KBC P165 LPCRST# , we suggest pull low avoid leakage
3. Clk to NB need to add Cap. when the trace change layer.
4. check page 9. what is the value of R481,R486, R498 and R499 is 100 ohm or 12 ohm.
D 5. check page 15, if on discrete mode does the 1D8V_S0 power for lvds should dummy or still contect on power plan. D
6. check page 19, can the 0 ohm resistance be dummied on P.19 right hand side?
7. check page 20, R203's voltage on pin 2.
8. page 21. check when the unused USB pin should be pull down or floating.
9. Can R471 change to common value?
10. check giga lan and 10/100 connect. Does them the same or can chose a cheaper one?
11. page 38. 12VGATE_S0 can decreased resistance.
12. Does the 1D5V_VGA_S0 can come from TPS5130?
Schematic change:
R659, change from 0R2 to 10Kr2
C C
B B
A A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
CHANGE HISTORY
Size Document Number Rev
A3 SNIPE SA
Date: Thursday, November 18, 2004 Sheet 2 of 56
5 4 3 2 1
A B C D E
3D3V_S0
3D3V_S0 3D3V_CLK_VDD 3D3V_CLK_VDDA
L8 L24
1 2 1 2
1
1
1
1
1
1
1
0R3-U C252 C794 0R3-U
C793 C807 C810 C808 C253
SCD1U16V SCD1U16V SCD1U16V SCD1U16V SC22U10V6ZY-U SCD1U16V SC22U10V6ZY-U
2
2
2
2
2
2
2
RN5 SRN33-2-U2
2 3 SBLINK_CLK# 13
3D3V_CLK_VDDA 1 4 SBLINK_CLK 13
1
1
1
1
4 RN4 1 4 SRN33-2-U2 SBSRC_CLK# 18 4
C800 C801 C811 C812 3D3V_S0 3D3V_CLK_VDD 2 3 SBSRC_CLK 18
SCD1U16V SCD1U16V SCD1U16V SCD1U16V U28
2
2
2
2
L22
1 2 3D3VDD48_S0 3 33 SRC_CLK0#
VDD_48 SRCC0 SRC_CLK0
39 VDDA SRCT0 34
1
0R3-U 32 25 SRC_CLK3#
C787 VDD_SRC SRCC3 SRC_CLK3
SRCT3 24
SC2D2U16V5ZY 21 23
VDD_SRC SRCC4
2
14 VDD_SRC SRCT4 22
35 VDD_SRC SRCC5 19
SRCT5 18
56 VDD_REF SRCC6 17
C206 SC33P50V2JN 51 16
XI_CLK VDD_PC1 SRCT6
1 2 43 VDD_CPU SRCC7 13
48 VDD_HTT SRCT7 12
1
2
X3 R145 40
DUMMY-R3 CPUC1
1 XIN CPUT1 41
DY 2 44 CPUCLKJ_CY R171 1 2 15R2J CPUCLK# 6
XOUT CPUC0 CPUCLK_CY R172 1
X-14D318MHZ-1-U1
CPUT0 45 2 15R2J CPUCLK 6
1
C227 USB_48M 4 USB_48
2
1 2 XO_CLK SMBC_CLK 7
SC33P50V2JN SMBD_CLK SCL ATI_CLK0# RN7
8 SDA SRCC1 29 2 3 NBSRC_CLK# 13
R152 1 2 22R2 30 ATI_CLK0 1 4 NBSRC_CLK 13
27 CLK48_CARDBUS R151 22R2 SRCT1 ATI_CLK1# SRN33-2-U2
21 CLK48_USB 1 2 10 CLKREQ0# SRCC2 28
R158 1 2 0R2-0 11 27 ATI_CLK1 RN6 1 4 GFX_CLK# 449
8,21 SMBC_SB R159 0R2-0 CLKREQ1# SRCT2
8,21 SMBD_SB 1 2 2 3 GFX_CLK 449
SRN33-2-U2
3 FS2 9 36 VGA
3
R155 1 SEL24/24_48# VSS_SRC
13 CLK14_NB 2 33R2 FS1 53 REF1 VSS_SRC 20
R146 1 2 33R2 FS0 54 15
21 SB_OSC_CLK REF0 RESET#
TURBO1 26
R162 1 2 33R2 CLK_REF2 52
37 CLK14_SIO REF2
42
Do not stuff when using UMA
R147 1 13 HTREF_CLK VSS_CPU
32 CLK14_AUDIO 2 33R2 R161 1 2 33R2 CLK_HTT66 47
HTT66 VSS_PCI 49
50 PCI0 VSS_HTT 46
31 SBLINK_CLK# R192 1 2 49D9R2F
IREF_CLKGEN VSS_SRC
37 IREF VSSA 38
5 SBLINK_CLK R193 1 2 49D9R2F
1 VSS_48
1
6 NC#6 VSS_REF 55
R170 R182 SBSRC_CLK# R190 1 2 49D9R2F
49D9R2F
475R2F IDTCV137PAG SBSRC_CLK R191 1 2 49D9R2F
2
2
GFX_CLK# R198 1 2 49D9R2F
GFX_CLK R189 1 VGA 2 49D9R2F
VGA
Do not stuff when using UMA
2 2
VGA_CORE_S0
NBSRC_CLK# R199 1 2 49D9R2F
NBSRC_CLK R200 1 2 49D9R2F
1
1
1
1
C804 C803 C805 C806
SCD1U16V SCD1U16V SCD1U16V SCD1U16V
2
2
2
2
3D3V_CLK_VDD
DY
R148 2K2R2
1 2 FS0
1 R1492
DUMMY-R2
DY
R153 2K2R2
1 DY 2 FS1
1 R154
2
DUMMY-R2
1
DY 1
R169 2K2R2
1 2 DY FS2
1 R160
2 Wistron Corporation
DUMMY-R2 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
DY Taipei Hsien 221, Taiwan, R.O.C.
Title
CLKGEN_IDTCV137
Size Document Number Rev
A3 SA
SNIPE
Date: Thursday, November 18, 2004 Sheet 3 of 56
A B C D E
A B C D E
1D2V_HT0A_S0
1
1
1
1
C81 C67 C82 C83
SCD22U16V3ZY SCD22U16V3ZY SCD22U16V3ZY SCD22U16V3ZY
2
2
2
2
4 4
HTT for CPU sideA HTT for CPU sideB
Transmit power Receive power
and NB sideA Receive and NB sideA
power Transmit power
1D2V_HT0A_S0 U13A 1D2V_HT0B_S0
D29 VLDT0_A VLDT0_B AH29 LAYOUT: Place bypass cap on topside of board near
D27 AH27
VLDT0_A VLDT0_B HTT power pins that are not connected directly to
1
D25 VLDT0_A VLDT0_B AG28
3 C28 VLDT0_A VLDT0_B AG26 C536 downstream HTT device, but connected internally to 3
C26 AF29 SC4D7U10V5ZY
VLDT0_A VLDT0_B other HTT power pins.
2
B29 VLDT0_A VLDT0_B AE28
B27 VLDT0_A VLDT0_B AF25
NB0CADOUT15 T25 N26 CPUCADOUT15 CPUCADOUT[15..0] 11
11 NB0CADOUT[15..0] NB0CADOUTJ15 L0_CADIN_H15 L0_CADOUT_H15 CPUCADOUTJ15
11 NB0CADOUTJ[15..0] R25 L0_CADIN_L15 L0_CADOUT_L15 N27 CPUCADOUTJ[15..0] 11
NB0CADOUT14 U27 L25 CPUCADOUT14
NB0CADOUTJ14 L0_CADIN_H14 L0_CADOUT_H14 CPUCADOUTJ14
U26 L0_CADIN_L14 L0_CADOUT_L14 M25
Used SideB Power Plane NB0CADOUT13 V25 L26 CPUCADOUT13 Used SideA Power Plane
NB0CADOUTJ13 L0_CADIN_H13 L0_CADOUT_H13 CPUCADOUTJ13
U25 L0_CADIN_L13 L0_CADOUT_L13 L27
NB0CADOUT12 W27 J25 CPUCADOUT12
NB0CADOUTJ12 L0_CADIN_H12 L0_CADOUT_H12 CPUCADOUTJ12
W26 L0_CADIN_L12 L0_CADOUT_L12 K25
NB0CADOUT11 AA27 G25 CPUCADOUT11
NB0CADOUTJ11 L0_CADIN_H11 L0_CADOUT_H11 CPUCADOUTJ11
AA26 L0_CADIN_L11 L0_CADOUT_L11 H25
NB0CADOUT10 AB25 G26 CPUCADOUT10
NB0CADOUTJ10 L0_CADIN_H10 L0_CADOUT_H10 CPUCADOUTJ10
AA25 L0_CADIN_L10 L0_CADOUT_L10 G27
NB0CADOUT9 AC27 E25 CPUCADOUT9
NB0CADOUTJ9 L0_CADIN_H9 L0_CADOUT_H9 CPUCADOUTJ9
AC26 L0_CADIN_L9 L0_CADOUT_L9 F25
NB0CADOUT8 AD25 E26 CPUCADOUT8
NB0CADOUTJ8 L0_CADIN_H8 L0_CADOUT_H8 CPUCADOUTJ8
AC25 L0_CADIN_L8 L0_CADOUT_L8 E27
NB0CADOUT7 T27 N29 CPUCADOUT7
NB0CADOUTJ7 L0_CADIN_H7 L0_CADOUT_H7 CPUCADOUTJ7
T28 L0_CADIN_L7 L0_CADOUT_L7 P29
NB0CADOUT6 V29 M28 CPUCADOUT6
NB0CADOUTJ6 L0_CADIN_H6 L0_CADOUT_H6 CPUCADOUTJ6
U29 L0_CADIN_L6 L0_CADOUT_L6 M27
NB0CADOUT5 V27 L29 CPUCADOUT5
NB0CADOUTJ5