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A B C D E
1 1
Compal Confidential
2 2
JDW50/JDY70 Schematics Document
Intel Merom Processor with Crestline(PM945/GM945) + DDRII + ICH7M
(With ATI MXM/B)
3 2007-4-12 3
REV: 0.3
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/1/15 Deciphered Date 2007/12/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JDW50/JDYL70 M/B LA-3771P
Date: Monday, April 16, 2007 Sheet 1 of 44
A B C D E
A B C D E
Compal Confidential
Intel Merom Processor Thermal Sensor Clock Generator
Fan Control
Model Name : JDW50/70 page 33
ADM1032
uPGA-478 Package page 4 page 14
File Name : LA-3771P
(Socket M) page 4,5
1 1
FSB
H_A#(3..35) 533/667MHz H_D#(0..63)
DVI-D Conn. LCD Conn. CRT & TV-out
page 16 page 16 page 17
Intel Memory BUS(DDRII)
LVDS 200pin DDRII-SO-DIMM X2
LVDS SDVO
945/PM/GM/943GML Dual Channel BANK 0, 1, 2, 3 page 12,13
DVI
1.8V DDRII 533/667
uFCBGA-1466
PCI-Express page 6,7,8,9,10,11
MXM II VGA/B
DMI C-Link USB conn x2 Bluetooth CMOS
page 15
page 26
Conn page 27
Camera page 16
USB port 0, 2 USB port 5 USB port 3
PCI-Express
2
Intel ICH7-M 3.3V 48MHz USB
2
3.3V 24.576MHz/48Mhz HD Audio
PCI BUS
3.3V 33 MHz 3.3V ATA-100 IDE
IDSEL:AD20 BGA-652
(PIRQA#,
S-ATA
New Card MINI Card x1 LAN(GbE) GNT#2, page 20,21,22,23
REQ#2)
Socket WLAN Boardcom CDROM MDC 1.5 HDA Codec
page 27 page 26 page 24 ALC268
Card Reader port 0, 1 Conn. 22
page
Conn 30
page page 31
USB port 1 USB port 7
ENE MR510
page 23
RJ45 SATA HDD
page 25
Conn. page 22
4 in 1 Audio AMP
socket page 32
page 23 LPC BUS
3 3
Phone Jack x3
BTN/B Conn. LS3553P
ENE KB926 page 32
RTC CKT. page 28
page 29
page 30
Power On/Off CKT. LED/B Conn. LS3557P Touch Pad Int.KBD
page 29 page 29 page 29
page 30
USB Conn. EC I/O Buffer BIOS
DC/DC Interface CKT. LS3551P page 29 page 29
USB port 4, 6
page 34 page 26
Power Circuit DC/DC AUDIO/B Conn. LS3558P
4 w/Woofer(JDY70) 4
page 35 page 32
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/1/15 Deciphered Date 2007/12/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JDW50/JDYL70 M/B LA-3771P
Date: Monday, April 16, 2007 Sheet 2 of 44
A B C D E
A B C D E
SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Voltage Rails
Full ON HIGH HIGH HIGH HIGH ON ON ON ON
Power Plane Description S1 S3 S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
VIN Adapter power supply (19V) N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
B+ AC or battery power rail for power circuit. N/A N/A N/A
1
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1
+CPU_CORE Core voltage for CPU ON OFF OFF
+0.9VS 0.9V switched power rail for DDR terminator ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.05VS 1.05V switched power rail ON OFF OFF
+1.25VS 1.25V switched power rail ON OFF OFF
+1.5VS 1.5V switched power rail ON OFF OFF Board ID / SKU ID Table for AD channel
+1.8V 1.8V power rail for DDR ON ON OFF Vcc 3.3V +/- 5%
+1.8VS 1.8V switched power rail ON OFF OFF Ra/Rc/Re 100K +/- 5%
+2.5VS 2.5V switched power rail ON OFF OFF Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+3VALW 3.3V always on power rail ON ON ON* 0 0 0 V 0 V 0 V
+3V 3.3V power rail for SB ON ON X 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+3V_LAN 3.3V power rail for LAN ON ON X 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+3VS 3.3V switched power rail ON OFF OFF 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+5VALW 5V always on power rail ON ON ON* 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+5VS 5V switched power rail ON OFF OFF 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
+VSB VSB always on power rail ON ON ON* 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
+RTCVCC RTC power ON ON ON 7 NC 2.500 V 3.300 V 3.300 V
2 2
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
BOARD ID Table BTO Option Table
External PCI Devices Board ID PCB Revision BTO Item BOM Structure
0 0.1 Discrete PM@
Device IDSEL# REQ#/GNT# Interrupts
Card Reader AD16 0 PIRQE
1 UMA GM@
2
3 DVI DVI@
4 SATA*1 SATA*1@
5 SATA*2 SATA*2@
6 Dbg Dbg@
7
EC SM Bus1 address EC SM Bus2 address
3 3
Device Address Device Address
Smart Battery 0001 011X b ADI ADM1032 1001 100X b
EEPROM(24C16/02) 1010 000X b
GMT G781-1 1001 101X b
ICH7M SM Bus address
Device Address
Clock Generator 1101 001Xb
(ICS9LPRS365)
DDR DIMM0 1001 000Xb
DDR DIMM2 1001 010Xb
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/1/15 Deciphered Date 2007/12/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JDW50/JDYL70 M/B LA-3771P
Date: Monday, April 16, 2007 Sheet 3 of 44
A B C D E
5 4 3 2 1
JP22A
H_A#3 J4 E22 H_D#0
H_A#4
H_A#5
L4
A3#
A4#
YONAH D0#
D1# F24 H_D#1
H_D#2
H_D#[0..63]
H_D#[0..63] 6
M3 A5# D2# E26
H_A#6 K5 H22 H_D#3
H_A#7 A6# D3# H_D#4
M1 A7# D4# F23
H_A#8 N2 G25 H_D#5
H_A#9 A8# D5# H_D#6 H_A#[3..31]
J1 A9# D6# E25 H_A#[3..31] 6
H_A#10 N3 E23 H_D#7
H_A#11 A10# D7# H_D#8 H_REQ#[0..4]
P5 A11# D8# K24 H_REQ#[0..4] 6
H_A#12 P2 G24 H_D#9
H_A#13 A12# D9# H_D#10 H_RS#[0..2]
L1 A13# D10# J24 H_RS#[0..2] 6
D H_A#14 P4 J23 H_D#11 D
H_A#15 A14# D11# H_D#12
P1 A15# D12# H26
H_A#16 R1 F26 H_D#13
H_A#17 A16# D13# H_D#14
Y2 A17# D14# K22
H_A#18 U5 H25 H_D#15
H_A#19 A18# D15# H_D#16
R3 A19# D16# N22
H_A#20 W6 K25 H_D#17
H_A#21 A20# D17# H_D#18
U4 A21# D18# P26
H_A#22 Y5 R23 H_D#19
H_A#23 A22# D19# H_D#20
U2 A23# D20# L25
H_A#24 R4 L22 H_D#21
H_A#25 A24# D21# H_D#22
T5 A25# ADDR GROUP DATA GROUP D22# L23
H_A#26 T3 M23 H_D#23
H_A#27 A26# D23# H_D#24
W3 A27# D24# P25
H_A#28 W5 P22 H_D#25
H_A#29 A28# D25# H_D#26
Y4 A29# D26# P23
H_A#30 W2 T24 H_D#27
H_A#31 A30# D27# H_D#28
Y1 A31# D28# R24
L26 H_D#29
H_REQ#0 D29# H_D#30
K3 REQ0# D30# T25
H_REQ#1 H2 N24 H_D#31 +1.05VS
H_REQ#2 REQ1# D31# H_D#32
K2 REQ2# D32# AA23
H_REQ#3 J3 AB24 H_D#33
H_REQ#4 REQ3# D33# H_D#34
L5 REQ4# D34# V24
V26 H_D#35 XDP_TDI R59 2 1 56_0402_5%
D35# H_D#36
6 H_ADSTB#0 L2 ADSTB0# D36# W25
V4 U23 H_D#37
6 H_ADSTB#1 ADSTB1# D37#
U25 H_D#38
D38# H_D#39 XDP_TDO R525 2 56_0402_5%
D39# U22 1
C AB25 H_D#40 C
D40# H_D#41
D41# W22
Y23 H_D#42
D42# H_D#43 XDP_TMS R63 56_0402_5%
14 CLK_CPU_BCLK A22 BCLK0 D43# AA26 2 1
A21 HOST CLK Y26 H_D#44
14 CLK_CPU_BCLK# BCLK1 D44#
Y22 H_D#45
D45# H_D#46
D46# AC26
AA24 H_D#47 H_PROCHOT# R114 2 1 75_0402_5%
D47# H_D#48
6 H_ADS# H1 ADS# D48# AC22
6 H_BNR# E2 AC23 H_D#49
BNR# D49# H_D#50
6 H_BPRI# G5 BPRI# D50# AB22
F1 AA21 H_D#51 XDP_BPM#5 R46 2 1 56_0402_5%
6 H_BR0# BR0# D51#
6 H_DEFER# H5 AB21 H_D#52
DEFER# D52# H_D#53
6 H_DRDY# F21 DRDY# D53# AC25
G6 AD20 H_D#54
6 H_HIT# HIT# D54#
E4 CONTROL AE22 H_D#55 H_IERR# R113 2 1 56_0402_5%
6 H_HITM# HITM# D55#
H_IERR# D20 AF23 H_D#56
IERR# D56# H_D#57
6 H_LOCK# H4 LOCK# D57# AD24
6 H_RESET# H_RESET# B1 AE21 H_D#58
RESET# D58# H_D#59
D59# AD21
AE25 H_D#60
H_RS#0 D60# H_D#61 XDP_TRST# R57 56_0402_5%
F3 RS0# D61# AF25 2 1
H_RS#1 F4 AF22 H_D#62
H_RS#2 RS1# D62# H_D#63 XDP_TCK R37 56_0402_5%
G3 RS2# D63# AF26 2 1
6 H_TRDY# G2 TRDY# TEST1 R526 2 1 @ 1K_0402_5%
DINV0# J26 H_DINV#0 6
M26 TEST2 R527 2 1 51_0402_5%
DINV1# H_DINV#1 6
AD4 BPM0# DINV2# V23 H_DINV#2 6
B B
AD3 BPM1# DINV3# AC20 H_DINV#3 6
AD1 BPM2#
AC4 BPM3#
DSTBN0# H23 H_DSTBN#0 6
20 XDP_DBRESET# XDP_DBRESET# C20 M24
DBR# DSTBN1# H_DSTBN#1 6
6 H_DBSY# E1 DBSY# DSTBN2# W24 H_DSTBN#2 6
19 H_DPSLP# B5 DPSLP# DSTBN3# AD23 H_DSTBN#3 6
19,42 H_DPRSTP# E5 DPRSTP# DSTBP0# G22 H_DSTBP#0 6
6 H_DPW R# D24 DPWR# DSTBP1# N25 H_DSTBP#1 6
AC2 MISC Y25 +3VS
PRDY# DSTBP2# H_DSTBP#2 6
XDP_BPM#5 AC1 AE24 C485
PREQ# DSTBP3# H_DSTBP#3 6
H_PROCHOT# D21 0.1U_0402_16V4Z
PROCHOT#
1 2
H_PW RGOOD D6
19 H_PW RGOOD PWRGOOD
H_CPUSLP# D7
6 H_CPUSLP# SLP#
XDP_TCK AC5
XDP_TDI TCK
AA6 TDI A20M# A6 H_A20M# 19
XDP_TDO AB3 A5 1 U21
TDO FERR# H_FERR# 19
TEST1 C26 C4 C484 1 8
TEST1 IGNNE# H_IGNNE# 19 VDD SCLK EC_SMB_CK2 28
TEST2 D25 B3
TEST2 INIT# H_INIT# 19
XDP_TMS AB5 C6 2200P_0402_50V7K THERMDA 2 7
TMS LINT0 H_INTR 19 2 D+ SDATA EC_SMB_DA2 28
XDP_TRST# AB6 B4
TRST# LINT1 H_NMI 19
LEGACY CPU THERMDC 3 6
D- ALERT#
THERMAL
THERMDA A24 D5 4 5
THERMDC THERMDA DIODE STPCLK# H_STPCLK# 19 THERM# GND
A25 THERMDC SMI# A3 H_SMI# 19
6,19 H_THERMTRIP# C7 THERMTRIP# ADM1032ARMZ_MSOP8
A A
FOX_PZ47903-2741-42_YONAH
Layout Note: Security Classification Compal Secret Data Compal Electronics, Inc.
THERMDA & THERMDC Trace / Space = 10 / 10 mil Issued Date 2007/1/15 Deciphered Date 2007/12/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Merom (1/2)
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JDW50/JDYL70 M/B LA-3771P
Date: Monday, April 16, 2007 Sheet 4 of 44
5 4 3 2 1
5 4 3 2 1
+CPU_CORE
JP22C
100_0402_1% +CPU_CORE
+CPU_CORE 2 1 JP22B 3 x 330uF(9mOhm/3) AE18 K1
R20 VCC VSS
AE17 VCC VSS J2
42 VCCSENSE VCCSENSE AF7 AB26 1 1 1 AB15 M2
VSSSENSE AE7 VCCSENSE VSS VCC VSS
20mils 42 VSSSENSE VSSSENSE VSS AA25
+ C669 + C670 + C671
AA15 VCC VSS N1
2 1 R21 VSS AD25 @ AD15 VCC VSS T1
100_0402_1% AE26 AC15 R2
VSS 330U_D2E_2.5VM_R9 330U_D2E_2.5VM_R9 330U_D2E_2.5VM_R9 VCC VSS
+1.5VS B26 VCCA VSS AB23 AF15 VCC VSS V2
2 2 2
VSS AC24 AE15 VCC VSS W1
D 1 1 +1.05VS K6 VCCP VSS AF24 AB14 VCC VSS A26 D
C148 C153 J6 AE23 South Side Secondary AA13 D26
VCCP VSS VCC VSS