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INTEGRATED CIRCUITS
DATA SHEET
SAA7111A Enhanced Video Input Processor (EVIP)
Product specification Supersedes data of 1997 May 26 File under Integrated Circuits, IC22 1998 May 15
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
CONTENTS 1 2 3 4 5 6 7 8 8.1 8.2 8.2.1 8.2.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.13.1 9 9.1 9.2 10 11 12 13 14 14.1 14.2 15 16 16.1 17 17.1 17.2 FEATURES APPLICATIONS GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Analog input processing Analog control circuits Clamping Gain control Chrominance processing Luminance processing RGB matrix VBI-data bypass VPO-bus (digital outputs) Reference signals HREF, VREF and CREF Synchronization Clock generation circuit Power-on reset and CE input RTCO output The Line-21 text slicer Suggestions for I2C-bus interface of the display software reading line-21 data BOUNDARY-SCAN TEST Initialization of boundary-scan circuit Device identification codes GAIN CHARTS LIMITING VALUES CHARACTERISTICS TIMING DIAGRAMS CLOCK SYSTEM Clock generation circuit Power-on control OUTPUT FORMATS APPLICATION INFORMATION Layout hints I2C-BUS DESCRIPTION I2C-bus format I2C-bus detail 17.2.1 17.2.2 17.2.3 17.2.4 17.2.5 17.2.6 17.2.7 17.2.8 17.2.9 17.2.10 17.2.11 17.2.12 17.2.13 17.2.14 17.2.15 17.2.16 17.2.17 17.2.18 17.2.19 17.2.20 17.2.21 17.2.22 17.2.23 17.2.24 17.2.25 18 18.1 18.2 18.3 18.4 19 20 21 21.1 21.2 21.3 21.4 22 23 24
SAA7111A
Subaddress 00 Subaddress 02 Subaddress 03 Subaddress 04 Subaddress 05 Subaddress 06 Subaddress 07 Subaddress 08 Subaddress 09 Subaddress 0A Subaddress 0B Subaddress 0C Subaddress 0D Subaddress 0E Subaddress 10 Subaddress 11 Subaddress 12 Subaddress 13 Subaddress 15 Subaddress 16 Subaddress 17 Subaddress 1A (read-only register) Subaddress 1B (read-only register) Subaddress 1C (read-only register) Subaddress 1F (read-only register) FILTER CURVES Anti-alias filter curve TUF-block filter curve Luminance filter curves Chrominance filter curves I2C-BUS START SET-UP PACKAGE OUTLINES SOLDERING Introduction Reflow soldering Wave soldering Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS
1998 May 15
2
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
1 FEATURES
SAA7111A
· Four analog inputs, internal analog source selectors, e.g. 4 × CVBS or 2 × Y/C or (1 × Y/C and 2 × CVBS) · Two analog preprocessing channels · Fully programmable static gain for the main channels or automatic gain control for the selected CVBS or Y/C channel · Switchable white peak control · Two built-in analog anti-aliasing filters · Two 8-bit video CMOS analog-to-digital converters · On-chip clock generator · Line-locked system clock frequencies · Digital PLL for horizontal-sync processing and clock generation · Requires only one crystal (24.576 MHz) for all standards · Horizontal and vertical sync detection · Automatic detection of 50 and 60 Hz field frequency, and automatic switching between PAL and NTSC standards · Luminance and chrominance signal processing for PAL BGHI, PAL N, PAL M, NTSC M, NTSC N, NTSC 4.43, NTSC-Japan and SECAM · User programmable luminance peaking or aperture correction · Cross-colour reduction for NTSC by chrominance comb filtering · PAL delay line for correcting PAL phase errors · Real time status information output (RTCO) · Brightness Contrast Saturation (BCS) control on-chip · The YUV (CCIR-601) bus supports a data rate of: 864 × fH = 13.5 MHz for 625 line sources 858 × fH = 13.5 MHz for 525 line sources. · Data output streams for 16, 12 or 8-bit width with the following formats: YUV 4 : 1 : 1 (12-bit) YUV 4 : 2 : 2 (16-bit) YUV 4 : 2 : 2 (CCIR-656) (8-bit) RGB (5, 6, and 5) (16-bit) with dither RGB (8, 8, and 8) (24-bit) with special application. 2 APPLICATIONS · Desktop/Notebook (PCMCIA) video · Multimedia · Digital television · Image processing · Video phone · Intercast. · Odd/even field identification by a non interlace CVBS input signal · Fix level for RGB output format during horizontal blanking · 720 active samples per line on the YUV bus · One user programmable general purpose switch on an output pin · Built-in line-21 text slicer · A 27 MHz Vertical Blanking Interval (VBI) data bypass programmable by I2C-bus for INTERCAST applications · Power-on control · Two via I2C-bus switchable outputs for the digitized CVBS or Y/C input signals AD1 (7 to 0) and AD2 (7 to 0) · Chip enable function (reset for the clock generator and power save mode up from chip version 3) · Compatible with memory-based features (line-locked clock) · Boundary scan test circuit complies with the `IEEE Std. 1149.1 - 1990' (ID-Code = 0 F111 02 B) · I2C-bus controlled (full read-back ability by an external controller) · Low power (<0.5 W), low voltage (3.3 V), small package (LQFP64) · 5 V tolerant digital I/O ports.
1998 May 15
3
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
3 GENERAL DESCRIPTION
SAA7111A
The Enhanced Video Input Processor (EVIP) is a combination of a two-channel analog preprocessing circuit including source selection, anti-aliasing filter and ADC, an automatic clamp and gain control, a Clock Generation Circuit (CGC), a digital multi-standard decoder (PAL BGHI, PAL M, PAL N, NTSC M, NTSC-Japan NTSC N and SECAM), a brightness/contrast/saturation control circuit, a colour space matrix (see Fig.1) and a 27 MHz VBI-data bypass.
The pure 3.3 V CMOS circuit SAA7111A, analog front-end and digital video decoder, is a highly integrated circuit for desktop video applications. The decoder is based on the principle of line-locked clock decoding and is able to decode the colour of PAL, SECAM and NTSC signals into CCIR-601 compatible colour component values. The SAA7111A accepts as analog inputs CVBS or S-video (Y/C) from TV or VTR sources. The circuit is I2C-bus controlled. The SAA7111A then supports several text features as Line 21 data slicing and a high-speed VBI data bypass for Intercast.
4
QUICK REFERENCE DATA SYMBOL PARAMETER digital supply voltage analog supply voltage operating ambient temperature analog and digital power 3.0 3.1 0 - MIN. 3.3 3.3 25 0.5 TYP. 3.6 3.5 70 - MAX. V V °C W UNIT
VDDD VDDA Tamb PA+D 5
ORDERING INFORMATION TYPE NUMBER PACKAGE NAME LQFP64 QFP64 DESCRIPTION plastic low profile quad flat package; 64 leads; body 10 × 10 × 1.4 mm plastic quad flat package; 64 leads (lead length 1.6 mm); body 14 × 14 × 2.7 mm VERSION SOT314-2 SOT393-1
SAA7111AHZ SAA7111AH
1998 May 15
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Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
6 BLOCK DIAGRAM
SAA7111A
handbook, full pagewidth
VBI DATA BYPASS UPSAMPLING FILTER
BYPASS AOUT AI11 AI12 14 12 10 ANALOG PROCESSING AND ANALOG-TODIGITAL CONVERSION AD2 n.c. VSSS 64 13 CON Y I2C-BUS CONTROL I2C-BUS INTERFACE AD1 CHROMINANCE CIRCUIT AND BRIGHTNESS C/CVBS CONTRAST SATURATION CONTROL YUV-to-RGB CONVERSION AND OUTPUT FORMATTER 34 to 39 42 to 51 VPO (0 : 15)
AI21 AI22
8 6
UV Y
52 31
FEI HREF
53 61 62 63
ANALOG PROCESSING CONTROL n.c. 10
GPSW IICSA SDA SCL
LUMINANCE CIRCUIT Y/CVBS
Y V SSA1-2 V DDA1-2 9,5 11,7
SAA7111A
CLOCKS
TDI TCK TMS TRST TDO
3 59 4 58 2
TEST CONTROL BLOCK FOR BOUNDARY SCAN TEST AND SCAN TEST
54 CLOCK GENERATION CIRCUIT POWER-ON CONTROL 55 21 22 20 23
XTAL XTALI LLC2 CREF LLC RES
SYNCHRONIZATION CIRCUIT LFCO
57,41,33,25,18 V DDD1-5
56,40,32,26,19
30 VS
27
17
29
28
60 V
15 V
16
24
MGG061
VSSD1-5
HS VREF RTS0 RTS1 RTCO
DDA0
SSA0
CE
Fig.1 Block diagram.
1998 May 15
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Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
7 PINNING PIN SYMBOL (L)QFP64 n.c. TDO TDI TMS VSSA2 AI22 VDDA2 AI21 VSSA1 AI12 VDDA1 AI11 VSSS AOUT VDDA0 VSSA0 VREF VDDD5 VSSD5 LLC LLC2 CREF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 - O I I P I P I P I P I P O P P O P P O O O Do not connect. Test data output for boundary scan test; note 1. Test data input for boundary scan test; note 1. Test mode select input for boundary scan test or scan test; note 1. Ground for analog supply voltage channel 2. Analog input 22. Positive supply voltage for analog channel 2 (+3.3 V). Analog input 21. Ground for analog supply voltage channel 1. Analog input 12. Positive supply voltage for analog channel 1 (+3.3 V). Analog input 11. Substrate ground connection. Analog test output; for testing the analog input channels. I/O/P DESCRIPTION
SAA7111A
Positive supply voltage for internal Clock Generator Circuit (CGC) (+3.3 V). Ground for internal CGC. Vertical reference output signal (I2C-bit COMPO = 0) or inverse composite blanking signal (I2C-bit COMPO = 1) (enabled via I2C-bus bit OEHV). Digital supply voltage 5 (+3.3 V). Ground for digital supply voltage 5. Line-locked system clock output (27 MHz). Line-locked clock 1/2 output (13.5 MHz). Clock reference output: this is a clock qualifier signal distributed by the internal CGC for a data rate of LLC2. Using CREF all interfaces on the VPO bus are able to generate a bus timing with identical phase. If CCIR 656 format is selected (OFTS0 = 1 and OFTS1 = 1) an inverse composite blanking signal (pixel qualifier) is provided on this pin. Reset output (active LOW); sets the device into a defined state. All data outputs are in high impedance state. The I2C-bus is reset (waiting for start condition). Chip enable; connection to ground forces a reset, up from version 3 power save function additionally available. Digital supply voltage input 4 (+3.3 V). Ground for digital supply voltage input 4. Horizontal sync output signal (programmable); the positions of the positive and negative slopes are programmable in 8 LLC increments over a complete line (equals 64 µs) via I2C-bus bytes HSB and HSS. Fine position adjustment in 2 LLC increments can be performed via I2C-bus bits HDEL1 and HDEL0. Two functions output; controlled by I2C-bus bit RTSE1. RTSE1 = 0: PAL line identifier (LOW = PAL line); indicates the inverted and non-inverted R - Y component for PAL signals. RTSE1 = 1: H-PLL locked indicator; a high state indicates that the internal horizontal PLL has locked. 6
RES CE VDDD4 VSSD4 HS
23 24 25 26 27
O I P P O
RTS1
28
O
1998 May 15
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
PIN SYMBOL (L)QFP64 RTS0 29 O Two functions output; controlled by I2C-bus bit RTSE0. RTSE0 = 0: odd/even field identification (HIGH = odd field). RTSE0 = 1: vertical locked indicator; a HIGH state indicates that the internal Vertical Noise Limiter (VNL) has locked. Vertical sync signal (enabled via I2C-bus bit OEHV); this signal indicates the vertical sync with respect to the YUV output. The HIGH period of this signal is approximately six lines if the VNL function is active. The positive slope contains the phase information for a deflection controller. Horizontal reference output signal (enabled via I2C-bus bit OEHV); this signal is used to indicate data on the digital YUV bus. The positive slope marks the beginning of a new active line. The HIGH period of HREF is 720 Y samples long. HREF can be used to synchronize data multiplexer/demultiplexer. HREF is also present during the vertical blanking interval. Ground for digital supply voltage input 3. Digital supply voltage 3 (+3.3 V). Digital VPO-bus (Video Port Out) signal; higher bits of the 16-bit VPO-bus or the 16-bit RGB-bus output signal. The output data rate, the format and multiplexing scheme of the VPO-bus are controlled via I2C-bus bits OFTS0 and OFTS1. If I2C-bus bit VIPB = 1 the six MSBs of the digitized input signal are connected to these outputs, configured by the I2C-bus `MODE' bits (see Figs 33 to 40): LUMA VPO15 to VPO8, CHROMA VPO7 to VPO0. Ground for digital supply voltage input 2. Digital supply voltage 2 (+3.3 V). Digital VPO-bus output signal; lower bits of the 16-bit YUV-bus or the 16-bit RGB-bus output signal. The output data rate, the format and multiplexing schema of the VPO-bus are controlled via I2C-bus bits OFTS0 and OFTS1. If I2C-bus bit VIPB = 1 the digitized input signal are connected to these outputs, configured by the I2C-bus `MODE' bits (see Figs 33 to 40): LUMA VPO15 to VPO8, CHROMA VPO7 to VPO0. Fast enable input signal (active LOW); this signal is used to control fast switching on the digital YUV-bus. A HIGH at this input forces the IC to set its Y and UV outputs to the high impedance state. General purpose switch output; the state of this signal is set via I2C-bus control and the levels are TTL compatible. Second terminal of crystal oscillator; not connected if external clock signal is used. Input terminal for 24.576 MHz crystal oscillator or connection of external oscillator with CMOS compatible square wave clock signal. Ground for digital supply voltage input 1. Digital supply voltage input 1 (+3.3 V). Test reset input not (active LOW), for boundary scan test; notes 1, 2 and 3. Test clock for boundary scan test; note 1. Real time control output: contains information about actual system clock frequency, subcarrier frequency and phase and PAL sequence. I/O/P DESCRIPTION
VS
30
O
HREF
31
O
VSSD3 VDDD3 VPO (15 to 10)
32 33 34 to 39
P P O
VSSD2 VDDD2 VPO (9 to 0)
40 41 42 to 51
P P O
FEI
52
I
GPSW XTAL XTALI VSSD1 VDDD1 TRST TCK RTCO
53 54 55 56 57 58 59 60
O O I P P I I O
1998 May 15
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Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
PIN SYMBOL (L)QFP64 IICSA 61 I I2C-bus slave address select; 0 = 48H for write, 49H for read 1 = 4AH for write, 4BH for read. Serial data input/output (I2C-bus). Serial clock input/output (I2C-bus). Not connect. I/O/P DESCRIPTION
SDA SCL n.c. Notes
62 63 64
I/O I/O -
1. In accordance with the `IEEE1149.1' standard the pads TCK, TDI, TMS and TRST are input pads with an internal pull-up transistor and TDO a 3-state output pad. 2. This pin provides easy initialization of BST circuit. TRST can be used to force the TAP (Test Access Port) controller to the Test-Logic-Reset state (normal operation) at once. 3. For board design without boundary scan implementation (pin compatibility with the SAA7110) connect the TRST pin to ground.
1998 May 15
8
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
VDDD1
VSSD1
RTCO
XTALI
VPO0
VPO1 50
n.c.
64
63
62
61
60
59
58
57
56
55
54
53
52
51
n.c. TDO TDI TMS VSSA2 AI22 VDDA2 AI21 VSSA1
1 2 3 4 5 6 7 8
49 48 VPO3 47 VPO4 46 VPO5 45 VPO6 44 VPO7 43 VPO8 42 VPO9 41 VDDD2 40 VSSD2 39 VPO10 38 VPO11 37 VPO12 36 VPO13 35 VPO14 34 VPO15 33 VDDD3 VSSD3 32
SAA7111A
9
AI12 10 VDDA1 11 AI11 12 VSSS 13 AOUT 14 VDDA0 15 VSSA0 16 VREF 17 VDDD5 18 VSSD5 19 LLC 20 LLC2 21 CREF 22 RES 23 CE 24 VDDD4 25 VSSD4 26 HS 27 RTS1 28 RTS0 29 VS 30 HREF 31
VPO2
IICSA
TRST
XTAL
handbook, full pagewidth
GPSW
SDA
TCK
SCL
FEI
MGG060
Fig.2 Pin configuration (LQFP64/QFP64).
1998 May 15
9
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
8 8.1 FUNCTIONAL DESCRIPTION Analog input processing
SAA7111A
The SAA7111A offers four analog signal inputs, two analog main channels with source switch, clamp circuit, analog amplifier, anti-alias filter and video CMOS ADC (see Fig.5). 8.2 Analog control circuits
The AGC (automatic gain control for luminance) is used to amplify a CVBS or Y signal to the required signal amplitude, matched to the ADCs input voltage range. The AGC active time is the sync bottom of the video signal.
handbook, halfpage
The anti-alias filters are adapted to the line-locked clock frequency via a filter control circuit. During the vertical blanking time, gain and clamping control are frozen. 8.2.1 CLAMPING
analog input level maximum
controlled ADC input level
+4.5 dB 0 dB (1 V(p-p) 27/47 ) -7.5 dB
range tbf
0 dB
The clamp control circuit controls the correct clamping of the analog input signals. The coupling capacitor is also used to store and filter the clamping voltage. An internal digital clamp comparator generates the information with respect to clamp-up or clamp-down. The clamping levels for the two ADC channels are fixed for luminance (60) and chrominance (128). Clamping time in normal use is set with the HCL pulse at the back porch of the video signal.
minimum
MGG063
Fig.4 Automatic gain range.
8.3
Chrominance processing
handbook, halfpage
TV line analog line blanking
255
GAIN 60 1
CLAMP
The 8-bit chrominance signal is fed to the multiplication inputs of a quadrature demodulator, where two subcarrier signals from the local oscillator DTO1 are applied (0 and 90° phase relationship to the demodulator axis). The frequency is dependent on the present colour standard. The output signals of the multipliers are low-pass filtered (four programmable characteristics) to achieve the desired bandwidth for the colour difference signals (PAL and NTSC) or the 0 and 90° FM-signals (SECAM). The colour difference signals are fed to the Brightness/Contrast/Saturation block (BCS), which includes the following five functions: · AGC (Automatic Gain Control for chrominance PAL and NTSC) · Chrominance amplitude matching (different gain factors for R - Y and B - Y to achieve CCIR-601 levels Cr and Cb for all standards) · Chrominance saturation control · Luminance contrast and brightness · Limiting YUV to the values 1 (min.) and 254 (max.) to fulfil CCIR-601 requirements.
HCL HSY
MGL065
Fig.3
Analog line with clamp (HCL) and gain range (HSY).
8.2.2
GAIN CONTROL
Signal (white) peak control limits the gain at signal overshoots. The flow charts (see Figs 13 and 14) show more details of the AGC. The influence of supply voltage variation within the specified range is automatically eliminated by clamp and automatic gain control. The gain control circuit receives (via the I2C-bus) the static gain levels for the two analog amplifiers or controls one of these amplifiers automatically via a built-in automatic gain control (AGC) as part of the Analog Input Control (AICO). 1998 May 15 10
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
The SECAM-processing contains the following blocks: · Baseband `bell' filters to reconstruct the amplitude and phase equalized 0 and 90° FM-signals · Phase demodulator and differentiator (FM-demodulation) · De-emphasis filter to compensate the pre-emphasised input signal, including frequency offset compensation (DB or DR white carrier values are subtracted from the signal, controlled by the SECAM-switch signal). The burst processing block provides the feedback loop of the chroma PLL and contains; · Burst gate accumulator · Colour identification and killer · Comparison nominal/actual burst amplitude (PAL/NTSC standards only) · Loop filter chrominance gain control (PAL/NTSC standards only) · Loop filter chrominance PLL (only active for PAL/NTSC standards) · PAL/SECAM sequence detection, H/2-switch generation · Increment generation for DTO1 with divider to generate stable subcarrier for non-standard signals. The chrominance comb filter block eliminates crosstalk between the chrominance channels in accordance with the PAL standard requirements. For NTSC colour standards the chrominance comb filter can be used to eliminate crosstalk from luminance to chrominance (cross-colour) for vertical structures. The comb filter can be switched off if desired. The embedded line delay is also used for SECAM recombination (cross-over switches). The resulting signals are fed to the variable Y-delay compensation, RGB matrix, dithering circuit and output interface, which contains the VPO output formatter and the output control logic (see Fig.6). 8.4 Luminance processing
SAA7111A
The high frequency components of the luminance signal can be peaked (control for sharpness improvement via I2C-bus) in two band-pass filters with selectable transfer characteristic. This signal is then added to the original (unpeaked) signal. A switchable amplifier achieves common DC amplification, because the DC gains are different in both chrominance trap modes. The improved luminance signal is fed to the BCS control located in the chrominance processing block (see Fig.7). 8.5 RGB matrix
Y, Cr and Cb data are converted after interpolation into RGB data in accordance with CCIR-601 recommendations. The realized matrix equations consider the digital quantization: R = Y + 1.371 Cr G = Y - 0.336 Cb - 0.698 Cr B = Y + 1.732 Cb. After dithering (noise shaping) the RGB data is fed to the output interface within the VPO-bus output formatter. 8.6 VBI-data bypass
For a 27 MHz VBI-data bypass the offset binary CVBS signal is upsampled behind the ADCs. Upsampling of the CVBS signal from 13.5 to 27 MHz is possible, because the ADCs deliver high performance at 13.5 MHz sample clock. Suppressing of the back folded CVBS frequency components after upsampling is achieved by an interpolation filter (see Fig.42). The TUF block on the digital top level performs the upsampling and interpolation for the bypassed CVBS signal (see Fig.6). For bypass details see Figs 8 to 10. 8.7 VPO-bus (digital outputs)
The 8-bit luminance signal, a digital CVBS format or a luminance format (S-VHS, HI8), is fed through a switchable prefilter. High frequency components are emphasized to compensate for loss. The following chrominance trap filter (f0 = 4.43 or 3.58 MHz centre frequency selectable) eliminates most of the colour carrier signal, therefore, it must be bypassed for S-video (S-VHS and HI8) signals.
The 16-bit VPO-bus transfers digital data from the output interfaces to a feature box or a field memory, a digital colour space converter (SAA7192 DCSC), a video enhancement and digital-to-analog processor (SAA7165 VEDA2) or a colour graphics board (Targa-format) as a graphical user interface.
1998 May 15
11
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
The output data formats are controlled via the I2C-bus bits OFTS0, OFTS1 and RGB888. Timing for the data stream formats, YUV (4 : 1 : 1) (12-bit), YUV (4 : 2 : 2) (16-bit), RGB (5, 6 and 5) (16-bit) and RGB (8, 8 and 8) (24-bit) with an LLC2 data rate, is achieved by marking each second positive rising edge of the clock LLC in conjunction with CREF (clock reference) (except RGB (8, 8 and 8), see special application in Fig.32). The higher output signals VPO15 to VPO8 in the YUV format perform the digital luminance signal. The lower output signals VPO7 to VPO0 in the YUV format are the bits of the multiplexed colour difference signals (B - Y) and (R - Y). The arrangement of the RGB (5, 6 and 5) and RGB (8, 8 and 8) data stream bits on the VPO-bus is given in Table 6. The data stream format YUV 4 : 2 : 2 (the 8 higher output signals VPO15 to VPO8) in LLC data rate fulfils the CCIR-656 standard with its own timing reference code at the start and end of each video data block. A pixel in the format tables is the time required to transfer a full set of samples. If 16-bit 4 : 2 : 2 format is selected two luminance samples are transmitted in comparison to one (B - Y) and one (R - Y) sample within a pixel. The time frames are controlled by the HREF signal. Fast enable is achieved by setting input FEI to LOW. The signal is used to control fast switching on the digital VPO-bus. HIGH on this pin forces the VPO outputs to a high-impedance state (see Figs 18 and 19). The I2C-bus bit OEYC has to be set HIGH to use this function. The digitized PAL, SECAM or NTSC signals AD1 (7 to 0) and AD2 (7 to 0) are connected directly to the VPO-bus via I2C-bus bit VIPB = 1 and MODE = 4, 5, 6 or 7. AD1 (7 to 0) VPO (15 to 8) and AD2 (7 to 0) VPO (7 to 0). The selection of the analog input channels is controlled via I2C-bus subaddress 02 MODE select. The upsampled 8-bit offset binary CVBS signal (VBI-data bypass) is multiplexed under control of the I2C-bus to the digital VPO-bus (see Fig.8). 8.8 Reference signals HREF, VREF and CREF
SAA7111A
· VREF: The VREF output delivers a vertical reference signal or an inverse composite blank signal controlled via the I2C-bus [subaddress 11, inverse composite blank (COMPO)]. Furthermore four different modes of vertical reference signals are selectable via the I2C-bus [subaddress 13, vertical reference output control (VCTR1 and VCTR0)]. The description of VREF timing and position is illustrated in Figs 15, 16, 24 and 25. · CREF: The CREF output delivers a clock/pixel qualifier signal for external interfaces to synchronize to the VPO-bus data stream. Four different modes for the clock qualifier signal are selectable via the I2C-bus [subaddress 13, clock reference output control (CCTR1 and CCTR0)]. The description of CREF timing and position is illustrated in Figs 16, 18, 20 and 21. 8.9 Synchronization
The prefiltered luminance signal is fed to the synchronization stage. Its bandwidth is reduced to 1 MHz in a low-pass filter. The sync pulses are sliced and fed to the phase detectors where they are compared with the sub-divided clock frequency. The resulting output signal is applied to the loop filter to accumulate all phase deviations. Internal signals (e. g. HCL and HSY) are generated in accordance with analog front-end requirements. The output signals HS, VS, and PLIN are locked to the timing reference, guaranteed between the input signal and the HREF signal, as further improvements to the circuit may change the total processing delay. It is therefore not recommended to use them for applications which require absolute timing accuracy on the input signals. The loop filter signal drives an oscillator to generate the line frequency control signal LFCO (see Fig.7). 8.10 Clock generation circuit
· HREF: The positive slope of the HREF output signal indicates the beginning of a new active video line. The high period is 720 luminance samples long and is also present during the vertical blanking. The description of timing and position from HREF is illustrated in Figs 15, 16, 21 and 23.
The internal CGC generates all clock signals required for the video input processor. The internal signal LFCO is a digital-to-analog converted signal provided by the horizontal PLL. It is the multiple of the line frequency 429 6.75MHz = --------- × f H 432 Internally the LFCO signal is multiplied by a factor of 2 or 4 in the PLL circuit (including phase detector, loop filtering, VCO and frequency divider) to obtain the LLC and LLC2 output clock signals. The rectangular output clocks have a 50% duty factor (see Fig.26).
1998 May 15
12
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
8.11 Power-on reset and CE input 8.13.1
SAA7111A
SUGGESTIONS FOR I2C-BUS INTERFACE OF THE DISPLAY SOFTWARE READING LINE-21 DATA
A missing clock, insufficient digital or analog VDDA0 supply voltages (below 2.7 V) will initiate the reset sequence; all outputs are forced to 3-state. The indicator output RES is LOW for approximately 128LLC after the internal reset and can be applied to reset other circuits of the digital TV system. It is possible to force a reset by pulling the chip enable (CE) to ground. After the rising edge of CE and sufficient power supply voltage, the outputs LLC, LLC2, CREF, RTCO, RTS0, RTS1, GPSW and SDA return from 3-state to active, while HREF, VREF, HS and VS remain in 3-state and have to be activated via I2C-bus programming (see Table 5). 8.12 RTCO output
There are two methods by which the software can acquire the data: 1. Synchronous reading once per frame (or once per field); It can use either the rising edge (Line-21 Field 1) or both edges (Line-21 Field 1 or 2) of the ODD signal (pin RTSO) to initiate an I2C-bus read transfer of the three registers 1A, 1B and 1C. 2. Asynchronous reading; It can poll either the F1RDY bit (Line-21 Field 1) or both F1RDY/F2RDY bits (Line-21 Field 1 or 2). After valid data has been read the corresponding F*RDY bit is set to LOW until new data has arrived. The polling frequency has to be slightly higher than the frame or field frequency, respectively.
The real time control and status output signal contains serial information about the actual system clock (increment of the HPLL), subcarrier frequency [increment and phase (via reset) of the FSC-PLL] and PAL sequence bit. The signal can be used for various applications in external circuits, e.g. in a digital encoder to achieve clean encoding (see Fig.20). 8.13 The Line-21 text slicer
The text slicer block detects and acquires Line-21 Closed Captioning data from a 525-line CVBS signal. Extended data services on Line-21 Field 2 are also supported. If valid data is detected the two data bytes are stored in two I2C-bus registers. A parity check is also performed and the result is stored in the MSB of the corresponding byte. A third I2C-bus register is provided for data valid and data ready flags. The two bits F1VAL and F2VAL indicate that the input signal carries valid Closed Captioning data in the corresponding fields. The data ready bits F1RDY and F2RDY have to be evaluated if asynchronous I2C-bus reading is used.
1998 May 15
13
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n.c. VSSA1 VSSA2 AI22 AI21 VDDA1 VDDA2 AI12 AI11 64 9 5 AOSL (1 : 0) 6 8 11 7 10 12 SOURCE SWITCH FUSE (1 : 0) SOURCE SWITCH CLAMP CIRCUIT ANALOG AMPLIFIER DAC9 ANTI-ALIAS FILTER BYPASS SWITCH ADC2 TEST SELECTOR AND BUFFER 14 AOUT CLAMP CIRCUIT ANALOG AMPLIFIER DAC9 ANTI-ALIAS FILTER BYPASS SWITCH ADC1
handbook, full pagewidth
Philips Semiconductors
Enhanced Video Input Processor (EVIP)
14
MODE CONTROL CLAMP CONTROL GAIN CONTROL ANTI-ALIAS CONTROL MODE 0 MODE 1 MODE 2 HCL GLIMB HSY GLIMT WIPA SLTCA
FUSE (1 : 0)
VERTICAL BLANKING CONTROL
ANALOG CONTROL
HOLDG GAFIX WPOFF GUDL0-GUDL2 GAI20-GAI28 GAI10-GAI18 HLNRS UPTCV
VBSL
VBLNK SVREF
8
8
VSSS
13
CROSS
MULTIPLEXER
Product specification
SAA7111A
MGC655
LUM
CHR
AD2BYP AD1BYP
Fig.5 Analog input processing.
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gewidth
1998 May 15
LUM CHR
n.c. 1 TRST TCK TDI TMS TDO 58 59 3 4 2 TEST CONTROL BLOCK QUADRATURE DEMODULATOR
Philips Semiconductors
Enhanced Video Input Processor (EVIP)
AD2BYP
AD1BYP
SECAM PROCESSING sequential UV signals LOW-PASS CHBW0 CHBW1
PHASE DEMODULATOR
VDDD1-5
57,41,33, 25,18 POWER-ON CONTROL
SUBCARRIER GENERATION
LEVEL ADJUSTMENT, BRIGHTNESS, CONTRAST, AND SATURATION CONTROL
52
FEI
Y
HUEC
SUBCARRIER INCREMENT GENERATION AND DIVIDER
RGB MATRIX interpolation dithering
RGB
AMPLITUDE DETECTOR
OUTPUT FORMATTER AND INTERFACE
42 to 51
VPO (9 : 0) VPO (15 : 10) HREF
34 to 39
RES
23
BURST GATE ACCUMULATOR LOOP FILTER
GAIN CONTROL AND Y-DELAY COMPENSATION
DIT UV
CBR 31
COMB FILTERS SECAM RECOMBINATION GPSW OFTS0 RTSE1 OFTS1 RGB888 RTSE0 VIPB OEYC VLOF OEHV COLO FECO COMPO VRLN VSTA (8 : 0) VSTO (8 : 0)
15
CE CLOCKS
CSTD 1 CSTD 0 INCS
FCTC
CODE
BRIG CONT SATN
DCCF
V
SSD1-5
56,40,32,26,19 VBI DATA BYPASS TUF
fH/2 switch signal
60
MGG062
RTCO
LUM
Y
Product specification
SAA7111A
Fig.6 Chrominance circuit.
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2
Philips Semiconductors
Enhanced Video Input Processor (EVIP)
LUM
Y
LUMINANCE CIRCUIT
PREFILTER CHROMINANCE TRAP VARIABLE BAND-PASS FILTER WEIGHTING AND ADDING STAGE
PREF
BYPS VBLB
BPSS0 BPSS1 PREF
PREFILTER SYNC
MATCHING AMPLIFIER
APER0 APER1 VBLB
CLOCK CIRCUIT
CLOCKS
VBLB LINE-LOCKED CLOCK GENERATOR PHASE DETECTOR COARSE DAC6 HPLL VTRC EXFIL
LINE 21 TEXT SLICER
SYNC SLICER
PHASE DETECTOR FINE
22 20 21
CREF LLC LLC2
BYTE1 BYTE2 STATUS
SYNCHRONIZATION CIRCUIT
VNOI0 VNOI1 VTRC
I C BUS CONTROL
FIDT
AUFD HSB HSS FSEL VTRC
CLOCK GENERATION CIRCUIT
15 16 24
VDDA0 VSSA0 CE
HLCK STTC
VTRC
INCS DISCRETE TIME OSCILLATOR 2 CRYSTAL CLOCK GENERATOR 55 54 XTALI XTAL
GPSW
53
I C-BUS INTERFACE 61 63 62
2
VERTICAL PROCESSOR 30 29 17
COUNTER
LOOP FILTER 2 28
27 HS
MGC654
IICSA SCL SDA
VS RTS0 VREF
RTS1
handbook, full pagewidth
Product specification
SAA7111A
Fig.7 Luminance and sync processing.
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
handbook, full pagewidth
TBP7 to 0 (CVBS)
0 MUX CVBS UP 1 SWHI
AD1BYP
0 MUX BYP UP 1 REGISTER VPO15 to 8
Y or YUV
(LUMA see Fig. 37)
BCHI1 VBP0 VBP4 BCHI1 to 0 I2C-bus 0 0 1 1
BCHI0 0 1 0 1
SWHI 1 0 VBP0 VBP4 VIPB I2C-bus
0 MUX CVBS UP 1 SWLO
AD2BYP
0 MUX BYP UP 1 REGISTER VPO7 to 0
UV or YUV
(CHROMA see Fig. 37)
BCLO1 VBP0 VBP4 BCLO1 to 0 I2C-bus 0 0 1 1
BCLO0 0 1 0 1
SWLO 1 0 VBP0 VBP4
REG V_GATE (programmable) EN
4 × REG VBP4
HREFINT
CLOCK 0
CLOCK 0 VBP0
MGG064
HREFINT = internal horizontal reference. TBP = upsampled CVBS input data (27 MHz). AD1BYP/AD2BYP = digitized CVBS input data and Y/C input data (13.5 MHz). VBP0 = programmable vertical reference signal. VBP4 = delayed programmable vertical reference signal (4LLC clocks delay).
Fig.8 Multiplexing of the CVBS signal to the VPO-bus.
1998 May 15
17
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
handbook, full pagewidth
REG EN V V C C T T R R 1 0 0 0 REG 1 1 0 1 0 1
VREF CCIR 656
VREFOUT
HREFINT VBP0 VBP4
CLOCK 0
VREFINT VREF CCIR 656 VBP0 VBP4 0
REG HREF
VREFINT EN HREFINT CLOCK 0
CLK0 REG
VCTR1 to 0 1
MUX
VREF
CLOCK 0 COMPO VREF_CCIR 656 = vertical reference signal referring to the field interval definitions of CCIR656. HREFINT = internal horizontal reference signal. VREFINT = internal vertical reference signal. VBP0 = programmable vertical reference signal. VBP4 = delayed programmable vertical reference signal (4LLC clocks delay).
MGG065
Fig.9 VREF output signal generation.
handbook, full pagewidth
CREFINT
C C C C T T R R 1 0 0 0 1 1 0 1 0 1
CREFOUT REG CREFINT 0 if VREF = 0 1 if VREF = 0 1 (always HIGH) CLOCK 0
MGG066
selected VREF CCTR1 to 0
CREF
CREFINT = internal clock qualifier signal.
Fig.10 CREF output signal generation.
1998 May 15
18
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
9 BOUNDARY-SCAN TEST 9.2 Device identification codes
SAA7111A
The SAA7111A has built in logic and 5 dedicated pins to support boundary-scan testing which allows board testing without special hardware (nails). The SAA7111A follows the `IEEE Std. 1149.1 - Standard Test Access Port and Boundary-Scan Architecture' set by the Joint Test Action Group (JTAG) chaired by Philips. The 5 special pins are Test Mode Select (TMS), Test Clock (TCK), Test Reset (TRST), Test Data Input (TDI) and Test Data Output (TDO). The BST functions BYPASS, EXTEST, INTEST, SAMPLE, CLAMP and IDCODE are all supported (see Table 1). Details about the JTAG BST-TEST can be found in the specification "EEE Std. 1149.1". A file containing the detailed Boundary-Scan Description Language (BSDL) description of the SAA7111A is available on request. 9.1 Initialization of boundary-scan circuit
A Device Identification Register (DIR) is specified in `IEEE Std. 1149.1-1990 - IEEE Standard Test Access Port and Boundary-Scan Architecture' (IEEE Std. 1149.1b-1994). It is a 32-bit register which contains fields for the specification of the IC manufacturer, the IC part number and the IC version number. Its biggest advantage is the possibility to check for the correct ICs mounted after production and determination of the version number of ICs during field service. When the IDCODE instruction is loaded into the BST instruction register, the identification register will be connected between TDI and TDO of the IC. The identification register will load a component specific code during the CAPTURE_DATA_REGISTER state of the TAP controller and this code can subsequently be shifted out. At board level this code can be used to verify component manufacturer, type and version number. The device identification register contains 32-bits, numbered 31 to 0, where bit 31 is the Most Significant Bit (MSB) (nearest to TDI) and bit 0 is the Least Significant Bit (LSB) (nearest to TDO); see Fig.11.
The Test Access Port (TAP) controller of an IC should be in the reset state (TEST_LOGIC_RESET) when the IC is in functional mode. This reset state also forces the instruction register into a functional instruction such as IDCODE or BYPASS. To solve the power-up reset, the standard specifies that the TAP controller will be forced asynchronously to the TEST_LOGIC_RESET state by setting the TRST pin LOW. Table 1 BST instructions supported by the SAA7111A
INSTRUCTION BYPASS EXTEST SAMPLE
DESCRIPTION This mandatory instruction provides a minimum length serial path (1 bit) between TDI and TDO when no test operation of the component is required. This mandatory instruction allows testing of off-chip circuitry and board level interconnections. This mandatory instruction can be used to take a sample of the inputs during normal operation of the component. It can also be used to preload data values into the latched outputs of the boundary-scan register. This optional instruction is useful for testing when not all ICs have BST. This instruction addresses the bypass register while the boundary-scan register is in external test mode. This optional instruction will provide information on the components manufacturer, part number and version number. This optional instruction allows testing of the internal logic (no support for customers available). This private instruction allows testing by the manufacturer (no support for customers available).
CLAMP IDCODE INTEST USER1
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19
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
handbook, full pagewidth
MSB 31 TDI 28 27 1111000100010001 12 11 00000010101 1
LSB 0 1 TDO
0010
4-bit version code
16-bit part number
11-bit manufacturer indentification
MGL111
Fig.11 32 bits of identification code.
1998 May 15
20
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
10 GAIN CHARTS
SAA7111A
handbook, halfpage
MGC648
dB 5.5
factor dB = 20 x log 10 gain =
(
768 - i
3.5
bit [8] = 1 i > 256 bit [8] = 0 i < 256
1.5
-0.5 -2.5 -4.5 0 256 gain value (i) 512
factor dB = 20 x log 10 gain =
Fig.12 Amplifier curve.
handbook, full pagewidth
ANALOG INPUT ADC
NO BLANKING ACTIVE
1
VBLK
0
<- CLAMP
GAIN ->
1
HCL
0
1
HSY
1
CLL
0
0
SBOT
1
+ CLAMP
- CLAMP
NO CLAMP
+ GAIN
- GAIN
WIPE = white peak level (254); SBOT = sync bottom level (1); CLL = clamp level [60 Y (128 C)]; HSY = horizontal sync pulse; HCL = horizontal clamp pulse.
Fig.13 Clamp and gain flow.
1998 May 15
21
(
(
(
257 + i 512
7.5
512
0
1
WIPE
0
fast - GAIN
slow + GAIN
MGC647
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
handbook, full pagewidth
ANALOG INPUT AMPLIFIER ANTI-ALIAS FILTER ADC 8 LUMA/CHROMA DECODER gain DAC 9
NO ACTION
1
VBLK 1
0 0
HOLDG
1
X 1
0 0
HSY
0 0 1
>254
1 1 0 1 0
<4
<1
>254
X=0 1 >248 0
X=1
+1/F STOP
+1/L
-1/LLC2
+1/LLC2
-1/LLC2
+/- 0
GAIN ACCUMULATOR (18 BITS) ACTUAL GAIN VALUE 9-BIT (AGV) [-6/+6 dB] 1 0
X 1
HSY 1
0 0
Y
AGV
UPDATE GAIN VALUE 9-BIT
FGV
MGC652
X = system variable; Y = IAGV - FGVI > GUDL; VBLK = vertical blanking pulse; HSY = horizontal sync pulse; AGV = actual gain value; FGV = frozen gain value.
Fig.14 Gain flow chart.
1998 May 15
22
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
11 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134); all ground pins connected together and all supply pins connected together. SYMBOL VDDD VDDA Vi(A) Vo(A) Vi(D) Vo(D) VSS Tstg Tamb Tamb(bias) Vesd Note 1. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k resistor. 12 CHARACTERISTICS VDDD = 3.0 to 3.6 V; VDDA = 3.1 to 3.5 V; Tamb = 25 °C; unless otherwise specified. SYMBOL Supplies VDDD IDDD PD VDDA IDDA PA PA+D Ppd Analog part Iclamp Vi(p-p) clamping current input voltage (peak-to-peak value) VI = 0.9 V DC - ±3.5 0.7 - 1.2 µA V for normal video levels 0.3 [1 V (p-p)]; -3 dB termination 27/47 and AC coupling required; coupling capacitor = 22 nF clamping current off 200 - 23 digital supply voltage digital supply current digital power analog supply voltage analog supply current analog power analog and digital power analog and digital power in CE connected to ground power-down mode (since version 3) AOSL = [1:0] = 00b; AOUT not connected 3.0 - - 3.1 - - - - 3.3 63 0.21 3.3 52 0.17 0.38 0.02 3.6 70 - 3.5 - - - - V mA W V mA W W W PARAMETER CONDITIONS MIN. TYP. MAX. UNIT PARAMETER digital supply voltage analog supply voltage input voltage at analog inputs output voltage at analog output input voltage at digital inputs and outputs output voltage at digital outputs voltage difference between VSSAall and VSSall storage temperature operating ambient temperature operating ambient temperature under bias electrostatic discharge all pins note 1 outputs in 3-state outputs active CONDITIONS MIN. -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 - -65 0 -10 -2000 MAX. +4.6 +4.6 VDDA + 0.5 (4.6 max.) VDDA + 0.5 +5.5 VDDD + 0.5 100 +150 70 +80 +2000 UNIT V V V V V V mV °C °C °C V
|Zi| Ci 1998 May 15
input impedance input capacitance
- -
- 10
k pF
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
SYMBOL cs B diff
PARAMETER channel crosstalk
CONDITIONS fi = 5 MHz at -3 dB - - -
MIN. -
TYP.
MAX. -50 - -
UNIT dB
Analog-to-digital converters bandwidth differential phase (amplifier plus anti-alias filter = bypass) differential gain (amplifier plus anti-alias filter = bypass) ADC clock frequency DC differential linearity error DC integral linearity error 7 2 MHz deg
Gdiff
-
2
-
%
fclkADC DLE ILE Digital inputs VIL(SCL,SDA) VIH VIL(xtal) VIH(xtal) VILn VIHn ILI Ci Ci(n)
12.8 - - -0.5 0.7VDDD -0.3 2.0 -0.3 2.0 - outputs at 3-state - -
- 0.7 1 - - - - - - - - -
14.3 - -
MHz LSB LSB
LOW level input voltage pins SDA and SCL HIGH level input voltage pins SDA and SCL LOW level CMOS input voltage pin XTALI HIGH level CMOS input voltage pin XTALI LOW level input voltage all other inputs HIGH level input voltage all other inputs input leakage current input capacitance input capacitance all other inputs
+0.3VDDD VDDD + 0.5 +0.8 VDDD + 0.3 +0.8 5.5 1 8 5
V V V V V V µA pF pF
Digital outputs VOL(SCL,SDA) VOL VOH VOL(clk) VOH(clk) ILO tSU;DAT tHD;DAT 1998 May 15 LOW level output voltage pins SDA and SCL LOW level output voltage HIGH level output voltage LOW level output voltage for clocks HIGH level output voltage for clocks output leakage current at 3-state mode SDA/SCL at 3 mA (6 mA) sink current VDDD = max; IOL = 2 mA VDDD = min, IOH = -2 mA - 0 2.4 -0.5 2.4 - - - - - - - - - 0.4 (0.6) 0.4 VDDD + 0.5 +0.6 VDDD + 0.5 10 - - V V V V V µA
FEI input timing input data set-up time input data hold time 24 13 3 ns ns
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
SYMBOL
PARAMETER
CONDITIONS
MIN. - - - -
TYP.
MAX.
UNIT
Data and control output timing; note 1 CL tOHD;DAT tPD tPDZ output load capacitance output hold time propagation delay propagation delay to 3-state CL = 15 pF CL = 25 pF 15 4 - - 40 - 20 20 pF ns ns ns
Clock output timing (LLC and LLC2); note 2 CL(LLC) Tcy LLC tr tf td output load capacitance cycle time duty factors for tLLCH/tLLC and tLLC2H/tLLC2 rise time LLC, LLC2 fall time LLC, LLC2 delay time LLC output to LLC2 output at 1.5 V; LLC/LLC2 = 25 pF LLC LLC2 CL = 25 pF 15 35 70 40 - - -4 - - - - - - - 40 39 78 60 5 5 +8 pF ns ns % ns ns ns
Data qualifier output timing (CREF) tOHD;CREF tPD;CREF output hold time propagation delay from positive edge of LLC CL = 15 pF CL = 25 pF 4 - - - - 20 ns ns
Clock input timing (XTALI) XTALI fHn fH/fHn fSCn duty factor for tXTALIH/tXTALI nominal frequency nominal line frequency permissible static deviation 50 Hz field 60 Hz field Subcarrier PLL nominal subcarrier frequency PAL BGHI NTSC M; NTSC-Japan PAL M PAL N fSC fn f/fn lock-in range Crystal oscillator nominal frequency permissible nominal frequency deviation 3rd harmonic; note 3 - - 24.576 - - ±50 MHz 10-6 - - - - ±400 4433619 3579545 3575612 3582056 - - - - - - Hz Hz Hz Hz Hz 40 - - - - 60 - - 5.7 %
Horizontal PLL 15625 15734 - Hz Hz %
1998 May 15
25
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
SYMBOL Crystal oscillator fn f/fn Tf/fn
PARAMETER
CONDITIONS - - -
MIN.
TYP. -
MAX.
UNIT
nominal frequency permissible nominal frequency deviation permissible nominal frequency deviation with temperature
3rd harmonic; note 3
24.576 - -
MHz 10-6 10-6
±50 ±20
CRYSTAL SPECIFICATION (X1) Tamb(X1) CL Rs C1 C0 Notes 1. The levels must be measured with load circuits; 1.2 k at 3 V (TTL load); CL = 50 pF. 2. The effects of rise and fall times are included in the calculation of tOHD;DAT, tPD and tPDZ. Timings and levels refer to drawings and conditions illustrated in Figs 15 and 16. 3. Order number: Philips 4322 143 05291. Table 2 Processing delay FUNCTION Without amplifier or anti-alias filter With amplifier, without anti-alias filter With amplifier and anti-alias filter Note 1. Digital processing delay (LLC CLOCKS) for VBI data is defined in Fig.23 `Horizontal timing diagram'. TYPICAL ANALOG DELAY AI22 ADCIN (AOUT) (ns) 15 25 75 179 DIGITAL DELAY ADCIN VPO (LLC CLOCKS) [YDEL(2 to 0) = 000]; note 1 operating ambient temperature load capacitance series resonance resistor motional capacitance parallel capacitance 0 8 - - - - - 40 1.5 ±20% 3.5 ±20% 70 - 80 - - °C pF fF pF
1998 May 15
26
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
13 TIMING DIAGRAMS
SAA7111A
handbook, full pagewidth
tLLC tLLCL CLOCK OUTPUT LLC t t LLCH tPD 2.4 V 0.6 V
MGC658
2.6 V 1.5 V 0.6 V tr
f
tOHD;DAT OUTPUTS VPO, HREF, VREF, VS, HS
An explanation of the output formats is given in Table 6.
Fig.15 Clock/data timing (8-bit CCIR-656 format of the VPO-bus).
handbook, full pagewidth
tLLC tLLCL
tLLC 2.6 V 1.5 V 0.6 V tr t PD 2.4 V 0.6 V
CLOCK OUTPUT LLC tLLCH tPD OUTPUT CREF tOHD;CREF tdLLC2 CLOCK OUTPUT LLC2 tPD tOHD;DAT OUTPUTS VPO, HREF, VREF, VS, HS tOHD;CREF tdLLC2 tf
2.6 V 1.5 V 0.6 V
2.4 V 0.6 V
MGC659
An explanation of the output formats is given in Table 6. The FEI timing of the VPO-bus is illustrated in Figs 18 and 19.
Fig.16 Clock/data timing (12 and 16-bit CCIR-601 format of the VPO-bus).
1998 May 15
27
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
handbook, full pagewidth
tLLC tLLCL
tLLC 2.4 V 1.5 V 0.6 V
CLOCK OUTPUT LLC tf tr
OUTPUT CREF
,,,, ,,,,, ,,,,, ,,,, ,,,,, ,,,,, ,,,, ,,,,, ,,,,,
tLLCH tPD;CREF tOHD;CREF tOHD;CREF tPD;CREF tOHD;CREF R(7 : 3) G(7 : 5)
2.4 V 1.5 V 0.6 V
RGB (8, 8, 8) data VPO15 to VPO8
2.4 V 1.5 V 0.6 V tOHD;DAT G(4 : 2) B(7 : 3)
RGB (8, 8, 8) data VPO7 to VPO0
,,, ,,,
R(2 : 0) G(1 : 0) B(2 : 0)
,, ,,
tPD
,,, ,,,
tOHD;DAT
2.4 V 1.5 V 0.6 V
MBH227
An explanation of the output formats is given in Table 6.
Fig.17 Clock/data timing for RGB (8, 8 and 8) output format.
handbook, full pagewidth
LLC
CREF
HREF
tSU;DAT tPDZ
tHD;DAT
FEI tOHD;DAT VPO
t
PD
MGC656
to 3-state
from 3-state
I2C-bus bit FECO = 1.
Fig.18 FEI timing diagram (FEI sampling at CREF = HIGH) for OFTS = 0, 1 or 2).
1998 May 15
28
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
handbook, full pagewidth
LLC
CREF
HREF tSU;DAT FEI tPDZ tOHD;DAT VPO
MGC657
tHD;DAT
tPD
to 3-state
from 3-state
Timing is compatible with SAA7110; I2C-bus bit FECO = 0.
Fig.19 FEI timing diagram (FEI sampling at CREF = LOW) for OFTS = 0, 1 or 2).
handbook, full pagewidth
transmitted once per line SEQUENCE RESERVED LOW HIGH INCRHPLL 16
15 0 1 0
RESERVED
DTO RESET(1) RESERVED 50 Hz fields: 235 60 Hz fields: 232
INCRFSCPLL 45
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
128 BIT NO.: TIME SLOT:
2
3 1
16 19
63 67 68
MGC649
(1) Set to zero for one transmission, if a phase reset of the fsc - DTO is applied via I2C-bus bit CDTO. RTCO sequence is generated in LLC/4. The HPLL increment represents the actual LFCO frequency (fLFCO × 4 = fLLC); 16 LSB from 20, upper four bits are fixed to 0100b. INCR HPLL × f XTAL f LFCO = -----------------------------------------------word length DTO2 2 Where: fXTAL = 24.576 MHz, word length DTO2 = 20 bits. The fsc increment represents the actual subcarrier frequency (related to the actual clock); 23 LSB from 24, MSB is 0b. INCR FSCPLL × f XTAL INCR HPLL f sc = ------------------------------------------------------ × --------------------------word length DTO1 19 2 2 Where: word length DTO1 = 24 bits.
Fig.20 Real time control output.
1998 May 15
29
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
handbook, full pagewidth
LLC
CREF
LLC2
START OF ACTIVE LINE HREF 0 1 2 3 4
Yn
UVn
U0
V0
U2
V2
U4
END OF ACTIVE LINE HREF 715 716 717 718 719
Yn
UVn
V714
U716
V716
U718
V718
MGC646
Fig.21 HREF timing diagram.
handbook, full pagewidth
LLC
tSU
tHD
FEI
tOHD
VPO
tPDZ
,,, ,,,
tPD
MBH766
Fig.22 FEI timing in CCIR 656 mode [OFTS (1 : 0) = 3].
1998 May 15
30
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
handbook, full pagewidth
CVBS 26 × 1/LLC VBI 179 × 1/LLC
burst
burst
processing delay CVBS->VPO(2)
Y - output HREF (50 Hz) 720 × 2/LLC 27 × 2/LLC RTS1 (PLIN)(1)
0
sync clipped
12 × 2/LLC 144 × 2/LLC 43 × 2/LLC
4/LLC HS
HS (50 Hz) 108 programming range (step size: 8/LLC) HREF (60 Hz) 23 × 2/LLC
0
-107
16 × 2/LLC 720 × 2/LLC HS (60 Hz) HS (60 Hz) programming range (step size: 8/LLC) -106
MGD701
138 × 2/LLC
107
0
(1) PLIN is switched to output RTS1 via I2C-bus bit RTSE1 = 0. (2) See Table 2. (3) HDEL (1 : 0) = 0 0, YDEL (2 : 0) = 0 0 0.
Fig.23 Horizontal timing diagram.
1998 May 15
31
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
handbook, full pagewidth
622
623
624
625
1
2
3
4
5
6
7
8
22
23
input CVBS HREF VREF VRLN = 1(2) VREF VRLN = 0(2) 535 x 2/LLC VS RTS0 (ODD)(1)
(a) 1st field
310 input CVBS HREF
311
312
313
314
315
316
317
318
319
320
335
336
337
VREF VREF
VRLN = 1(2) VRLN = 0(2) 77 x 2/LLC
VS
RTS0 (ODD)(1) (b) 2nd field
MGG069
(1) ODD is switched to output RTS0 via I2C-bus bit RTSE0 = 0. (2) Additional VREF positions can be achieved via I2C-bits VCTR1 and VCTR0 (see Fig.9). The luminance peaking and the chrominance trap are bypassed during VREF = 0 if I2C-bus bit VBLB is set to logic 1. The chrominance delay line (chrominance-comb filter for NTSC, phase error correcting for PAL) is disabled during VREF = 0.
Fig.24 Vertical timing diagram for 50 Hz [nominal input signal VNL in normal mode (VNOI = 00b)].
1998 May 15
32
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
handbook, full pagewidth
522 (525)
523 (1)
524 (2)
525 (3)
1 (4)
2 (5)
3 (6)
4 (7)
5 (8)
6 (9)
7 (10)
8 (11)
17 (20)
18 (21)
19 (22)
(2)
input CVBS HREF VRLN = 1(3) VREF VRLN = 0(3) VREF 520 x 2/LLC VS RTS0 (ODD)(1) (a) 1st field
259 (262) input CVBS HREF
260 (263)
261 (264)
262 (265)
263 (266)
264 (267)
265 (268)
266 (269)
267 (270)
268 (271)
269 (272)
270 (273)
271 (274)
280 (283)
281 (284)
282 (285)
(2)
VRLN = 1(3) VREF VRLN = 0(3) VREF 81 x 2/LLC VS RTS0 (ODD)(1) (b) 2nd field
MGG070
(1) ODD is switched to output RTS0 via I2C-bus bit RTSE0 = 0. (2) Line numbers in parenthesis refer to CCIR line counting. (3) Additional VREF positions can be achieved via I2C-bus bits VCTR1 and VCTR0 (see Fig.9). The luminance peaking and the chrominance trap are bypassed during VREF = 0 if I2C-bus bit VBLB is set to logic 1. The chrominance delay line (chrominance-comb filter for NTSC, phase error correcting for PAL) is disabled during VREF = 0.
Fig.25 Vertical timing diagram for 60 Hz [nominal input signal VNL in normal mode (VNOI = 00b)].
1998 May 15
33
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
Table 3 OEYC 0 1 0 1 0 1 0 1 Note 1. Only active in 656-format (OFTS = 3). Digital output control FEI 0 0 1 1 0 0 1 1 TCLO(1) 0 0 0 0 1 1 1 1 Z active Z Z VPO 15 to 8 Z active Z Z Z Z Z Z Table 4 Clock frequencies CLOCK XTAL LLC LLC2 LLC4 LLC8 VPO 7 to 0 14 CLOCK SYSTEM 14.1 Clock generation circuit
SAA7111A
The internal CGC generates the system clocks LLC, LLC2 and the clock reference signal CREF. The internally generated LFCO (triangular waveform) is multiplied by 4 via the analog PLL (including phase detector, loop filter, VCO and frequency divider). The rectangular output signals have a 50% duty factor.
FREQUENCY (MHz) 24.576 27 13.5 6.75 3.375
handbook, full pagewidth
LFCO
BAND PASS FC = LLC/4
ZERO CROSS DETECTION
PHASE DETECTION
LOOP FILTER
OSCILLATOR
LLC
DIVIDER 1/2
DIVIDER 1/2
LLC2
DELAY
MGC632
CREF
Fig.26 Block diagram of clock generation circuit.
1998 May 15
34
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
14.2 Power-on control
SAA7111A
Power-on reset is activated at power-on, chip enable, PLL clock generation failure and if the supply voltage falls below 2.7 V. The RES signal can be applied to reset other circuits of the digital picture processing system.
handbook, full pagewidth
POC VDDA ANALOG
POC VDDD DIGITAL
CLOCK PLL LLC POC LOGIC CE POC DELAY RES
CLK0
CE
XTAL
LLCINT
RESINT
LLC
RES some ms 20 to 200 µs PLL-delay <1 ms 896 LCC digital delay 128 LCC
MGC633
CE = chip enable input; XTAL = crystal oscillator output; LLCINT = internal system clock; RESINT = internal reset; LLC = line-locked clock output; RES = reset output (active LOW).
Fig.27 Power-on control circuit.
1998 May 15
35
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
Table 5 Power-on control sequence PIN OUTPUT STATUS
SAA7111A
INTERNAL POWER-ON CONTROL SEQUENCE Directly after power-on asynchronous reset
FUNCTION
VPO15 to VPO0, RTCO, RTS0, RTS1, direct switching to high impedance for GPSW, HREF, VREF, HS, VS, LLC, 20 to 200 ms LLC2 and CREF are in high-impedance state LLC, LLC2, CREF, RTCO, RTS0, internal reset sequence RTS1, GPSW and SDA become active; VPO15 to VPO0, HREF, VREF, HS and VS are held in high-impedance state VPO15 to VPO0, HREF, VREF, HS and after power-on (reset sequence) a VS are held in high-impedance state complete I2C-bus transmission is required
Synchronous reset sequence
Status after power-on control sequence
15 OUTPUT FORMATS Table 6 Output formats of the VPO bus (note 1) 411 (12-BIT) Y07 Y06 Y05 Y04 Y03 Y02 Y01 Y00 U07 U06 V07 V06 X X X X 0 Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 U05 U04 V05 V04 X X X X 1 0 LLC2 OFTS0 = 0 OFTS1 = 1 RGB888 = X Y27 Y26 Y25 Y24 Y23 Y22 Y21 Y20 U03 U02 V03 V02 X X X X 2 Y37 Y36 Y35 Y34 Y33 Y32 Y31 Y30 U01 U00 V01 V00 X X X X 3 422 (16-BIT)(2) Y07 Y06 Y05 Y04 Y03 Y02 Y01 Y00 U07 U06 U05 U04 U03 U02 U01 U00 0 0 LLC2 OFTS0 = 1 OFTS1 = 0 RGB888 = X Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 V07 V06 V05 V04 V03 V02 V01 V00 1 CCIR-656 (8-BIT)(3) U07 U06 U05 U04 U03 U02 U01 U00 X X X X X X X X 0 0 LLC OFTS0 = 1 OFTS1 = 1 RGB888 = X Y07 Y06 Y05 Y04 Y03 Y02 Y01 Y00 X X X X X X X X V07 V06 V05 V04 V03 V02 V01 V00 X X X X X X X X 1 Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 X X X X X X X X RGB (16-BIT)(4) R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 - - LLC2 OFTS0 = 0 OFTS1 = 0 RGB888 = 0 RGB (24-BIT)(4) R7 R6 R5 R4 R3 G7 G6 G5 G4 G3 G2 B7 B6 B5 B4 B3 note 5 - - OFTS0 = 0 OFTS1 = 0 RGB888 = 1 R7 R6 R5 R4 R3 G7 G6 G5 R2 R1 R0 G1 G0 B2 B1 B0 note 6
BUS SIGNAL VPO15 VPO14 VPO13 VPO12 VPO11 VPO10 VPO9 VPO8 VPO7 VPO6 VPO5 VPO4 VPO3 VPO2 VPO1 VPO0 Pixel order Y Pixel order UV Data rates I2C-bus control signals
1998 May 15
36
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
Notes to Table 5 1. VPO bus allows connection to 5 V video data bus systems. 2. Values in accordance with CCIR 601. 3. Before and after the video data, video timing codes are inserted in accordance with CCIR 656. a) VPO15 to VPO8 = VPO7 to VPO0 = CCIR 656 data if I2C-bus bit TCLO = 0 b) VPO15 to VPO8 = CCIR 656 data, VPO7 to VPO0 = 3-state if I2C-bus bit TCLO = 1.
SAA7111A
4. During HREF = LOW RGB levels are set to 16 (10 hex). RGB 16-bit is achieved by dropping the LSBs of the 8-bit signals (after dithering if desired). 5. CREF = 0 (see Fig.17). 6. CREF = 1 (see Fig.17).
handbook, full pagewidth
+255 +235 white
+255 +240 +212
blue 100% blue 75%
+255 +240 +212
red 100% red 75%
+128
LUMINANCE 100%
+128 U-COMPONENT
colourless
+128 V-COMPONENT
colourless
+44 +16 0 black +16 0
yellow 75% yellow 100%
+44 +16 0
cyan 75% cyan 100%
MGC634
a.
Y output range.
b.
U output range (Cb).
c.
V output range (Cr).
CCIR Rec. 602 digital levels.
Equations for modification to the YUV levels via BCS control I2C-bus bytes BRIG, CONT and SATN. Luminance: CONT Y OUT = Int ----------------- × ( Y 128 ) + BRIG 71 Chrominance: SATN UV OUT = Int ---------------- × ( Cr, Cb 128 ) + 128 64 It should be noted that the resulting levels are limited to 1 to 254 in accordance with CCIR-601/656 standard.
Fig.28 VPO output signal range with default BCS settings.
1998 May 15
37
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
handbook, full pagewidth
+255 +209 white
+255 +199 white
LUMINANCE
LUMINANCE
+71 +60 SYNC 1
black black shoulder
+60 SYNC
black shoulder = black
sync bottom
1
sync bottom
MGD700
a.
For sources containing 7.5 IRE black level offset (e.g. NTSC-M).
b.
For sources not containing black level offset.
VBI data levels are not dependent on BCS settings.
Fig.29 VBI data bypass output range.
handbook, full pagewidth
quartz (3rd harmonic) 24.576 MHz XTAL C= 10 pF XTALI
54
XTAL
54
SAA7111A
55 XTALI 55
SAA7111A
L = 10 µH ± 20% C= 10 pF C= 1 nF
MGG072
a.
With quartz crystal.
b.
With external clock.
Order number: Philips 4322 143 05291.
Fig.30 Oscillator application.
1998 May 15
38
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
16 APPLICATION INFORMATION
SAA7111A
handbook, full pagewidth
VDD VDDA C8 100 nF VSSA
C15 C9 100 nF C7 n.c. VDDA0 VDDA1 TRST 100 nF VDDA2 n.c. TMS TDO TDI n.c. TCK BST VSS VDD1 VDD2 VDD3 VDD4 VDD5 100 nF C14 C13 100 nF 100 nF C12 C11 100 nF 100 nF VSS
15 R10 AI22 27 R4 C4 6 22 nF
11
7
4
3
2
59
58
57
41
33
25
18 34 35 36 37 38 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VPO(15 : 0)
VSSA 47 R9 AI21 27 R3 C3 8 22 nF
39 42 43 44
VSSA 47 R8 AI12 27 R2 VSSA 47 R7 AI11 27 R1 VSSA 47 VDDD SCL SDA FEI R6
C2 10 22 nF
45 46 47 48
C1 12 22 nF
49
SAA7111A
50 51
R5 1 k
24 63 62 52
31 17 27 30 60 28 29 53 14
HREF VREF HS VS RTCO RTS1 RTS0 GPSW AOUT LLC LLC2 CREF RES
1 k VSS XTAL 54 55
20 21 22 23
Q1(24.576 MHz) XTALI L1 10 µH C16 1 nF C17 C18 16 VSSA0 9 VSSA1 5 VSSA2 13 VSSS 56 40 VSS1 VSS2 32 26 VSS3 VSS4 19 61 IICSA VSS5 64 1
10 pF 10 pF VSS
n.c. VSSA VSS VSS n.c.
MGG071
Fig.31 Application diagram.
1998 May 15
39
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
handbook, full pagewidth
34 35 36 VPO (15 : 8) 37 38 39 42 43 44 45 46 VPO (7 : 0) 47 48 49 50 51
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VPO (15 : 11) 3
R (7 : 3)
VPO (10 : 8) 3 VPO (7 : 5) 3 VSS OEN D7 D6 D5 D4 D2 D1 D0 VSS VSS VPO (4 : 0) 5 e.g. VDD O7 O6 O5 O4 O2 O1 00 CLK
G (7 : 5) G (4 : 2)
VDD R (2 : 0) 3 8
R (7 : 0)
G (1 : 0) 2 B (2 : 0) 3 8 8
G (7 : 0) B (7 : 0)
D3 74HCT574 O3
SAA7111A
31 17 27 30 60 28 29 53 14 20 21 32 23
B (7 : 3)
HREF VREF HS VS RTCO RTS1 RTS0 GPSW AOUT LLC CREF RES
MGG073
e.g. 74HCT240 LLC2 LLC2N
I2C-bus control bits: OFTS(1 : 0) = 00 (subaddress 10H, bits D7 and D6). RGB888 = 1 (subaddress 12H, bit D3).
Fig.32 Application diagram for RGB 24-bit output format.
16.1
Layout hints
Use separate ground planes for analog and digital ground. Connect these planes at one point directly under the device, by using a zero resistor. Use separate supply lines for analog and digital supply. Place the supply decoupling capacitors close to the supply pins.
Place the coupling (clamp) capacitors close to the analog input pins. Place the termination resistors close to the coupling capacitors. Care should be exercised concerning the hidden layout capacitors around the crystal application. To avoid reflection effects use serial resistors in the clock, sync and data lines.
1998 May 15
40
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
17 I2C-BUS DESCRIPTION 17.1 I2C-bus format Write procedure SLAVE ADDRESS W ACK-s SUBADDRESS ACK-s DATA (N BYTES)
SAA7111A
Table 7 S Table 8 S Sr Table 9
ACK-s
P
Read procedure (combined format) SLAVE ADDRESS W SLAVE ADDRESS R Description of I2C-bus format DESCRIPTION START condition repeated START condition 0100 1000b (IICSA = LOW) or 0100 1010b (IICSA = HIGH) 0100 1001b (IICSA = LOW) or 0100 1011b (IICSA = HIGH) acknowledge generated by the slave acknowledge generated by the master subaddress byte; see Table 10 data byte; see Table 10; note 1 STOP condition read/write control bit; X = 0, order to write (the circuit is slave receiver); X = 1, order to read (the circuit is slave transmitter) read = 49H or 4BH; note 2 write = 48H or 4AH IICSA = 0 or 1 ACK-s ACK-s SUBADDRESS DATA (N BYTES) ACK-s ACK-m P
CODE S Sr Slave address W Slave address R ACK-s ACK-m Subaddress Data P X = LSB slave address Slave address
Subaddresses
00H chip version 01H reserved 02h to 05H front-end part 06H to 13H decoder part 14H reserved 15H to 17H decoder part 18H to 19H reserved 1AH to 1CH Line-21 text slicer part 1DH to 1EH reserved 1FH status byte
read and write; note 3 - read and write read and write - read and write - read only - read only
Notes 1. If more than one byte DATA is transmitted then the auto-increment of the subaddress is performed. 2. During slave transmitter mode the SCL-LOW period may be extended by pulling SCL to LOW (in accordance with the I2C-bus specification). 3. The I2C-bus subaddress 00 has to be initialized with 0 before being read.
1998 May 15
41
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
Table 10 I2C-bus receiver/transmitter overview READ SLAVE ADDRESS 49H 4BH D7 ID07
(1)
SAA7111A
WRITE 48H 4AH D6 D5 ID05
(1)
IICSA 0 1
REGISTER FUNCTION Chip version Reserved Analog input contr 1 Analog input contr 2 Analog input contr 3 Analog input contr 4 Horizontal sync start Horizontal sync stop Sync control Luminance control Luminance brightness Luminance contrast Chroma saturation Chroma Hue control Chroma control Reserved Format/delay control Output control 1 Output control 2 Output control 3 Reserved V_GATE1_START V_GATE1_STOP V_GATE1_MSB Reserved Text slicer status Decoded bytes of the text slicer Reserved Status byte Note
SUBADDR 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18-19 1A 1B 1C 1D-1E 1F
D4 ID04
(1)
D3 ID03
(1)
D2 ID02
(1)
D1 ID01
(1)
D0 ID00
(1)
ID06
(1)
FUSE1
(1)
FUSE0 HLNRS GAI16 GAI26 HSB6 HSS6 FSEL PREF BRIG6 CONT6 SATN6 HUEC6 CSTD2
(1)
GUDL2 VBSL GAI15 GAI25 HSB5 HSS5 EXFIL BPSS1 BRIG5 CONT5 SATN5 HUEC5 CSTD1
(1)
GUDL1 WPOFF GAI14 GAI24 HSB4 HSS4
(1)
GUDL0 HOLDG GAI13 GAI23 HSB3 HSS3 VTRC VBLB BRIG3 CONT3 SATN3 HUEC3 DCCF
(1)
MODE2 GAFIX GAI12 GAI22 HSB2 HSS2 HPLL UPTCV BRIG2 CONT2 SATN2 HUEC2 FCTC
(1)
MODE1 GAI28 GAI11 GAI21 HSB1 HSS1 VNOI1 APER1 BRIG1 CONT1 SATN1 HUEC1 CHBW1
(1)
MODE0 GAI18 GAI10 GAI20 HSB0 HSS0 VNOI0 APER0 BRIG0 CONT0 SATN0 HUEC0 CHBW0
(1)
GAI17 GAI27 HSB7 HSS7 AUFD BYPS BRIG7 CONT7 SATN7 HUEC7 CDTO
(1)
BPSS0 BRIG4 CONT4 SATN4 HUEC4 CSTD0
(1)
OFTS1 GPSW RTSE1 VCTR1
(1)
OFTS0 CM99 RTSE0 VCTR0
(1)
HDEL1 FECO TCLO CCTR1
(1)
HDEL0 COMPO CBR CCTR0
(1)
VRLN OEYC RGB888 BCHI1
(1)
YDEL2 OEHV DIT BCHI0
(1)
YDEL1 VIPB AOSL1 BCLO1
(1)
YDEL0 COLO AOSL0 BCLO0
(1)
VSTA7 VSTO7
(1) (1) (1)
VSTA6 VSTO6
(1) (1) (1)
VSTA5 VSTO5
(1) (