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4 3 2 1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO'S PROPERTY. Table of Contents
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
Sheet 1 Cover
D Sheet 2 Diagram (Block/Power) & Annotations D
Sheet 8 Clock Generator
Sheet 9 Thermal Sensor & FAN
Sheet 10-12 Merom-4M CPU
Sheet 13-17 Crestline-GMCH
Sheet 18 DDR2 SODIMM A
MILAN Sheet 19 DDR2 SODIMM B
g l
Sheet 20-23 ICH8-M
Sheet 24 ICH8-M STRAP
n a
Sheet 25-28 NIVIDIA NB8P
Sheet 29 NIVIDIA NB8P STRAP
u ti
Sheet 30 Video Memory Channel A
CPU : MEROM Sheet 31 Video Memory Channel B
Sheet 32 LCD Connector
s n
C Chip Set : SANTAROSA CHIPSET Sheet 33 CRT PORT C
Sheet 34-36 CRADBUS CONTROLER
Remarks : Mobility Platform Sheet 37 MINI CARD AND ROBSON DVB-T
m e
Sheet 38 AUDIO - ALC262
Sheet 39 AUDIO - AMP
a id
Sheet 40 AUDIO - HEADPHONE & MIC JACK
Sheet 41 AUDIO - POWER
Model Name : MILAN Sheet 42-43 LAN AND CONNECTOR
S f
Sheet 44-45 MICOM AND MICOM POWER LOGIC
PBA Name : MAIN Sheet 46
Sheet 47
POWER - SWITCH POWER
POWER - SANTAROSA PLATFORM POWER
PCB Code : BA41-00745A Sheet 48
Sheet 49
POWER - DDR2 POWER
POWER - CHARGE & POWER MANAGEMENT
n
Dev. Step : SR Sheet 50
Sheet 51
POWER - P3.3V_ALW & P5V_AUX
POWER - CPU VRM
B B
o
Revision : 1.0 Sheet 52 POWER - GFX CORE
Sheet 53 HDD & ODD Connector
T.R. Date : Sheet 54 USB/MDC/IR Connector
C
Sheet 55 KEYBOARD TOUCHPAD & 80 PORT Connector
Sheet 56~58 Test Point
Sheet 59~60 MIO Board
DRAW CHECK APPROVAL
A A
DRAW DATE TITLE
CHECK
SUN XIAO,
DEV. STEP
8/23/2006
MILAN SAMSUNG
ELECTRONICS
WUSHIJIANG, SR 1.0 MILAN
APPROVAL REV PART NO.
KEVIN LEE, 1.0 COVER BA41-00744A
MODULE CODE LAST EDIT
April 6, 2007 12:24:35 PM PAGE 1 OF 60
4 3 2 1
COM-22C-015(1996.6.5) REV. 3 D:/mentor/milan-document/Milan_sr0405
4 3 2 1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO'S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
FAN Mobile Processor CPU Smart IGFX / EGFX
DC/DC Charging Battery DC/DC
Clocking
CK-505
PG 9 CPU IMVP-6
Circuit Module CORE
D Merom-4M D
PG 8 CPU PG 51 PG 49 PG 49 46 PG 52
Thermistor (800MHz)
(TBD) 478pin
PG 9
ON BOARD
PG 10,11,12 L2 Cache : 4 MB
PG 71 HDMI FSB
Termination VCCP / DC-DC
PG 18,19
800 MT/S PG 47
g l
Channel A (Standard) DDR II 667/533,400 DDR II PG 18
SODIMM 0
GMCH-M 965 Dual channel DDR II Power
NVIDIA
n a
DDR II PG 19 PG 48
Channel B (Reverse) DDR II 667/533,400
NB8P Crestline-GM SODIMM 1
PG 32 LCD 30PIN
LCD/CRT/TV
u ti
(TBD)
M/S(SD...) PG 34
PG 25-29 PG 13 - 17 1299 FCBGA CARDBUS
PG 33 CRT CardBus PG 35
s n
C R5C843 C
Direct Media Interface CLINK
x4, 1.5V PG 34, 35, 36
PG 54 USB 0,1,2,3 USB 0,1,2,3
m e
PG 37
52P
Lane 0 MINI CARD
ANT PCIE x1
a id
PG 55 Bluetooth USB 5 ROBSON 8055(GLAN)
SVHS / RCA
Component DVB-T OPTION PG 42
ICH8-M RJ45 PG 43
S f
GLCI (Lane5) 82566Mx (Nineveh) OPTION
HDAUDIO
High Definition Audio 676 BGA
LCI 82562V
ANT
Aud. Audio HD Primary
PCIE x1 Lane 1 52P
AMP
ALC262 12P PG 20 - 24 USB 4 Mini Card Kedron
CLINK
n
MDC HD Secondary
PG 39 PG 38 RJ11
PG 37
Modem
PG 43
B B
o
PG 40 PG 54
SPI
HEADPHONE SPI ROM
PG 22
C
MIC-IN
LPC
SATA 0
2P 2P PG 53 SATA HDD
PATA MIO_BUTTON
80 Port
Pri. IDE slave
SPKR R PG 55 Touch
MICOM PAD PG 55
3.3V LPC, 33MHz
HD64F2169/2160
PG 51 TMKBC (TBD) KBD PG 55
SPKR L
PG 53
CD-ROM
A CD / DVD A
DRAW DATE TITLE
FIR(CIR) LED PG 45
CHECK
SUN XIAO,
DEV. STEP
8/23/2006
MILAN SAMSUNG
ELECTRONICS
PG 54 WUSHIJIANG, SR 1.0
APPROVAL REV PART NO.
KEVIN LEE, 1.0 BLOCK DIAGRAM BA41-00744A
MODULE CODE LAST EDIT
April 6, 2007 12:24:35 PM PAGE 2 OF 60
4 3 2 1
COM-22C-015(1996.6.5) REV. 3 D:/mentor/milan-document/Milan_sr0405
4 3 2 1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO'S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
BOARD INFORMATION
D SCHEMATIC ANNOTATIONS AND BOARD INFORMATION D
PCI Devices
Crystal / Oscillator
Devices IDSEL# REQ/GNT# Interrupts
TYPE FREQUENCY DEVICE USAGE
Cardbus AD25 3 B,C,D
Crystal 32.768KHz ICH8-M Real Time Clock
g l
DT PCI SLOT AD22 1 B,C,D,C Crystal 10MHz MICOM HD64F2169/2160
MiniPCI SLOT AD23 2 A,B Crystal 14.318MHz CLOCK-Generator CK-505
USB AD29(internal) - USB2.0 #0 (USB0) : A Crystal 24.576MHz Cardbus Controller 1394
USB2.0 #1 (USB1) : D Crystal 25MHz LAN Intel LAN
USB2.0 #2 (USB4) : C
n a
Crystal 27MHz (TBD) VIDEO PEG
USB2.0 #3 (USB5) : E 24.576MHz (TBD) HD Audio Audio
Crystal
USB2.0 #4 (EHCI) : H
Hub to PCI AD30(internal) - -
LPC bridge/IDE/AC97/SMBUS AD31(internal) - B
u ti
Internal MAC AD24(internal) - E
AC Link - - B
GLAN - - F
LCD Pannel Detect (TBD)
s n
C Devices Resolution PANNEL_DETECT_0 C
m e
Voltage Rails
2
a id
VDC
VCC_CORE
Primary DC system power supply (7 to 21V)
Core Voltage for CPU
I C / SMB Address
MCH_CORE Core Voltage for CPU Devices Address Hex Bus
ICH_CORE Core Voltage for CPU
P1.05V (VCCP) VTT for CPU, Crestline & ICH8-M
S f
ICH8-m Master - SMBUS Master
P1.05V_M 1.05V switched power rail for ME (on in M0/M1) CPU Thermal Sensor 1001 110x 9Ch Thermal Sensor
P1.25V_M 1.25V switched power rail for ME (on in M0/M1) SODIMM0 1010 000x A0h -
P3.3V_M 3.3V switched power rail for ME (on in M0/M1) SODIMM1 1010 010x A4h -
P3.3V_A 3.3V always power rail (by KBC3_ALWS_ON) Thermal Sensor on SODIMM0 0011 000x 30h -
MICOM_P3V 3.3V always power rail (for Micom) Thermal Sensor on SODIMM1 0011 010x 34h -
LAN_3.3V 3.3V always power rail (for LAN) CK-505M (Clock Generator) 1101 001x D2h Clock, Unused Clock Output Disable
P1.5V 1.5V switched off power rail (off in S3-S5) DB400 (PCI Express Clocks) 1101 110x DCh Clock Buffer for PCI Express
P1.5V_AUX 1.5V switched on power rail TBD 0100 1100 4Ch Thermal Sensor
P2.5V 2.5V switched off power rail (off in S3-S5) TBD : (LVDS BackLight Inverter) 0101 1000 58h -
n
P1.8V 1.8V switched off power rail (off in S3-S5) TBD : (ALS) 0111 0010 72h Ambient Light Sensor
P1.8V_AUX 1.8V power rail for DDR TBD : (AUX DISPLAY) 0011 110x 3Ch EMA
P0.9V 0.9V power rail for DDR LAN 1100 1000 C8h 82566
P3.3V 3.3V switched off power rail (off in S3-S5) PCI Express Docking TBD TBD TBD
B P3.3V_AUX 3.3V switched on power rail TPM TBD TBD TBD B
o
P5V 5.0V switched off power rail (off in S3-S5)
P5V_AUX 5.0V switched on power rail
USB PORT Assign
PORT #
0
1
2
3
4
5
6
7
8
ASSIGNED TO
SYSTEM PORT 0
SYSTEM PORT 1
DMB
Expresas Card
DOCKING PORT 0
Bluetooth
Mini PCI Express
Aux Display
Test Port (RSVD)
PORT #
0
1
2
3
4
5
C
PCI Express Assign
ASSIGNED TO
PCIE x1 Slot
Mini Card (Golan)
Mini Card (WIBRO : RSVD)
Expresas Card
DOCKING PORT 0
GLAN
REVISION HISTORY
See rev notes for more information.
9 WWAN/WIBRO (TBD)
A A
DRAW DATE TITLE
CHECK
SUN XIAO,
DEV. STEP
8/23/2006
MILAN SAMSUNG
WUSHIJIANG, SR 1.0
ELECTRONICS
APPROVAL REV PART NO.
KEVIN LEE, 1.0 BOARD INFO BA41-00744A
MODULE CODE LAST EDIT
April 6, 2007 12:24:35 PM PAGE 3 OF 60
4 3 2 1
4 3 2 1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO'S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
POWER DIAGRAM
KBC3_ALWS_ON
KBC3_MEPWRON KBC3_SUSPWR KBC3_MEPWRON KBC3_PWRON
D (CHP3_S4_STATE*) (CHP3_SLPM*) D
(CHP3_SLPM*) (CHP3_SLPS3*) KBC3_VRON
ME ENABLE ME DISABLE
AC Adapter
(CHP3_S4_STATE*) or (CHP3_SLPM*) MEROM
CPU_CORE
: KBC3_DDRPWRON (CHP3_SLPS4*)
ME OPTION PEG
P1.8V
VDC P1.8V_AUX (ME) P1.8V_AUX
g l
GDDR-3 for PEG
DOCK DC
SODIMM (DDR II) SODIMM (DDR II)
CRESTLINE CRESTLINE
n a
P0.9V DDR II-Termination
DDR II for PEG (TBD)
P0.9 (ME) ME OPTION
Battery DC
u ti
DDR II-Termination CRESTLINE
DDR II for PEG (TBD) P1.25V ICH8-M
R5C843
P1.25V_M
s n
PEG
P1.25V_M
C nVidia C
CRESTLINE
CRESTLINE P1.2V
P1.05V_M
m e
P1.05V MEROM
CRESTLINE P1.05V_M CRESTLINE
(VCCP) ICH8-M
a id
MICOM_P3V CRESTLINE
ICH8-M PCMCIA HDD R5C843
FDD USB M_PCI PEG
MICOM P5V_AUX P5V CRT HEATSINK FAN CIRCUIT
S f
MICOM MDC AUX DISPLAY
P3.3V_M
CK505
SPI P1.5V CRESTLINE VCCA MEROM
ICH ICH8-M
P1.5V
P3.3V_ALW
n
P3.3V_AUX CRESTLINE Thermal Sensor MICOM
Power Sequence by ME On/Off ICH8-M SODIMM
ICH8-M
ICH8-M P3.3V_M P3.3V SUPER I/O FWH M_PCI
B Host Boot / ME Off LAN PEG PCMCIA B
o
TPM
P3.3V_LAN MDC
MDC LEDs LCD
(SLPS4* = S4_STATE*) > (SLPM* = SLPS3*) BT CRESTLINE
P3.3V_WLL CK505
CRESTLINE
INT_VR_ICH
Host / ME Boot ICH8-M SPI ICH8-M
LAN P1.05V_AUX P2.5V
C
(SLPS4* = S4_STATE*) > SLPM* > SLPS3* R5C843
PEG
INT_VRM_LAN
Host S5 / ME Boot P1.8V_LAN VTT3_PWRGD ATI (TBD)
(SLPS4* = SLPM*) > S4_STATE* > SLPS3* P1.5V_AUX EGFX_CORE nVidia (TBD)
LAN
ICH8-M
Power On/Off Table by S-state P1.0V_LAN MCH3_GFX_VR_EN
IGFX_CPRE CRESTLINE
Rail M0 M1 M off
LAN
State S0 S3 S4 S5 S3 S4 S5
+V*A(LWS)
S5-S3 S3- S0 S0
ON ON ON ON ON ON ON
+V*LAN
+1.8V_AUX ON ON ON ON ON
S5-S3/Moff-M0 S4-S3/M1-M0 S0/M0
A A
+0.9V ON ON ON ON
DRAW DATE TITLE
+V*AUX ON ON ON
CHECK
SUN XIAO,
DEV. STEP
8/23/2006