Text preview for : Toshiba L640 Quanta TE2 DA0TE2MB6F0.pdf part of TOSHIBA Toshiba L640 Quanta TE2 DA0TE2MB6F0 TOSHIBA Toshiba L640 Quanta TE2 DA0TE2MB6F0.pdf
Back to : Toshiba L640 Quanta TE2 D | Home 1 2 3 4 5 6 7 8 PCB STACK UP LAYER 1 : TOP LAYER 2 : GND TE2 Block Diagram LAYER 3 : IN1 LAYER 4 : IN2 A LAYER 5 : VCC A USB-0 INT_LVDS LCD/CCD Con. P15 LAYER 6 : BOT DDRIII-SODIMM1 DDRIII-SODIMM2 Arrandale (UMA+VGA) INT_CRT CRT Con. P12,13 daughter board DDR SYSTEM MEMORY P15 Dual Channel DDR III PCI-E Graphics Interfaces 800/1066/1333 MHZ INT_HDMI HDMI Con. HDMI Level Shift rPGA 989 P14 P14 SATA - HDD Re-Driver P3,4, 5, 6, P18 P18 FDI DMI DMI(x4) SATA - ODD P18 SATA 0 FDI DMI B SATA 1 B SATA PCI-Express SATA 5 PCI-E USB-13 ESATA Con. P17 PCIE-3 CK505 3G P2 USB-10 USB Con. daughter board P24 USB-8 PCIE-4 Ibex Peak-M POWER SYSTEM ISL88731A P25 USB-4 USB 2.0 (Port0~13) SIM CARD. PCIE-5 RT8210B P26 USB P16 WLAN UP6163 P27 PCH USB-5 UP6111A P28 USB-2 P24 Bluetooth Con. P7,8, 9, 10, 11 RT015A P29 P23 ISL62882C P30 PCIE-6 RT8152C P32 USB-3 RTC Giga/10/100 Lan Cardreader P28 P21 BATTERY +VCC_CORE C USB Con. USB-9 C P9 P17 Cardreader Con. +1.5V Azalia +1.5VSUS 3 IN 1 P29 IHDA NVRAM LPC +VTT LPC +1.05V +1.8V Audio Codec EC +1.5V_S5 P19 P22 +3VPCU Port-B Port-A +3V_S5 +3V FAN K/B Con. HALL Sensor SPI Flash Touch Pad /B Power /B +5VPCU MDC Con. MIC JACK HP SPK Con. Con. Con. +5V_S5 P19 P19 P19 P19 P4 P23 P15 P22 P23 P23 +5V D D +SMDDR_VTERM +SMDDR_VREF Quanta Computer Inc. PROJECT : TE2 Size Document Number Rev 2A Block Diagram Date: Wednesday, March 10, 2010 Sheet 1 of 35 1 2 3 4 5 6 7 8 5 4 3 2 1 CLOCK Gen [CLK] Pin1/17/24 Sligo595 =>1.5V (AL000595000) +3V Sligo590 =>3.3V (AL8SP590000) +1.05V +VDDIO_CLK 80mA(20mils) L18 PBY160808T-601Y-N_1A 250mA(20mils) +3V_CK505_VDD L6 PBY160808T-601Y-N_1A D C494 C491 C327 C318 D C485 C297 C489 10U/6.3V_8X 0.1U/10V_4X 0.1U/10V_4X U10 *10U/6.3V_8X 10U/6.3V_8X 0.1U/10V_4X 0.1U/10V_4X R237 +1.5V *590@0_6 5 VDD_27 29 VDD_REF VDD_SRC_I/O 15 VDD_CPU_I/O 18 L5 595@PBY160808T-601Y-N_1A 150mA(20mils) +1.5V_CK505_VDD 1 VDD_DOT_1.5 DOT_96 3 DREFCLK_R RP5 2 1 *short_4P2R CLK_BUF_DREFCLKP [8] 17 4 DREFCLK#_R 4 3 VDD_SRC_1.5 DOT_96# CLK_BUF_DREFCLKN [8] 24 VDD_CPU_1.5 6 CLK_VGA_27M_R R246 *33_4 C486 C309 C322 C308 XTAL_OUT 27M CLK_VGA_27M#_R R249 *33_4 27 XTAL_OUT 27M_SS 7 595@10U/6.3V_8X *0.1U/10V_4X *0.1U/10V_4X *0.1U/10V_4X XTAL_IN 28 C319 *15P/50V_4C XTAL_IN DREFSSCLK_R RP6 *short_4P2R SRC_1/SATA 10 2 1 CLK_BUF_DREFSSCLKP [8] 11 DREFSSCLK#_R 4 3 SRC_1#/SATA# CLK_BUF_DREFSSCLKN [8] CPU_SEL 30 13 PCIE_3GPLL_R RP7 2 1 *short_4P2R REF_0/CPU_SEL SRC_2 CLK_BUF_PCIE_3GPLLP [8] 14 PCIE_3GPLL#_R 4 3 SRC_2# CLK_BUF_PCIE_3GPLLN [8] CGDAT_SMB 31 CGCLK_SMB SDA ICS_CPU_STOP# R255 10K_4 32 SCL *CPU_STOP# 16 +3V C CLK_PCH_14M R216 33_4 2 20 CLK_BUF_BCLK1_P_R TP59 C [8] CLK_PCH_14M VSS_DOT CPU_1 8 19 CLK_BUF_BCLK1_N_R TP58 VSS_27 CPU_1# CLK_BUF_BCLK0_P_R RP4 *short_4P2R 9 VSS_SATA CPU_0 23 4 3 CLK_BUF_BCLKP [8] C291 12 22 CLK_BUF_BCLK0_N_R 2 1 VSS_SRC CPU_0# CLK_BUF_BCLKN [8] 21 VSS_CPU *15P/50V_4C 26 25 VR_PWRGD_CLKEN VSS_REF CKPWRGD/PD# 33 GND SLG8SP595VTR CLK POWERGOOD CLK CRYSTAL CLK CPU_SEL CLK I2C Change to +3VPCU (follow CRB) B B +3V +3V +3VPCU R225 10K_4 VR_PWRGD_CLKEN R221 3 *10K_4 R229 R227 2 Q15 100K/F_4 [30] VR_PWRGD_CK505# 2 Y2 CPU_SEL 10K_4 XTAL_IN XTAL_OUT 2N7002_200MA 1 2 3 1 CGDAT_SMB [8,16,20] SDATA CGDAT_SMB [12,13] 14.318MHZ_30 R224 1 C295 C296 10K_4 2N7002_200MA 33P/50V_4N 33P/50V_4N Q51 R228 +3V 10K_4 2 A A 0 1 3 1 CGCLK_SMB [8,16,20] SCLK CGCLK_SMB [12,13] Quanta Computer Inc. CPU =133MHz CPU=100MHz 2N7002_200MA CPU_SEL Q50 PROJECT : TE2 (default) Size Document Number Rev 2A CLOCK GENERATOR Date: Friday, March 19, 2010 Sheet 2 of 35 5 4 3 2 1 1 2 3 4 5 6 7 8 U16A PEG_ICOMPI B26 PEG_COMP R341 49.9/F_4 PEG_ICOMPO A26 [9] DMI_TXN0 A24 DMI_RX#[0] PEG_RCOMPO B27 [9] DMI_TXN1 C23 DMI_RX#[1] PEG_RBIAS A25 PEG_RBIAS R342 750/F_4 [9] DMI_TXN2 B22 DMI_RX#[2] [9] DMI_TXN3 A21 DMI_RX#[3] PEG_RX#[0] K35 J34 U16B PEG_RX#[1] R207 20/F_4 H_COMP3 AT23 [9] DMI_TXP0 B24 DMI_RX[0] PEG_RX#[2] J33 COMP3 BCLK A16 CLK_CPU_BCLKP [10] [9] DMI_TXP1 D23 G35 R206 20/F_4 H_COMP2 AT24 B16 CLK_CPU_BCLKN [10] DMI_RX[1] PEG_RX#[3] R104 49.9/F_4 H_COMP1 G16 COMP2 BCLK# [9] DMI_TXP2 B23 DMI_RX[2] PEG_RX#[4] G32 COMP1 MISC [9] DMI_TXP3 A22 F34 R205 49.9/F_4 H_COMP0 AT26 AR30 TP86 DMI_RX[3] PEG_RX#[5] COMP0 BCLK_ITP PEG_RX#[6] F31 AH24 SKTOCC# BCLK_ITP# AT30 TP87 D24 D35 TP34 A [9] DMI_RXN0 [9] DMI_RXN1 G24 F23 DMI_TX#[0] DMI_TX#[1] DMI PEG_RX#[7] PEG_RX#[8] E33 C33 H_CATERR# AK14 CLOCKSPEG_CLK# PEG_CLK E16 D16 CLK_PCIE_3GPLLP [8] A [9] DMI_RXN2 DMI_TX#[2] PEG_RX#[9] CATERR# CLK_PCIE_3GPLLN [8] [9] DMI_RXN3 H23 DMI_TX#[3] PEG_RX#[10] D32 [10] H_PECI AT15 PECI H_PROCHOT#_D AN26 A18 CLK_DREFSSCLKP_R R340 3 4 *short_4P2R DPLL_REF_SSCLK D25 PEG_RX#[11] B32 C31 CPU_PM_THRMTRIP# AK15 PROCHOT# THERMAL DPLL_REF_SSCLK A17 CLK_DREFSSCLKN_R 1 2 CLK_DREFSSCLKP [8] [9] DMI_RXP0 DMI_TX[0] PEG_RX#[12] THERMTRIP# DPLL_REF_SSCLK# CLK_DREFSSCLKN [8] Only for UMA [9] DMI_RXP1 F24 DMI_TX[1] PEG_RX#[13] B28 [9] DMI_RXP2 E23 DMI_TX[2] PEG_RX#[14] B30 [9] DMI_RXP3 G23 A31 H_CPURST#_R AP26 F6 DDR3_DRAMRST#_C DMI_TX[3] PEG_RX#[15] RESET_OBS# SM_DRAMRST# [9] PM_SYNC AL15 PM_SYNC PEG_RX[0] J35 AN14 VCCPWRGOOD_1 DDR3 SM_RCOMP[0] AL1 SM_RCOMP_0 AM1 SM_RCOMP_1 R447 R446 100/F_4 24.9/F_4 2.7GT/s data rate PEG_RX[1] H34 [10] H_PWRGOOD AN27 VCCPWRGOOD_0 SM_RCOMP[1] [9] FDI_TXN[7:0] FDI_TXN0 E22 PEG_RX[2] H33 F35 PM_DRAM_PWRGD AK13 SM_DRAMPWROK MISC SM_RCOMP[2] AN1 SM_RCOMP_2 R445 R210 130/F_4 10K_4 +VTT FDI_TXN1 FDI_TX#[0] PEG_RX[3] D21 FDI_TX#[1] PEG_RX[4] G33 TP41 AM26 TAPPWRGOOD PM_EXT_TS#[0] AN15 PM_EXT_TS#0 R212 *short_4 PM_EXTTS#0 [12] FDI_TXN2 D19 E34 AP15 PM_EXT_TS#1 R213 *short_4 PM_EXTTS#1 [13] FDI_TXN3 FDI_TX#[2] PEG_RX[5] H_VTTPWRGD AM15 PM_EXT_TS#[1] R211 10K_4 D18 FDI_TX#[3] PEG_RX[6] F32 VTTPWRGOOD +VTT FDI_TXN4 G21 D34 [9,16,20,21,22] PLTRST# R139 1.5K/F_4 CPU_PLTRST# AL14 FDI_TXN5 FDI_TX#[4] PEG_RX[7] RSTIN# FDI_TXN6 E19 F21 FDI_TX#[5] Intel(R) FDI PEG_RX[8] F33 B33 PRDY# AT28 AP27 XDP_PREQ# TP88 PCI EXPRESS -- GRAPHICS FDI_TXN7 FDI_TX#[6] PEG_RX[9]