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5 4 3 2 1
D D
FOOSE 15" UMA Schematics Document
uFCPGA Mobile Penryn
C
www.kythuatvitinh.com
Intel Cantiga-GM + ICH9M
2008-06-04
C
REV : -1
B B
DY : Nopop Component
5761 : Use BCM5761E
5756 : Use BCM5756M
B_TPM : Use LOM TPM
C_TPM : Use China TPM
A A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Foose Intel
Size Document Number Rev
A3 SC
COVER PAGE
Date: Wednesday, June 04, 2008 Sheet 1 of 58
5 4 3 2 1
5 4 3 2 1
Foose Intel UMA Block Diagram CPU DC/DC
ISL6260
INPUTS OUTPUTS
Intel Mobile CPU
Project code : 91.4X801.001 +PWR_SRC VCC_CORE 43
44
D
Penryn (35W) Part Number : 48.4X802.011 SYSTEM DC/DC D
SN0608098
Thermal & Fan Clock Generator
Socket P 8,9 PCB Number : 07238 INPUTS OUTPUTS
EMC4002
36
SLG8LP554VTR
7
Revision : -1 +PWR_SRC
+3.3V_ALW
HOST BUS FSB 800 / 1066MHz +5V_ALW 45
S-Vedio CONN19
SYSTEM DC/DC
LVDS S-VIDEO TPS5117
LCD 19 CRT CONN18
Intel
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VGA VSW INPUTS OUTPUTS
DDRII Slot 0 DDRII 667/800 Channel A
Cantiga-GML 18
+PWR_SRC +1.05V_VCCP
667/800 16
46
AGTL+ CPU I/F DISPLAY PORT
DDR Memory I/F SYSTEM DC/DC
DDRII Slot 1 DDR II 667/800 Channel B External Graphics DISPLAY PORT L6935TR(LDO)
C
667/800 17 C
INPUTS OUTPUTS
10,11,12,13,14,15 Int Mic
PCMCIA +1.8V_SUS +1.5V_RUN
27 E Docking 46
DAI32
SYSTEM DC/DC
Level Azalia Codec MIC IN TPS5116
DMI Shift 11 HP1
INPUTS OUTPUTS
1394 Ricoh R5C847 IDT 92HD71B7
27 +PWR_SRC +1.8V_SUS
1394 OP AMP 47
USB2.0
Intel TPA6040 37 SYSTEM DC/DC
PCI
SD/SDIO/MMC 32 /MAX9789A33 TPS5116(LDO)
27
26 ICH9-M
INPUTS OUTPUTS
Mini-Card
USB 2.0/1.1 ports (12) HDA 2CH WWAN / WPAN +V_DDR_MCH_REF
SATA MDC MODEM25 RJ11 +1.8V_SUS
B
SPEAKER / Robson 30 +0.9V_DDR_VTT B
HDD SATA 25
PCI Express ports (6) 29 47
High Definition Audio SATA
SATA ATA 66/ 100 1/2 Mini-Card SYSTEM DC/DC
12.7mm ODD SATA PCIE(6) WLAN / UWB
EMC4002(LDO)
25
SATA (3) 30
LPC I/F INPUTS OUTPUTS
SPI SPI USB2.0 Left Side Top:
SPI FLASH 16Mb Charger USB x 1 +3.3V_RUN +2.5V_RUN
22
ACPI 1.1
USB2.0 Left Side Bottom: 36
PCI/PCI BRIDGE 31
LOM ESW USB Port x 1
TI CHARGER
China TPM BCM5756M/ FLASH Right Side:
BQ24745
ZTE,Jetway 21,22,23,24 BCM5761E 28 2Mb/8Mb 28 USB Port x 2 31
INPUTS OUTPUTS
(Optional) 29
+DC_IN
Finger printer +VCHGR
+PWR_SRC
LPC RJ45/RJ11
29 (Optional) 20 42
A
WIFI A
On/Off 35
Digitally signed by dd
Wistron Corporation
Serial DN:88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F,
cn=dd, o=dd, ou=dd,
Taipei Hsien 221, Taiwan, R.O.C.
TouchPad BC EC Port 35
KSI/KSO MEC 5035
BC
SIO Expander Title [email protected],
Int KB ECE1077 31 PS2
ECE 5028 35 Size Document Number
c=US
Foose Intel Rev
34 A3 Date: 2009.12.04 19:30:07
BLOCK DIAGRAM SC
5 4 3 2
Date: Monday, June 02, 2008
+07'00' Sheet
1
2 of 58
5 4 3 2 1
Regulator
ADAPTER
SI3457BDV
GFX_PWR_SRC
D
19 LDO D
ISL6260C 43 +VCC_CORE43 Switch
BATTERY +PWR_SRC
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+3V_ALW_245
TPS51117 TPS51116
46 47
CHARGER SN0608098 +5V_ALW_245
BQ24745
C C
+15V_ALW 45
+1.05V_VCCP
46 +0.9V_DDR_VTT 49 +1.8V_SUS47
L6935TR
46
+5V_ALW +3.3V_ALW
46 46
+1.5V_RUN 46
B B
SI3456BDV SI4800BDY SI4800BDY SI4800BDY SI3456BDV SI3456BDV SI3456BDV
40 40 40 40 40 40 40
+5V_HDD +5V_MOD +5V_RUN +3.3V_RUN 40 +3.3V_LAN 40 +3.3V_SUS 40 +3.3V_ALW_ICH 40
40 40 40
MMBT35200MT1G MMJT9435T1G
A EMC4002 36
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
+2.5V_RUN 36 +2.5V_ROM 36 +1.2V_ROM 36
Size Document Number
Foose Intel Rev
Custom SC
Power Block Diagram
Date: Friday, May 30, 2008 Sheet 3 of 58
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
+3.3V_ALW_ICH
2.2K 2.2K
2.2K 2.2K
Device Adress: A0/A4
G16 ICH_SMBCLK 2N7002 MEM_SMBCLK
A13 ICH_SMBDATA MEM_SMBDATA DIMM1 page 16
2N7002
+3.3V_ALW_ICH +3.3V_LAN
ICH9M
D C17 2.2K D
AMT_SMBCLK DIMM2
2.2K 2.2K page 17
B18 2N7002 2N7002
AMT_SMBDAT
2N7002 LAN_SMBDATA
2.2K
+3.3V_ALW BCM5761E/BCM5756M
2N7002 LAN_SMBCLK
2.2K 2.2K
94 LOM_WLAN_SMBCLK +3.3V_ALW +3.3V_ALW
93 LOM_WLAN_SMBDAT
8.2K 8.2K 10K
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Device Adress: C4/72/70/48
3 DOCK_SMB_ALERT# 133
5 DOCK_SMB_DAT 129
DOCK
6 DOCK_SMB_CLK 127 page 38
C
8.2K C
+3.3V_ALW
7 LCD_SMBDAT 11
+3.3V_WLAN
8.2K LVDS Connector
8 LCD_SMBCLK 12 page 19
Device Adress: 58/20-22
2.2K
2.2K
98 SMBUS_WIRELESS_CLK 2N7002 WLAN_SMBCLK 30
97 SMBUS_WIRELESS_DAT WLAN_SMBDATA 32 WLAN page 30
2N7002
2.2K
MEC5035 2.2K +3.3V_RUN
2N7002
2.2K MINI_SMBCLK 30
page 30
+3.3V_ALW 2N7002 MINI_SMBDAT 32 WWAN
2.2K
+3.3V_ALW +3.3V_RUN
B B
2.2K 2.2K
2.2K 2.2K
12
CKG_SMBDAT 2N7002 CLK_SDATA 17
13 CKG_SMBCLK CLK_SCLK 16 ICS9LPR390 page 7
2N7002
10 28
BQ24745RHDR page 32
9 27 SSM2602
page 44
+3.3V_ALW BAV99
BAV99
2.2K 2.2K
A 111 100 A
PBAT_SMBDAT 6
100 page 41
112 PBAT_SMBCLK 7 Battery Connector
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Foose Intel
Size Document Number Rev
A2 SC
SMBus Block Diagram
Date: Friday, May 30, 2008 Sheet 4 of 58
5 4 3 2 1
5 4 3 2 1
PCIE Routing
LANE1 MiniCard WWAN
INTEL ICH9-M STRAP PIN LANE2 MiniCard WLAN
USB TABLE
LANE3 No use USB
Signal Usage/When Sampled Comment
LANE4 No use Pair Device
HDA_SDOUT XOR Chain Entrance/ Allows entrance to XOR Chain testing when TP3 LANE5 GIGA LAN 0 Charge USB
PCIE Port Config 1 bit1, pulled low at rising edge of PWROK. (LEFT SIDE TOP)
Rising Edge of PWROK When TP3 not pulled low at rising edge of PWROK, LANE6 No use 1
D
sets bit 1 of RPC.PC (Chipset Config Registers:
USB1(LEFT SIDE BOTTOM) D
2
Offset224h).This signal has a weak internal
pull-down.
SATA Routing 3
USB2(RIGHT SIDE TOP)
SATA0 HDD USB3(RIGHT SIDE BOTTOM)
HDA_SYNC PCIE Port Config 1 bit0, This signal has a weak internal pull-down. SATA1 ODD 4 WLAN
Rising Edge of PWROK. Sets bit 0 of RPC.PC (Chipset Config Registers:
Offset 224h) XOR Chain Entrance Strap SATA4 No use 5 WWAN/ WPAN
ICH_RSVD tp3AZ_DOUT_ICH Description SATA5 Dock eSATA 6 Reserve
GNT2# / PCIE Port Config 2 bit0, This signal has a weak internal pull-up.
GPIO53 Rising Edge of PWROK. Sets bit 2 of RPC.PC2 (Chipset Config 0 0 RSVD 7 Card Bus/Express Card
Registers:Offset 0224h) when sampled low. 0 1 Enter XOR Chain
Normal Operation(default)
PCI ROUTING 8 DOCK1
This signal has a weak internal pull-down. 1 0 IDSEL INT REQ GNT 9 DOCK2
GPIO20 Reserved NOTE: This signal should not be pulled high
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1 1 Set PCIE port cofig bit1 B 10 Biometric
Tying this strap low configures DMI for ESI 1394/
compatible operation. This signal has a weak AD17 1 C 1 11 BCM5761E
GNT1#/ ESI Strap, MediaCard D
internal pull-up. NOTE: ESI compatible mode
GPIO51 Rising Edge of PWROK. is for server platforms only. This signal should
not be pulled low for desktop and mobile. A16 swap override strap
The signal has a weak internal pull-up. If the
GNT3# /
GPIO55
Top-Block Swap Override.
Rising Edge of PWROK.
signal is sampled low, this indicates that the PCI_GNT#3 low = A16 swap override enable ICH9-M INTEGRATED PULL-UPS and PULL-DOWNS
C system is strapped to the "top-block swap" high = default C
mode (IntelR ICH9 inverts A16 for all cycles SIGNAL Resistor Type/Value
targeting BIOS space). The status of this strap
is readable via the Top Swap bit (Chipset Config BOOT BIOS Strap CL_CLK[1:0] PULL-UP 20K
Registers:Offset 3414h:bit 0). Note that software PCI_GNT#0 SPI_CS#1 BOOT BIOS Location
will not be able to clear the Top-Swap bit until
CL_DATA[1:0] PULL-UP 20K
the system is rebooted without GNT3# being CL_RST0# PULL-UP 10K
pulled down 0 1 SPI
DPRSLPVR/GPIO16 PULL-DOWN 20K
GNT0# Boot BIOS Destination This field determines the destination of accesses 1 0 PCI HDA_BIT_CLK PULL-DOWN 20K
SPI_CS1# Selection. to the BIOS memory range. Signals have weak
Rising Edge of PWROK. internal pull-ups. Also controllable via Boot HDA_DOCK_EN#/GPIO33 PULL-UP 20K
BIOS Destination bit (Chipset Config Registers:
1 1 LPC(Default)
HDA_RST# PULL-DOWN 20K
Offset 3410h:bit 11).This strap is used in
conjunction with Boot BIOS HDA_SDIN[3:0] PULL-DOWN 20K
Destination Selection 0 strap. Enable VccSus1_05,VccSus1_5,VccCL1_5 HDA_SDOUT PULL-DOWN 20K
SATALED# PCIE LAN REVERSAL.Rising Signal has weak internal pull-up.Sets bit 27 of HDA_SYNC PULL-DOWN 20K
Edge of PWROK. MPC.LR (Device 28: Function 0: Offset D8) SM_INTVRMEN High=Enable Low=Disable
GNT[3:0] PULL-UP 20K
The signal has a weak internal pull-down. If the
signal is sampled high, this indicates that the integrated VccLan1_05VccCL1_05 GPIO[20] PULL-DOWN 20K
SPKR No Reboot. system is strapped to the "No Reboot" mode
(ICH9 will disable the TCO Timer system
GPIO[49] PULL-UP 20K
B Rising Edge of PWROK. LAN100_SLP High=Enable Low=Disable B
reboot feature). The status of this strap is LAD[3:0]#/FHW[3:0]# PULL-UP 20K
readable via the NO REBOOT
bit (Chipset Config Registers:Offset 3410h:bit 5). LAN_RXD[2:0] PULL-UP 20K
LDRQ[0] PULL-UP 20K
See IntelR ICH9 Family XOR Chains In-Circuit
TP3 XOR Chain Entrance. Tester Package for functionality information. No Reboot Strap LDRQ[1]/GPIO23 PULL-UP 20K
Rising Edge of PWROK. This signal has a weak internal pull-up. NOTE:
This signal should not be pulled low unless
PME# PULL-UP 20K
SPKR LOW = Defaule
using XOR Chain testing. PWRBTN# PULL-UP 20K
High=No Reboot
SATALED# PULL-UP 15K
GPIO33 / Flash Descriptor Security This signal has a weak internal pull-up resistor.
HDA_DOCK_EN# Override Strap If sampled low, the Flash Descriptor Security SPI_CS1# PULL-UP 20K
Rising Edge of PWROK. will be overridden. If high, the security
measures defined in the Flash Descriptor will
SPI_MOSI PULL-DOWN 20K
be in effect.NOTE: This strap should only be SPI_MISO PULL-UP 20K
enabled in manufacturing environments.
SPKR PULL-DOWN 20K
The signal is required to be low for desktop TACH_[3:0] PULL-UP 20K
GPIO49 DMI Termination Voltage applications and required to be high for mobile
Rising Edge of PWROK. applications. TP[3] PULL-UP 20K
USB[11:0][P,N] PULL-DOWN 15K
This signal has a weak internal pull-down resistor.
A SPI_MOSI Integrated TPM Enable When the signal is sampled low the Integrated TPM A
Rising Edge of PWROK. will be disabled. When the signal is sampled high,
the MCH TPM enable strap is sampled low and the
TPM Disable bit is clear, the Integrated TPM will Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
be enabled.NOTE: This signal is required to be Taipei Hsien 221, Taiwan, R.O.C.
floating or pulled low for desktop applications.
Title
Size Document Number
Foose Intel Rev
A3 SC
Table of Content
Date: Friday, May 30, 2008 Sheet 5 of 58
5 4 3 2 1
5 4 3 2 1
CPU ITP Connector
D D
TCK(PIN 5)
TCK(PIN AC5)
FBO(PIN 11)
www.kythuatvitinh.com +3.3V_ALW_ICH
1
+1.05V_VCCP
SC-20080327
SC-20080327
1
1
1
1
1
C C