Text preview for : Compal_LA-7012P.pdf part of Compal Compal LA-7012P Compal Compal_LA-7012P.pdf
Back to : Compal_LA-7012P.pdf | Home
A B C D E
ZZZ1 ZZZ2 ZZZ3 ZZZ4 ZZZ5
PCB LA-7012P LS-7012P LS-7013P LS-7014P
15"DAZ@ 15"DA@ 15"DA@ 15"DA@ 15"DA@
1 1
Compal Confidential
Schematics Document
2 2
PAW20
Montevina
3
with Intel Cantiga + ICH9 core logic 3
REV:1.0A
2010-12-24
4 4
Security Classification Compal Secret Data Compal Electronics,Ltd.
Issued Date 2010/09/10 Deciphered Date 2010/08/19 Title
Cover Sheet
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA7012P
Date: Friday, December 24, 2010 Sheet 1 of 41
A B C D E
A B C D E
Compal confidential
File Name : For 14" For 15"
Clock Generator LS-7011P 4PIN PWR/B LS-7012P 8PIN PWR/B
SLG8SP556VTR Mobile Penryn LS7013P Audio/B LS7013P Audio/B
LS7014P Touch/B LS7014P Touch/B
page16
uPGA-478 CPU
1 1
page4,5,6
H_A#(3..35) FSB
H_D#(0..63) 667/800MHz
CRT Connector
page21
Intel Cantiga GMCH DDR3-SO-DIMM X2
GM45 BANK 0, 1, 2, 3 page 14,15
LVDS Dual Channel
Connector page22 uFCBGA 1329 DDR3-667/800(1.5V) up to 4G
page 7,8,9,10,11,12,13
DMI 4 C-Link 2Channel Speaker
page26
2 2
AZALIA Audio Codec Analog MIC_Int
page26
CONEXTAN
CX20671 page26
Wire Less Mini
card Slot 1 6*PCI-E BUS Intel ICH9-M 14*USB2.0 CMOS Camera
page23
page22
SPI ROM 6*SATA serial BlueTooth CONN
page 17,18,19,20 page30
BIOS
USB CONN X1(Right)
page29
LPC BUS
3
USB PORT X1(Left) 3
page29
AR8151/8152 EC USB PORT X1(Left)
ENE KB926 E0
page29
10/100/Giga LAN page27 Audio Jack SB CONN
page24
HP X 1+
MIC_Ext X1 page30
Card Reader RTS5139
RJ45 CONN Int.KBD
page25 page32
SPI ROM
BIOS page28 SATA HDD CONN
page28
4 Touch Pad SATA ODD CONN 4
page32
page32
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/09/10 Deciphered Date 2010/08/19 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MB Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA7012P
Date: Friday, December 24, 2010 Sheet 2 of 41
A B C D E
A B C D E
DDR3 Voltage Rails
elbaT lortnoC SUBMS
ECRUOS TTAB NALW 9HCI lmrehT
+5VS NAWW PIHC KLC MMIDOS 629BK
+3VS 1KC_BMS_CE
power
plane +1.5VS 1AD_BMS_CE 629BK
WLAV3+
V
WLAV3+
X X X X X X
+CPU_CORE 2KC_BMS_CE
1
+5VALW +1.5V +VGA_CORE 2AD_BMS_CE 629BK
WLAV3+
X X X X X X SV+
V3 1
+B +1.8VS KLCBMS_HCI
+3VALW ATADBMS_HCI HCI
WLAV3+
X X V
SV3+ SV+
V3 WLV 3+
AV X X
+0.75VS
+1.05VS
State
S0
O O O O
S3
GNISSERDDA SUBMS / C2I
O O O X
2
S5 S4/AC
O O
ECIVED XEH SSERDDA 2
X X
MMID-OS RDD 0A 00000101
S5 S4/ Battery only
O 0
X X X MMID-OS RDD
1
4A 00100101
).TXE( ROTARENEG KCOLC 2D 01001011
S5 S4/AC & Battery
don't exist X X X X
@ FUNCTION
Structure Description NON-USE
45@ 45 BOM
BT@ Blue Tooth function
CMOS@ CMOS CAMERA function
PCIE PORT LIST USB PORT LIST
3 PORT DEVICE PORT DEVICE 3
1 LAN 0 RIGHT SIDE
2 1 LEFT SIDE
3 WLAN 2 CMOS
4 3
5 4 CARD READER
6 5 WIRELESS
7 6 BT
8 7 USB PORT(ESATA)
8
9
10
11
12
13
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/09/10 Deciphered Date 2010/08/19 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MB Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA7012P
Date: Friday, December 24, 2010 Sheet 3 of 41
A B C D E
A B C D E
PVT ESD solution.
ME@ Please close to R715
JCPU1A
H_A#3 J4 H1 H_ADS#
<7> H_A#[3..16] A[3]# ADS# H_ADS# <7> +1.05VS +1.05VS
ADDR GROUP_0
ADDR GROUP_0
H_A#4 L5 E2 H_BNR#
H_A#5 A[4]# BNR# H_BPRI# H_BNR# <7>
L4 A[5]# BPRI# G5 H_BPRI# <7>
H_A#6 K5 H_IERR# R714 1 2 56_0402_5%
H_A#7 A[6]# H_DEFER#
M3 A[7]# DEFER# H5 H_DEFER# <7> 1
H_A#8 N2 F21 H_DRDY# H_PROCHOT# R715 1 2 68_0402_5%
H_A#9 A[8]# DRDY# H_DBSY# H_DRDY# <7>
J1 E1 C864
H_A#10 A[9]# DBSY# H_DBSY# <7>
N3 0.1U_0402_16V4Z
H_A#11 A[10]# H_BR0# 2
P5 F1 H_BR0# <7>
H_A#12 A[11]# BR0#
P2
A[12]#
CONTROL
1 H_A#13 H_IERR# 1
L2 D20
H_A#14 A[13]# IERR# H_INIT#
P4 B3 H_INIT# <18>
H_A#15 A[14]# INIT#
P1
H_A#16 A[15]# H_LOCK#
R1 H4 H_LOCK# <7>
H_ADSTB#0 A[16]# LOCK#
<7> H_ADSTB#0 M1
ADSTB[0]# H_RESET#
C1 H_RESET# <7>
H_REQ#0 RESET# H_RS#0
<7> H_REQ#0 K3 F3 H_RS#0 <7>
H_REQ#1 REQ[0]# RS[0]# H_RS#1
<7> H_REQ#1 H2 F4 H_RS#1 <7>
H_REQ#2 REQ[1]# RS[1]# H_RS#2
<7> H_REQ#2 K2 G3 H_RS#2 <7>
H_REQ#3 REQ[2]# RS[2]# H_TRDY#
<7> H_REQ#3 J3 G2 H_TRDY# <7>
H_REQ#4 REQ[3]# TRDY#
<7> H_REQ#4 L1
REQ[4]# H_HIT#
HIT# G6 H_HIT# <7>
H_A#17 Y2 E4 H_HITM#
H_A#18 A[17]# HITM# H_HITM# <7>
<7> H_A#[17..35] U5 A[18]#
H_A#19 R3 AD4
A[19]# BPM[0]#
ADDR GROUP_1
H_A#20 W6 AD3
H_A#21 A[20]# BPM[1]#
U4 A[21]# BPM[2]# AD1
H_A#22 Y5 AC4
A[22]# BPM[3]#
XDP/ITP SIGNALS
H_A#23 U1 AC2
H_A#24 A[23]# PRDY#
R4 A[24]# PREQ# AC1
H_A#25 T5 AC5 XDP_TCK
H_A#26 A[25]# TCK XDP_TDI
T3 A[26]# TDI AA6
H_A#27 W2 AB3 XDP_TDO
H_A#28 A[27]# TDO XDP_TMS
W5 A[28]# TMS AB5
H_A#29 Y4 AB6 XDP_TRST#
H_A#30 A[29]# TRST# XDP_DBRESET# +3VS +3VS
U2 A[30]# DBR# C20 XDP_DBRESET# <19>
H_A#31 V4
H_A#32 A[31]#
W3 A[32]#
1
H_A#33 AA4 THERMAL 1
H_A#34 A[33]# H_PROCHOT#
AB2 A[34]#
H_A#35 AA3 D21 C831 U1 R713
H_ADSTB#1 A[35]# PROCHOT# H_THERMDA 0.1U_0402_16V4Z 10K_0402_5%
<7> H_ADSTB#1 V1 ADSTB[1]# THERMDA A24
2
B25 H_THERMDC 2 2
2
H_A20M# THERMDC EC_SMB_CK2
<18> H_A20M# A6 A20M# ICH
ICH 1 VDD SMCLK 8 EC_SMB_CK2 <27>
H_FERR# A5 C7 H_THERMTRIP#
<18> H_FERR# H_IGNNE# FERR# THERMTRIP# H_THERMTRIP# <8,18> H_THERMDA EC_SMB_DA2
<18> H_IGNNE# C4 IGNNE# 2 DP SMDATA 7 EC_SMB_DA2 <27>
H_STPCLK# D5 1 2 H_THERMDC 3 6
<18> H_STPCLK# H_INTR STPCLK# DN ALERT#
C6 H CLK C832 2200P_0402_50V7K
<18> H_INTR LINT0
H_NMI B4 A22 CLK_CPU_BCLK THERM# 4 5
<18> H_NMI LINT1 BCLK[0] CLK_CPU_BCLK <16> THERM# GND
H_SMI# A3 A21 CLK_CPU_BCLK#
<18> H_SMI# SMI# BCLK[1] CLK_CPU_BCLK# <16>
M4 +3VS 1 2
RSVD[01] R716 10K_0402_5% EMC1402-1-ACZL-TR_MSOP8
N5
RSVD[02]
T2
RSVD[03] H_THERMDA, H_THERMDC routing together,
V3
RSVD pins on the CPU B2
RSVD[04] Trace width / Spacing = 10 / 10 mil Address:100_1100
RESERVED
RSVD[05]
should be left as NO D2
D22
RSVD[06]
RSVD[07]
CONNECT D3
F6
RSVD[08]
RSVD[09]
Penryn
10/01 Add for reduce noise 09/16 Add C834 For ESD
H_RESET#
XDP_DBRESET#
3 XDP Reserve for debug , Please close to CPU side C651
@
1
1
3
100P_0402_50V8J C834
+3VS 2 0.1U_0402_16V4Z
2
XDP_DBRESET# R718
1 2 @ 1K_0402_5%
+1.05VS
XDP_TDI
Place closely pin C1 Place closely pin C20
R8 1 2 54.9_0402_1%
XDP_TMS R9 1 2 54.9_0402_1%
XDP_TDO R10 1 2 @ 54.9_0402_1%
XDP_TRST# R11 1 2 54.9_0402_1%
XDP_TCK R12 1 2 54.9_0402_1%
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/09/10 Deciphered Date 2010/08/19 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Penryn(1/3)-AGTL+THM,FAN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA7012P
Date: Friday, December 24, 2010 Sheet 4 of 41
A B C D E
5 4 3 2 1
ME@
JCPU1D
A4 VSS[001] VSS[082] P6
ME@ A8 P21
JCPU1B VSS[002] VSS[083]
<7> H_D#[0..15] H_D#[32..47] <7> A11 VSS[003] VSS[084] P24
H_D#0 E22 Y22 H_D#32 A14 R2
H_D#1 D[0]# D[32]# H_D#33 VSS[004] VSS[085]
F24 D[1]# D[33]# AB24 A16 VSS[005] VSS[086] R5
H_D#2 E26 V24 H_D#34 A19 R22
D[2]# D[34]# VSS[006] VSS[087]
DATA GRP 0
H_D#3 G22 V26 H_D#35 A23 R25
DATA GRP 2
H_D#4 D[3]# D[35]# H_D#36 VSS[007] VSS[088]
F23 D[4]# D[36]# V23 AF2 VSS[008] VSS[089] T1
H_D#5 G25 T22 H_D#37 B6 T4
H_D#6 D[5]# D[37]# H_D#38 VSS[009] VSS[090]
E25 D[6]# D[38]# U25 B8 VSS[010] VSS[091] T23
H_D#7 E23 U23 H_D#39 B11 T26
H_D#8 D[7]# D[39]# H_D#40 VSS[011] VSS[092]
K24 D[8]# D[40]# Y25 B13 VSS[012] VSS[093] U3
H_D#9 G24 W22 H_D#41 B16 U6
D H_D#10 D[9]# D[41]# H_D#42 VSS[013] VSS[094] D
J24 D[10]# D[42]# Y23 B19 VSS[014] VSS[095] U21
H_D#11 J23 W24 H