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Layout Gerber-Out 0822-91
Title Page
MS-6702 VER:0E ATX Cover Sheet 1
1. Modify Circuit 6702-0A_0822-91.DSN 08/22/91-> Layout Finished ( Gerber-Out Version ).
Release ES-BOM
Block Diagram 2 1. Modify Circuit 6702-0A_0827A-91.DSN 08/27/91-> Release NEW BOM of ES-BOM for Standard
*AMD PGA 754 K8-Processor (DDR 400) GPIO SPEC 3
( 6702-A20 ).
2. Modify Circuit 6702-0A_1001-91.DSN 10/01/91-> After Pilot-Run ( Didn't release ECR ) .
D *VIA K8T400M / VT8237 Chipset AMD K8 -> 754 PGA Socket 4,5,6
D
(AGP 8X / VLink 8X) Modify MS6702/VER:0B 10/04/2002
Clock Synthesizer & MS1 7 1. Modify Circuit 6702-0B_1108-91.DSN 11/08/91=> VER:0A -> OB : Modify H/W issue & K8-CPU
*Winbond 83697HF-VF LPC I/O & NB-K8T400M & Change H/W Audio to S/W Audio ( Gerber-Out Version ) .
System Memory DDR DIMM 1 & 2 & 3 8,9 2. Creat new BOM for MS6702/VER:0B , 6702-0B_1108A-91.dsn 11/08/91 .
*VT6306 1394a OHCI Link Layer Controller 3. Modify BOM for MS6702/VER:0B , 6702-0B_1118-91.dsn 11/18/91 .
DDR Terminations R & C 10
*PDC20378 Serial ATA Controller DDR Damping R & Bypass Cap. 11 Modify MS6702/VER:0C 1/03/2003
*RTL 8110S Giga/ 8100C100/10 Bit LAN NB VIA K8T400M/VER:0.4 (HT) 12,13,14
1. Modify Circuit 6702-0C FROM 67020B.
2.GERBER OUT 1/29/2003.
Support
K8 Vcore 15
*USB 2.0 support (integrated into VT8237)
*Vcore Jumpless support AGP SLOT 8X 16
*ALC650/ALC655 6 channel S/W Audio VT8237 17,18,19
PCI Connectors * 5 20,21,22
ALC650/ALC655 6 channel S/W Audio 23
C C
*DDR DIMM * 3 Serial ATA Controller PDC20378 24,25
*AGP SLOT * 1 ( 8X ) IDE ATA 66/100 Connectors * 2 26
*PCI SLOT * 5 1394 Controller VT6306 27
Front USB Port *2 28
Rear USB Port *2 29
LPC I/O W83697HF & Floppy 30
Hardware monitor & FAN 31
BIOS ROM & VCORE ADJUSTING 32
Keyboard/Mouse Connectors 33
B
LPT/COM Port 34 B
Giga-Bit LAN RTL8110S/RTL8100C 35
ACPI Power CONTROLLER (MS-6) 36
SYSTEM VOLTAGE REGULATOR 37
Front Panel & POWER OK CIRCUIT 38
Decoupling Cap. 39
Power Sequence 40
History 41
OPTION PARTS 42
A A
Micro Star Restricted Secret
MS6702-0E Title
Cover Sheet
Rev
0E
Document Number MS-6702
MICRO-STAR INT'L Last Revision Date:
CO.,LTD.
No. 69, Li-De St, Jung-He City, Wednesday, June 25, 2003
Taipei Hsien, Taiwan Sheet
http://www.msi.com.tw 1 of 42
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Block Diagram
DDR400
AMD K8 Socket 754
D D
HT DDR * 3
A
G
P
AGP 8X /Fast Write
VIA
C
K8T400M C
S
L
O
5 PCI Slots
T
IDE Slot
VLINK ==>ATA66,100,133 *2
Dual ATA
PCI-33 100/133
VT8237
B B
1394 1394 Host
Front-Port *3 Controller LPC BUS
VT6306
AC97
AC97 => S/W Audio
ALC655 / 6 channel
SUPER I/O ROM
W83697HF
SERIAL ATA *2 USB
Serial ATA & IDE
RAID Controller
PDC20378
X BUS
A A
Serial Port *2 , Giga Bit LAN Dual USB 1.1 OHCI
IDE Port *1 RTL8110S/8100C /2.0 EHCI 8 Ports
==> Front-Port *6 ,
Back-Port *2 Micro Star Restricted Secret
Title Rev
Block Diagram
0E
Document Number MS-6702
MICRO-STAR INT'L Last Revision Date:
CO.,LTD.
No. 69, Li-De St, Jung-He City, Wednesday, June 25, 2003
Taipei Hsien, Taiwan Sheet
http://www.msi.com.tw 2 of 42
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GPIO FUNCTION PCI Routing
DEVICES INT# IDSEL REQ#/GNT# CLOCK
VT8237 GPIO Function Define
INT#A PREQ#6
PIN NAME Function define PIN NAME Function define PCI SLOT 1 INT#B AD16 PCICLK1
D INT#C PGNT#6 D
INT#D
GPO0 (VSUS33) VCORE_ADJ GPI0 NA (Exteranl Pull up to VBAT)
INT#B PREQ#3
GPO1/SUSA#(VSUS33) NA GPI1 ATADET0=>Detect IDE1 ATA100/66 PCI SLOT 2 INT#C AD17 PCICLK2
INT#D PGNT#3
INT#A
GPO2/SUSB#(VSUS33) SUSB# GPI2/EXTSMI# EXTSMI#
INT#C PREQ#4
GPO3/SUSST1#(VSUS33) SUSST# GPI3/RING# RING# PCI SLOT 3 INT#D AD18 PCICLK3
INT#A PGNT#4
INT#B
GPO4/SUSCLK(VSUS33) NA (Exteranl Pull up to 3VDUAL) GPI4/LID# ATADET1=>Detect IDE2 ATA100/66
INT#D PREQ#7
GPO5/CPUSTP# NA (Exteranl Pull up to VCC3) GPI5/BATLOW# NA (Exteranl Pull up to 3VDUAL) PCI SLOT 4 INT#A AD19 PCICLK4
INT#B PGNT#7
INT#C
GPO6/PCISTP# NA (Exteranl Pull up to VCC3) GPI6/AGPBZ# POWERF3
INT#B PREQ#8
GPO7/SLP# LDTSTOP# GPI7/REQ#5 NA (Exteranl Pull up to 3VDUAL) PCI SLOT 5 INT#C AD21 PCICLK5
INT#D PGNT#8
INT#A
GPO8/GPI8/IPBIN0 NA GPI16/INTRUDER# NA (Exteranl Pull up to VBAT)
GPO9/GPI9/IPBIN1 NA GPI17/CPUMISS NA (Exteranl Pull up to 3VDUAL)
C C
GPO10/GPI10/IPBRDFR NA GPI18/AOLGP1/THRM# THRM#
GPO11/GPI11/IPBRDCK NA GPI19/IORDY NA (Exteranl Pull up to VCC3) Giga-Bit INT#A AD22 PREQ#1 GLAN_PCLK
LAN PGNT#1
GPO12/GPI12/INTE# S_VID0
S/IO GPIO Function Define PREQ#0 MS1_PCLK
GPO13/GPI13/INTF# S_VID1 MS1 #1
PIN NAME Function define PGNT#0
GPO14/GPI14/INTG# S_VID2
GPBX/GP13 LED#4
GPO15/GPI15/INTH# NA
GPAY/GP15 LED#2
SERIAL ATA INT#B AD24 ( PREQ#2 ) SATAPCLK
GPO16/SA16/STRAP LDT Freq Strapping Bit0 ( PGNT#2 )
GPAS1/GP10 LED1
GPO17/SA17/STRAP LDT Freq Strapping Bit1 1394 INT#D AD25 ( PREQ#5 ) 1394_PCLK
GPAS2/GP17 LED4 ( PGNT#5 )
GPO18/SA18/STRAP LDT Width (Low=8 Bit)
GPAX/GP12 LED#3
B GPO19/SA19/STRAP Fast Command (Low=Disable) B
GPBY/GP14 LED#1
GPO20/GPI20
/ACSDIN2/PCS0#/EI POWERF1
GPBS1/GP11 LED2
GPO21/GPI21/ACSDIN3
/PCS1#/SLPBTN# POWERF2
GPBS2/GP16 LED3
GPO22/GPI22/IOR# NA
GPO23/GPI23/DPSLP ROMLOCK
GPO24/GPI24/GPIOA NA
GPO25/GPI25/GPIOC NA
GPO26/GPI26/SMBDT2
(VSUS33) SMBDATA2/Slave SMBUS
GPO27/GPI27/SMBCK2
(VSUS33) SMBCLK2/Slave SMBUS
GPO28/GPI28/
VIDSEL NA
GPO29/GPI29/
A VRDSLP NA A
GPO30/GPI30/GPIOD NA
Micro Star Restricted Secret
GPO31/GPI31/GPIOE NA Title Rev
GPIO Spec. 0E
Document Number MS-6702
MICRO-STAR INT'L Last Revision Date:
CO.,LTD.
No. 69, Li-De St, Jung-He City, Wednesday, June 25, 2003
Taipei Hsien, Taiwan Sheet
http://www.msi.com.tw 3 of 42
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C1561 VDD_12_A
VREF routed as 40~50 mils trace wide ,
Space>25 mils
X102P C171 C160 C162 C169 C230 C237 C161
U7B VTT_DDR_SUS
C62 X_0.22u 0.22u 0.22u X_0.22u 0.22u 0.22u 0.22u
AE13 VTT_SENSE VTT_A4 D17
102P A18
VTT_A1
8,9 DDR_VREF VTT_A2 B17
D
AG12 MEMVREF1 VTT_A3 C17 D
VTT_B1 AF16
R120 10RST MEMZN D14 AG16
VDD_25_SUS MEMZN VTT_B2
R126 10RST MEMZP C14 AH16
MEMZP VTT_B3
VTT_B4 AJ17
U7A
Place near CPU in 1" , AG10 VDD_12_A N12-7540010-A10
MEMRESET_L VLDT0
Routed => 5:10/Trace:Space , VLDT0 5
Same Length AE8 MCKE0
MEMCKEA MCKE0 8,9,10
AE7 MCKE1 D29 AH29
MEMCKEB MCKE1 8,9,10 VLDT0_A6 VLDT0_B6
MD63 A16 D27 AH27
11 MD[63..0] MEMDATA63 VLDT0_A5 VLDT0_B5
MD62 B15 D10 MEMCLK_H7 MEMCLK_H[7..0] D25 AG28 C69
MEMDATA62 MEMCLK_H7 MEMCLK_H[7..0] 8,9,10 VLDT0_A4 VLDT0_B4
MD61 A12 C10 MEMCLK_L7 MEMCLK_L[7..0] C28 AG26
MEMDATA61 MEMCLK_L7 MEMCLK_L[7..0] 8,9,10 VLDT0_A3 VLDT0_B3
MD60 B11 E12 MEMCLK_H6 C26 AF29 4.7u/0805
MD59 MEMDATA60 MEMCLK_H6 MEMCLK_L6 VLDT0_A2 VLDT0_B2
A17 MEMDATA59 MEMCLK_L6 E11 B29 VLDT0_A1 VLDT0_B1 AE28
MD58 A15 AF8 MEMCLK_H5 B27 AF25
MD57 MEMDATA58 MEMCLK_H5 MEMCLK_L5 VLDT0_A0 VLDT0_B0
C13 MEMDATA57 MEMCLK_L5 AG8
MD56 A11 AF10 MEMCLK_H4 CADIP15 T25 N26 CADOP15
MEMDATA56 MEMCLK_H4 12 CADIP[0..15] CADIN15 L0_CADIN_H15 L0_CADOUT_H15 CADON15 CADOP[0..15] 12
MD55 A10 AE10 MEMCLK_L4 R25 N27
MEMDATA55 MEMCLK_L4 12 CADIN[0..15] L0_CADIN_L15 L0_CADOUT_L15 CADON[0..15] 12
MD54 B9 V3 CADIP14 U27 L25 CADOP14
MD53 MEMDATA54 MEMCLK_H3 CADIN14 L0_CADIN_H14 L0_CADOUT_H14 CADON14
C7 MEMDATA53 MEMCLK_L3 V4 U26 L0_CADIN_L14 L0_CADOUT_L14 M25
MD52 A6 K5 CADIP13 V25 L26 CADOP13
MD51 MEMDATA52 MEMCLK_H2 CADIN13 L0_CADIN_H13 L0_CADOUT_H13 CADON13
C11 MEMDATA51 MEMCLK_L2 K4 U25 L0_CADIN_L13 L0_CADOUT_L13 L27
MD50 A9 MEMDATA50 MEMCLK_H1 R5 MEMCLK_H1 CADIP12 W27 L0_CADIN_H12 L0_CADOUT_H12 J25 CADOP12
MD49 A5 MEMDATA49 MEMCLK_L1 P5 MEMCLK_L1 CADIN12 W26 L0_CADIN_L12 L0_CADOUT_L12 K25 CADON12
MD48 B5 P3 MEMCLK_H0 CADIP11 AA27 G25 CADOP11
MD47 MEMDATA48 MEMCLK_H0 CADIN11 L0_CADIN_H11 L0_CADOUT_H11 CADON11
C5 MEMDATA47 MEMCLK_L0 P4 MEMCLK_L0 AA26 L0_CADIN_L11 L0_CADOUT_L11 H25
MD46 A4 CADIP10 AB25 G26 CADOP10
MD45 MEMDATA46 CADIN10 L0_CADIN_H10 L0_CADOUT_H10 CADON10
E2 MEMDATA45 MEMCS_L7 D8 AA25 L0_CADIN_L10 L0_CADOUT_L10 G27
MD44 E1 C8 CADIP9 AC27 E25 CADOP9
MD43 MEMDATA44 MEMCS_L6 -MCS5 CADIN9 L0_CADIN_H9 L0_CADOUT_H9 CADON9
C A3 MEMDATA43 MEMCS_L5 E8 -MCS5 9,10 AC26 L0_CADIN_L9 L0_CADOUT_L9 F25 C
MD42 B3 E7 -MCS4 CADIP8 AD25 E26 CADOP8
MEMDATA42 MEMCS_L4 -MCS4 9,10 CADIN8 L0_CADIN_H8 L0_CADOUT_H8 CADON8
MD41 E3 D6 -MCS3 AC25 E27
MD40 MEMDATA41 MEMCS_L3 -MCS2 CADIP7 L0_CADIN_L8 L0_CADOUT_L8 CADOP7
F1 MEMDATA40 MEMCS_L2 E6 T27 L0_CADIN_H7 L0_CADOUT_H7 N29
MD39 G2 C4 -MCS1 CADIN7 T28 P29 CADON7
MD38 MEMDATA39 MEMCS_L1 -MCS0 -MCS[3..0] CADIP6 L0_CADIN_L7 L0_CADOUT_L7 CADOP6
G1 MEMDATA38 MEMCS_L0 E5 -MCS[3..0] 8,10 V29 L0_CADIN_H6 L0_CADOUT_H6 M28
MD37 L3 CADIN6 U29 M27 CADON6
MD36 MEMDATA37 -MSRASA CADIP5 L0_CADIN_L6 L0_CADOUT_L6 CADOP5
L1 MEMDATA36 MEMRASA_L H5 -MSRASA 8,10 V27 L0_CADIN_H5 L0_CADOUT_H5 L29
MD35 G3 D4 -MSCASA CADIN5 V28 M29 CADON5
MEMDATA35 MEMCASA_L -MSCASA 8,10 L0_CADIN_L5 L0_CADOUT_L5
MD34 J2 G5 CADIP4 Y29 K28 CADOP4
MEMDATA34 MEMWEA_L -MSWEA 8,10 CADIN4 L0_CADIN_H4 L0_CADOUT_H4 CADON4
MD33 L2 W29 K27
MD32 MEMDATA33 CADIP3 L0_CADIN_L4 L0_CADOUT_L4 CADOP3
M1 MEMDATA32 MEMBANKA1 K3 MEMBANKA1 8,10 AB29 L0_CADIN_H3 L0_CADOUT_H3 H28
MD31 W1 H3 CADIN3 AA29 H27 CADON3
MEMDATA31 MEMBANKA0 MEMBANKA0 8,10 L0_CADIN_L3 L0_CADOUT_L3
MD30 W3 CADIP2 AB27 G29 CADOP2
MD29 MEMDATA30 CADIN2 L0_CADIN_H2 L0_CADOUT_H2 CADON2
AC1 MEMDATA29 RSVD_MEMADDA15 E13 AB28 L0_CADIN_L2 L0_CADOUT_L2 H29
MD28 AC3 C12 CADIP1 AD29 F28 CADOP1
MD27 MEMDATA28 RSVD_MEMADDA14 MAA13 CADIN1 L0_CADIN_H1 L0_CADOUT_H1 CADON1
W2 MEMDATA27 MEMADDA13 E10 MAA[13..0] 8,10 AC29 L0_CADIN_L1 L0_CADOUT_L1 F27
MD26 Y1 AE6 MAA12 CADIP0 AD27 E29 CADOP0
MD25 MEMDATA26 MEMADDA12 MAA11 CADIN0 L0_CADIN_H0 L0_CADOUT_H0 CADON0
AC2 MEMDATA25 MEMADDA11 AF3 AD28 L0_CADIN_L0 L0_CADOUT_L0 F29
MD24 AD1 M5 MAA10
MD23 MEMDATA24 MEMADDA10 MAA9 CLKOP1
AE1 MEMDATA23 MEMADDA9 AE5 12 CLKIP1 Y25 L0_CLKIN_H1 L0_CLKOUT_H1 J26 CLKOP1 12
MD22 AE3 AB5 MAA8 W25 J27 CLKON1
MEMDATA22 MEMADDA8 MAA7 12 CLKIN1 L0_CLKIN_L1 L0_CLKOUT_L1 CLKON1 12
MD21 AG3 AD3 Y27 J29 CLKOP0
MEMDATA21 MEMADDA7 MAA6 12 CLKIP0 L0_CLKIN_H0 L0_CLKOUT_H0 CLKOP0 12
MD20 AJ4 Y5 Y28 K29 CLKON0
MEMDATA20 MEMADDA6 MAA5 12 CLKIN0 L0_CLKIN_L0 L0_CLKOUT_L0 CLKON0 12
MD19 AE2 AB4
MD18 MEMDATA19 MEMADDA5 MAA4 VLDT0 R86 49.9RST CTLIP1
AF1 MEMDATA18 MEMADDA4 Y3 R27 L0_CTLIN_H1 L0_CTLOUT_H1 N25
MD17 AH3 V5 MAA3 R80 49.9RST CTLIN1 R26 P25
MD16 MEMDATA17 MEMADDA3 MAA2 L0_CTLIN_L1 L0_CTLOUT_L1 CTLOP0
AJ3 MEMDATA16 MEMADDA2 T5 12 CTLIP0 T29 L0_CTLIN_H0 L0_CTLOUT_H0 P28 CTLOP0 12
MD15 AJ5 T3 MAA1 R29 P27 CTLON0
MEMDATA15 MEMADDA1 MAA0 12 CTLIN0 L0_CTLIN_L0 L0_CTLOUT_L0 CTLON0 12
MD14 AJ6 N5
B
MD13 MEMDATA14 MEMADDA0 B
AJ7 MEMDATA13 HYPER TRANSPORT - LINK0
MD12 AH9 H4
MEMDATA12 MEMRASB_L -MSRASB 8,9,10
MD11 AG5 F5
MEMDATA11 MEMCASB_L -MSCASB 8,9,10
MD10 AH5 F4
MEMDATA10 MEMWEB_L -MSWEB 8,9,10
MD9 AJ9
MD8 MEMDATA9
AJ10 MEMDATA8 MEMBANKB1 L5 MEMBAKB1 8,9,10
MD7 AH11 J5
MEMDATA7 MEMBANKB0 MEMBAKB0 8,9,10
MD6 AJ11
MD5 MEMDATA6
AH15 MEMDATA5 RSVD_MEMADDB15 E14
MD4 AJ15 D12
MD3 MEMDATA4 RSVD_MEMADDB14 MAB13
AG11 MEMDATA3 MEMADDB13 E9 MAB[13..0] 8,9,10
MD2 AJ12 AF6 MAB12
MD1 MEMDATA2 MEMADDB12 MAB11
AJ14 MEMDATA1 MEMADDB11 AF4
MD0 AJ16 M4 MAB10
MEMDATA0 MEMADDB10 MAB9
11 DM[8..0] MEMADDB9 AD5
DM8 R1 AC5 MAB8
DM7 MEMDQS17 MEMADDB8 MAB7
A13 MEMDQS16 MEMADDB7 AD4
DM6 A7 AA5 MAB6
DM5 MEMDQS15 MEMADDB6 MAB5
C2 MEMDQS14 MEMADDB5 AB3
DM4 H1 Y4 MAB4
DM3 MEMDQS13 MEMADDB4 MAB3
AA1 MEMDQS12 MEMADDB3 W5
DM2 AG1 U5 MAB2
DM1 MEMDQS11 MEMADDB2 MAB1
AH7 MEMDQS10 MEMADDB1 T4
DM0 AH13 M3 MAB0
-MDQS8 MEMDQS9 MEMADDB0
11 -MDQS[8..0] T1 MEMDQS8
-MDQS7 A14 N3 MEMCHECK7
MEMDQS7 MEMCHECK7 MEMCHECK6 MEMCHECK[7..0] 11
-MDQS6 A8 N1
-MDQS5 MEMDQS6 MEMCHECK6 MEMCHECK5
D1 MEMDQS5 MEMCHECK5 U3
-MDQS4 J1 V1 MEMCHECK4
-MDQS3 MEMDQS4 MEMCHECK4 MEMCHECK3
A AB1 MEMDQS3 MEMCHECK3 N2 A
-MDQS2 AJ2 P1 MEMCHECK2
-MDQS1 MEMDQS2 MEMCHECK2 MEMCHECK1
AJ8 MEMDQS1 MEMCHECK1 U1
-MDQS0 AJ13 U2 MEMCHECK0
MEMDQS0 MEMCHECK0
MEMORY INTERFACE
Micro Star Restricted Secret
Title Rev
K8 DDR & HT
Document Number 0E
MS-6702
MICRO-STAR INT'L Last Revision Date:
CO.,LTD. Wednesday, June 25, 2003
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan Sheet
http://www.msi.com.tw 4 of 42
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