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PWA FP381, PWB DY483,
JM7-INTEGRATED SCHEM UW474.
A
JM7 M/B PCB
VER : 1A A
POWER SYSTEM POWER
PG 44 Merom CLOCK
RESET CIRCUIT CK410M+LP
(478 Micro-FCPGA) REGULATOR PG 48
BATT +1.5V_RUN/+1.05V_VCCP CPU VR PG 51
PG 45 PG 3,4
SELECTOR
REGULATOR PG 49 PG 17
BATT (Symbol Rev.09) +1.8V_SUS/+1.25V_RUN DC/DC PG 52
PG 46 /+0.9V_DDR_VTT
AC/BATT CHARGER +3.3V_ALW/+5V_ALW/+15V_ALW
CONNECTOR
RUN POWER SW PG 53
PG 54 +3.3V_SUS/+5V_SUS
667/800 MHz FSB
+5V/+3.3V/+1.8V
LVDS
Panel Connector PG 24
Crestline SDVO SI1362
DDR2-SODIMM1 533/667 MHZ DDR II
B
1299 uFCBGA PG 18 B
PG 15,16 TVOUT
PG 5,6,7,8,9,10
VGA CRT CONN.
533/667 MHZ DDR II
DDR2-SODIMM2 PG 25
(Symbol Rev.09)
PG 15,16
USB2.0 (P0,P1) (EXT SIDE)
POWER USB & USB
USB2.0 (P2,P3) (EXT BACK)
IDE PG 33
Internal Media Bay DMI interface USB2.0 (P8)
33MHz PCI
CD-ROM PG 26 Q-SWITCH
USB1.0 SATA - HDD SATA PCIEx1 CARDBUS/1394 PG 42 DOCKING
PG 26 ICH8-M USB2.0 (P6)
SMART CARD OZ711EZ1TN CONNECTOR
USB2.0 (P4) PCIEx2
OZ77CR6LN 676 BGA PG 27
USB2.0 (P9)
PG 28 PG 43
IHDA PG 11,12,13,14 USB2.0 (P7) EXPRESS-CARD
C R5538 C
MINI-CARD PG 28
AUDIO/AMP MDC
(Symbol Rev.09) WLAN
PG 38,39 PG 30 PG 29
USB2.0 (P5) Biometric MINI-CARD
PG 35 WWAN
LPC PCIEx1
SPI PG 29
Bluetooth
S/PDIF Audio RJ11 Tip
for Dock Jacks for Dock Ring PG 35
PG 43 PG 39 PG 43 PG 30 SIO SIO
MEC5025 ECE5018 BCM5755M E-Switch RJ45/Magnetics
PI3L500
128KB Flash BC Expander /BCM5752 +3.3V_LAN
Keyboard ECE1077 BC TMKBC USB 2.0 Hub(4) PG 41
Controllor PG 40 PG 41
PG 34 128 Pins VTQFP 128 Pins VTQFP
DOCK LPC
PG 31 PG 32
D D
SPI PS/2
USER Keyboard Touchpad/ Serial Port IrDA FAN & THERMAL QUANTA
FLASH
INTERFACE Stick point EMC4001
Title
COMPUTER
PG 36 PG 36 PG 34 PG 35 PG 33 PG 35 PG 37 Schematic Block Diagram1
Size Document Number Rev
JM7 1A
Date: Monday, June 26, 2006 Sheet 1 of 57
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1 2 3 4 5 6 7 8
INDEX Power States
Control S3/ S4/ S5/
Pg# Description Power Rail S0/M0 S3/M1 S3/M1 S4/M1
Signal M-off M-off M-off
1 Schematic Block Diagram
2 Front Page +3.3V_ALW
3-4 Merom
+5V_ALW
5-10 Crestline
A 11-14 ICH8M +3.3V_LAN A
15-16 DDRII SO-DIMM(200P)
17 Clock Generator
18-23 VGA
24 LCD Conn. & SSP
+1.8V_SUS
25 CRT Conn
26 SATA & IDE Conn +0.9V_DDR_VTT
27 PCCARD/Conn & 1394
+5V_SUS
28 Express Card & Smart Card
29 Mini Card +3.3V_SUS
30 MDC Conn.
+5V_RUN
31 SIO (MEC5025)
32 SIO (MEC5018) +3.3V_RUN
33 SERIAL PORT & USB
+1.8V_RUN
34 Flash ROM, RTC & ECE1077
B 35 TP,BT & FIR +1.25V_RUN B
36 Switch,Keyboard & LED
+1.5V_RUN
37 FAN & Thermal
38-39 Audio CODEC(STAC9205)/Phone Jack +1.05V_VCCP
40-41 LOM (Nineveh)/Switch
VCC_VCRE
42-43 Docking Conn/Q-Switch
44 System Reset Circuit +LCDVCC
45-46 Battery Selector & Charger
+5V_MOD
47 DDR2_1.8VSUS, 0.9V
48 1.5VSUS,1.05V(VTT)
49 VGA DC/DC,1.25V,1.05V
50 CPU_MAX8786(3phase)
51 D/D Power
52 RUN Power Switch
53 DCIN,Batt
C C
54 PAD& SCREW
55 EMI CAP
56 SMBUS BLOCK
D D
QUANTA
Title
COMPUTER
Index & Power Status
Size Document Number Rev
JM7 1A
Date: Monday, June 26, 2006 Sheet 2 of 57
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
H_A#[3..16] U6A H_D#[0..63] U6B H_D#[0..63]
5 H_A#[3..16] 5 H_D#[0..63] H_D#[0..63] 5
H_A#3 J4 H1 H_D#0 E22 Y22 H_D#32
A[3]# ADS# H_ADS# 5 D[0]# D[32]#
H_A#4 L5 E2 H_D#1 F24 AB24 H_D#33
A[4]# BNR# H_BNR# 5 D[1]# D[33]#
H_A#5 L4 G5 H_D#2 E26 V24 H_D#34
A[5]# BPRI# H_BPRI# 5 D[2]# D[34]#
H_A#6 K5 H_D#3 G22 V26 H_D#35
H_A#7 A[6]# H_D#4 D[3]# D[35]# H_D#36
M3 A[7]# DEFER# H5 H_DEFER# 5 F23 D[4]# D[36]# V23
H_A#8 N2 F21 H_D#5 G25 T22 H_D#37
A[8]# DRDY# H_DRDY# 5 D[5]# D[37]#
H_A#9 J1 E1 H_D#6 E25 U25 H_D#38
A[9]# DBSY# H_DBSY# 5 D[6]# D[38]#
H_A#10 N3 +1.05V_VCCP H_D#7 E23 U23 H_D#39
A[10]# H_BR0# 5 D[7]# D[39]#
ADDR GROUP 0
ADDR GROUP 0
DATA GRP 0
DATA GRP 2
H_A#11 P5 F1 Layout Note: H_D#8 K24 Y25 H_D#40
H_A#12 A[11]# BR0# R352 56 H_D#9 D[8]# D[40]# H_D#41
P2 A[12]# Place R646 G24 D[9]# D[41]# W22
1
H_A#13 L2 D20 H_IERR# 1 2 H_D#10 J24 Y23 H_D#42
CONTROL
A A[13]# IERR# +1.05V_VCCP close to D[10]# D[42]# A
H_A#14 P4 B3 R356 H_D#11 J23 W24 H_D#43
A[14]# INIT# H_INIT# 11 D[11]# D[43]#
H_A#15 P1 A[15]#
51/F_NC CPU. H_D#12 H22 D[12]# D[44]# W25 H_D#44
H_A#16 R1 H4 H_D#13 F26 AA23 H_D#45
A[16]# LOCK# H_LOCK# 5 D[13]# D[45]#
M1 H_D#14 K22 AA24 H_D#46
5 H_ADSTB#0
2
H_REQ#[0..4] ADSTB[0]# H_RESET# H_D#15 D[14]# D[46]# H_D#47
5 H_REQ#[0..4] RESET# C1 H_RESET# 5 H23 D[15]# D[47]# AB25
H_REQ#0 K3 F3 J26 Y26
REQ[0]# RS[0]# H_RS#0 5 5 H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 5
H_REQ#1 H2 F4 H26 AA26
REQ[1]# RS[1]# H_RS#1 5 5 H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 5
H_REQ#2 K2 G3 H25 U22
REQ[2]# RS[2]# H_RS#2 5 5 H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 5
H_REQ#3 J3 G2
REQ[3]# TRDY# H_TRDY# 5 H_D#[0..63] H_D#[0..63]
H_REQ#4 L1
H_A#[17..35] REQ[4]# 5 H_D#[0..63] H_D#[0..63] 5
G6 H_D#16 N22 AE24 H_D#48
5 H_A#[17..35] HIT# H_HIT# 5 D[16]# D[48]#
H_A#17 Y2 E4 H_D#17 K25 AD24 H_D#49
A[17]# HITM# H_HITM# 5 D[17]# D[49]#
H_A#18 U5 H_D#18 P26 AA21 H_D#50
H_A#19 A[18]# ITP_BPM#0 H_D#19 D[18]# D[50]# H_D#51
R3 A[19]# BPM[0]# AD4 R23 D[19]# D[51]# AB22
H_A#20 W6 AD3 ITP_BPM#1 Layout Note: H_D#20 L23 AB21 H_D#52
A[20]# BPM[1]# D[20]# D[52]#
ADDR GROUP 1
H_A#21 U4 AD1 ITP_BPM#2 H_D#21 M24 AC26 H_D#53
XDP/ITP SIGNALS
H_A#22 A[21]# BPM[2]# ITP_BPM#3
Place voltage H_D#22 D[21]# D[53]# H_D#54
Y5 A[22]# BPM[3]# AC4 L22 D[22]# D[54]# AD20
divider within
DATA GRP 1
DATA GRP 3
H_A#23 U1 AC2 ITP_BPM#4 H_D#23 M23 AE22 H_D#55
H_A#24 A[23]# PRDY# ITP_BPM#5 0.5" of GTLREF H_D#24 D[23]# D[55]# H_D#56
R4 A[24]# PREQ# AC1 P25 D[24]# D[56]# AF23
H_A#25 T5 AC5 ITP_TCK pin H_D#25 P23 AC25 H_D#57
H_A#26 A[25]# TCK ITP_TDI H_D#26 D[25]# D[57]# H_D#58
T3 A[26]# TDI AA6 P22 D[26]# D[58]# AE21
H_A#27 W2 AB3 ITP_TDO H_D#27 T24 AD21 H_D#59
H_A#28 A[27]# TDO ITP_TMS +1.05V_VCCP H_D#28 D[27]# D[59]# H_D#60
W5 A[28]# TMS AB5 R24 D[28]# D[60]# AC22
H_A#29 Y4 AB6 ITP_TRST# H_D#29 L25 AD23 H_D#61
H_A#30 A[29]# TRST# ITP_DBRESET# H_D#30 D[29]# D[61]# H_D#62
U2 A[30]# DBR# C20 ITP_DBRESET# 13,31 T25 D[30]# D[62]# AF22
2
H_A#31 V4 H_D#31 N25 AC23 H_D#63
H_A#32 A[31]# R353 56 R339 D[31]# D[63]#
W3 A[32]# 5 H_DSTBN#1 L26 DSTBN[1]# DSTBN[3]# AE25 H_DSTBN#3 5
H_A#33 AA4 THERMAL 2 1 +1.05V_VCCP 1K/F M26 AF24
A[33]# 5 H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 5
H_A#34 AB2 N24 AC20
A[34]# 5 H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 5
B H_A#35 AA3 D21 H_PROCHOT# B
PAD T44
1
A[35]# PROCHOT# H_THERMDA V_CPU_GTLREF AD26 COMP0
5 H_ADSTB#1 V1 ADSTB[1]# THERMDA A24 H_THERMDA 37 GTLREF COMP[0] R26 Note:
B25 H_THERMDC CPU_TEST1 C23 MISC COMP[1] U26 COMP1 H_DPRTSTP need to daisy chain
THERMDC H_THERMDC 37 TEST1
2
A6 CPU_TEST2 D25 AA1 COMP2
11 H_A20M# A20M# TEST2 COMP[2] from ICH8 to IMVP6 to CPU.
A5 C7 H_THERMTRIP# CPU_TEST3 C24 Y1 COMP3
11 H_FERR# FERR# THERMTRIP# H_THERMTRIP# 37 TEST3 COMP[3]
ICH
ICH
C4 R360 56 R338 CPU_TEST4 AF26
11 H_IGNNE# IGNNE# TEST4
1 2 +1.05V_VCCP 2K/F CPU_TEST5 AF1 E5
TEST5 DPRSTP# H_DPRSTP# 6,11,51
D5 H CLK CPU_TEST6 A26 B5
11 H_STPCLK# H_DPSLP# 11
1
STPCLK# TEST6 DPSLP#
11 H_INTR C6 LINT0 DPWR# D24 H_DPWR# 5
11 H_NMI B4 LINT1 BCLK[0] A22 CLK_CPU_BCLK 17 6,17 CPU_MCH_BSEL0 B22 BSEL[0] PWRGOOD D6 H_PWRGOOD 11
11 H_SMI# A3 SMI# BCLK[1] A21 CLK_CPU_BCLK# 17 6,17 CPU_MCH_BSEL1 B23 BSEL[1] SLP# D7 H_CPUSLP# 5
6,17 CPU_MCH_BSEL2 C21 BSEL[2] PSI# AE6 H_PSI# 51
M4 RSVD[01]
N5 Merom Ball-out Rev 1a
RSVD[02] C101
T2 RSVD[03] Voltage Level shift
V3 H_THERMDA 1 2 H_THERMDC
RSVD[04]
RESERVED
B2 +1.05V_VCCP +3.3V_ALW
RSVD[05] 2200P/50V_NC CPU_TEST3
C3 RSVD[06] PAD T7
D2 PAD T42 CPU_TEST5
RSVD[07]
2
D22 R358 1K/F_NC
RSVD[08] CPU_TEST1
D3 RSVD[09] 1 2 For the purpose of testability, route these signals
F6 R351 R355 1K/F_NC through a ground referenced Z0 = 55ohm trace that
RSVD[10] 2.2K_NC CPU_TEST2
1 2
ends in a via that is near a GND via and is
2
Q57 C401 0.1U/10V_NC
1
2 1 CPU_TEST4 accessible through an oscilloscope connection.
Merom Ball-out Rev 1a H_PROCHOT# 1 3 R357 0_NC
CPU_PROCHOT# 31
1 2 CPU_TEST6
2N7002W-7-F_NC
C
Place C close to the FSB BCLK BSEL2 BSEL1 BSEL0 C
CPU_TEST4 pin. Make sure
CPU_TEST4 routing is 533 133 0 0 1
Populate ITP700Flex for bringup reference to GND and away 667 166 0 1 1
from other noisy signal.
+1.05V_VCCP 800 200 0 1 0
Layout Note:
Place couple 0.1uF Decoupling COMP0
caps with in 0.1" ITP connector.
1
1
1
1
COMP1
R9 R7 R3 R2 COMP2
51/F 51 39/F 150 +1.05V_VCCP +3.3V_ALW