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A B C D E
1 1
Compal confidential
Schematics Document
2 2
Mobile Penryn uFCPGA with Intel
Cantiga_GM+ICH9-M SFF core logic
3 3
ULV core logic HDI board
DISCRETE VGA M92 2009-06-19 V.03
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/04/20 Deciphered Date 2010/04/30 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LS-5588 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, July 01, 2009 Sheet 1 of 35
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A B C D E
Compal confidential
Model Name : NAW20
File Name : LS-5588P
ULV ZZZ
CK505
1
Thermal Sensor Mobile Peryn PCB-MB
1
LV/ULV Dual Core Clock Generator
uFCPGA-956 CPU - SFF ICS9LPRS387BKLFT
page 4 MLF 72P
page 16
page 4,5,6,7
DISCRETE VGA HDI BRD H_A#(3..35) FSB
H_D#(0..63)
page 17,18,19,20,21 667/800/1066MHz 1.05V
ATI M92 S2 Intel Cantiga GS
600MHz DDR3-SO-DIMM X 2
FCBGA 1363 - SFF DDR3 1066MHz 1.5V BANK 0, 1, 2, 3 page 14,15
Dual Channel
VRAM DDR3
512MB(64Mx16) page 8,9,10,11,12,13
2 2
DMI X4
SATA x3
RGB
USB x9
Single Channel PCIE*3 Intel ICH9-M
LPC WBMMAP-569 - SFF HDA
page 22,23,24,25
3 3
Golden finger HDI to I/O board page 26
HDMI LPC
HDA
EC AUDIO
PCIE
CRT miniPCIE*1
USB
LVDS SATA
USB*2 CMOS LAN
miniPCIE
ODD CardReader *2
4
I/O BRD PORTION 4
HDD BT
ESATA Security Classification Compal Secret Data Compal Electronics, Inc.
2009/04/20 2010/04/30 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LS-5588 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, July 01, 2009 Sheet 2 of 35
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A
( O MEANS ON X MEANS OFF )
Voltage Rails
Symbol Note :
+B +5VALW +1.5V +5VS
+3VL +3VALW +3VS
+1.5VS : means Digital Ground
power
plane +0.75VS
+VCCP
+CPU_CORE : means Analog Ground
+VGA_CORE
+1.1VS @ : means just reserve , no build
+1.8VS
ME@ : means ME part.
State
45@ : means install after SMT.
S0 O O O O
S1 O O O O
S3 O O O X
S5 S4/AC O O X X
S5 S4/ Battery only O X X X
S5 S4/AC & Battery
1
don't exist X X X X SMBUS Control Table
1
SERIAL THERMAL
SOURCE INVERTER BATT EEPROM SENSOR SODIMM CLK CHIP MINI CARD LCD
(CPU)
SMB_EC_CK1
SMB_EC_DA1
KB926 X V V X X X X X
SMB_EC_CK2
SMB_EC_DA2
KB926 X X X V X X X X
SMB_CK_CLK1
SMB_CK_DAT1 ICH9 X X X X V V V X
LCD_CLK
LCD_DAT Cantiga
X X X X X X X V
I2C / SMBUS ADDRESSING
DEVICE HEX ADDRESS
DDR SO-DIMM 0 A0 10100000
CLOCK GENERATOR (EXT.) D2 11010010
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/04/20 Deciphered Date 2010/04/30 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LS-5588 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, July 01, 2009 Sheet 3 of 35
A
5 4 3 2 1
XDP_TDI
+VCCP
XDP_DBRESET#
XDP_TDO XDP_TDI R1 1 2 54.9_0402_1%
XDP_TMS XDP_TMS R2 1 2 54.9_0402_1%
XDP_TRST# XDP_TDO R3 1 2 54.9_0402_1%
D XDP_TCK XDP_BPM#5 R4 1 2 54.9_0402_1% D
XDP_BPM#5 R03
@ @ @ @ XDP_TRST# R6 1 2 51_0402_1%
3
2
3
2
3
2
3
2
+VCCP
Place close to U1.
D12 D9 D10 D11 XDP_TCK R7 1 2 54.9_0402_1%
[8] H_A#[3..16] PJDLC05_SOT23-3 PJDLC05_SOT23-3 PJDLC05_SOT23-3 PJDLC05_SOT23-3
U1A This shall place near CPU
H_A#3 P2 M4
A[3]# ADS# H_ADS# [8]
H_A#4 V4 J5 R03
A[4]# BNR# H_BNR# [8]
H_A#5 W1 L5 H_BPRI# [8]
2
2
A[5]# BPRI#
56_0402_5%
H_A#6 T4
A[6]#
ADDR GROUP 0
H_A#7 AA1 N5 R10
1
1
1
1
A[7]# DEFER# H_DEFER# [8]
H_A#8 AB4 F38 51_0402_1% 0518/'09
A[8]# DRDY# H_DRDY# [8]
H_A#9 T2 J1
A[9]# DBSY# H_DBSY# [8]
R9
H_A#10 9/20
AC5 For ESD
1
1
A[10]#
CONTROL
H_A#11 AD2 M2
A[11]# BR0# H_BR0# [8]
H_A#12 AD4
H_A#13 A[12]#
AA5 B40
H_A#14 A[13]# IERR#
AE5 D8 H_INIT# [23]
H_A#15 A[14]# INIT#
AB2
H_A#16 AC1 A[15]# N1
A[16]# LOCK# H_LOCK# [8]
[8] H_ADSTB#0 Y4
ADSTB[0]# H_RESET#
G5 H_RESET# [8]
R1 RESET# K2
[8] H_REQ#0 REQ[0]# RS[0]# H_RS#0 [8]
0.1U_0402_16V4Z
[8] H_REQ#1 R5 H4 H_RS#1 [8] 1
REQ[1]# RS[1]#
[8] H_REQ#2 U1 K4 H_RS#2 [8]
REQ[2]# RS[2]# C1251 @
[8] H_REQ#3 P4 L1 H_TRDY# [8]
W5 REQ[3]# TRDY#
[8] H_REQ#4 REQ[4]#
H2 2 For EMI
[8] H_A#[17..35] HIT# H_HIT# [8]
H_A#17 AN1 F2
C A[17]# HITM# H_HITM# [8] C
H_A#18 AK4
H_A#19 A[18]# Add 0 ohm per EMI request.
AG1 AY8
A[19]# BPM[0]# +3VS
ADDR GROUP 1
H_A#20 AT4 BA7 10/17
H_A#21 AK2 A[20]# BPM[1]# BA5
H_A#22 A[21]# BPM[2]#
AT2 AY2
H_A#23 A[22]# BPM[3]# R25 R03
AH2 AV10
A[23]# PRDY#
0.1U_0402_16V4Z
H_A#24 XDP_BPM#5_R 0_0402_5% XDP_BPM#5
XDP/ITP SIGNALS
AF4 AV2 1 2 1
H_A#25 AJ5 A[24]# PREQ# AV4 XDP_TCK
H_A#26 A[25]# TCK XDP_TDI C1034
AH4 AW7
H_A#27 A[26]# TDI XDP_TDO U7
AM4 AU1
H_A#28 AP4 A[27]# TDO AW5 XDP_TMS 2
H_A#29 A[28]# TMS XDP_TRST#
AR5 AV8
H_A#30 A[29]# TRST# XDP_DBRESET# SMB_EC_CK2
AJ1 J7 XDP_DBRESET# [24] 1 8 EC_SMB_CK2 [17,26]
H_A#31 AL1 A[30]# DBR# H_PROCHOT# VDD SMCLK
A[31]# H_PROCHOT# [31]
H_A#32 AM2 H_THERMDA 2 7 SMB_EC_DA2
A[32]# +VCCP DP SMDATA EC_SMB_DA2 [17,26]
H_A#33 AU5
A[33]# THERMAL Place Close to U1. H_PROCHOT# C1035
H_A#34 AP2 1 2 H_THERMDC 3 6 R3051 2 10K_0402_5% +3VS
H_A#35 AR1 A[34]# D38 R22 1 2 68_0402_5% 2200P_0402_50V7K DN ALERT#
A[35]# PROCHOT# H_THERMDA_R R23
[8] H_ADSTB#1 AN5 BB34 1 2 0_0402_5% H_THERMDA THERM# 4 5
ADSTB[1]# THERMDA H_THERMDC_R R24 THERM# GND
BD34 1 2 0_0402_5% H_THERMDC
THERMDC R306
[23] H_A20M# C7
A20M#
0.1U_0402_16V4Z
D4 B10 H_THERMTRIP# 1 @ +3VS 1 2
[23] H_FERR# FERR# THERMTRIP# H_THERMTRIP# [8,23]
ICH
ICH
F10 R03 10K_0402_5% EMC1402-1-ACZL-TR_MSOP8
[23] H_IGNNE# IGNNE# C1045
H_THERMDA, H_THERMDC routing together,
[23] H_STPCLK# F8
STPCLK# 2 Address:100_1100
[23] H_INTR C9
LINT0 H CLK Trace width / Spacing = 10 / 10 mil
[23] H_NMI C5 A35 CLK_CPU_BCLK [16]
LINT1 BCLK[0]
[23] H_SMI# E5 C35 CLK_CPU_BCLK# [16]
SMI# BCLK[1]
V2
Y2 RSVD01
RSVD02
AG5
RSVD03
RESERVED
B AL5 B
RSVD04
J9
RSVD05
F4
RSVD06
H8
RSVD07
PENRYN SFF_UFCBGA956 H_A20M#
H_FERR#
H_IGNNE#
H_INIT#
H_STPCLK#
H_INTR
H_NMI
H_SMI#
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 1 1 1 1 1 1 1
C1036 C1037 C1038 C1039 C1040 C1041 C1042 C1043
2 2 2 2 2 2 2 2
For ESD 4/21
@ @ @ @ @ @ @ @
A A
Security Classification Compal Secret Data
Title