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ZZZ1 PJP1




LA-5413P [email protected] DCIN
[email protected]



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Compal Confidential
2 2




NBLB2 Schematics Document
Intel Clarksfield Processor with DDRIII + Ibex PM55

2009-11-17
REV:0.2
3 3




4 4




Security Classification Compal Secret Data Compal Electronics,Ltd.
Issued Date 2009/02/04 Deciphered Date 2010/02/04 Title
Cover Sheet
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBLB2 M/B LA-5413P Schematic
Date: Thursday, November 19, 2009 Sheet 1 of 61
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Compal Confidential
Clock Gen.
Model Name : NBLB2 SLG8SP587
9LRS3199AKLFT
File Name : LA-5413P(Madison) page23


1 1


LVDS Conn.
page 22 VRAM 64M*16
DDR3*8 Intel Mobile Clarkfield
DDR3-SO-DIMM X2
page 18,19 PCI-Express Dual Channel BANK 0, 1, 2, 3 page 11,12
ATI Madison uPGA989 DDR3-1066/1333(1.5V)
page5~10
Switch




Switch CRT
page 21

FDI*8 DMI*4
2
HDMI Switch 2

Level shift
page 20
USB conn x4 Bluetooth CMOS Camera Finger Print
page 42
Conn page 41 page 47
Conn page 47

3.3V 48MHz USB
Intel Ibex Peak-M
PCI-Express
3.3V 24.576MHz/48Mhz
FCBGA 1071 HD Audio
PM55/HM55 S-ATA
Card Reader
page24~32 RTS5159
port 0 port 1 page 34
New Card MINI Card x2 LAN(GbE) MDC 1.5 HDA Codec
Socket WLAN, Conn 47
page
ALC272
page 44
TV-Tuner AR8131 3 in 1
page 38 S-ATA HDD S-ATA ODD
3
page 37 page 35
LPC BUS Conn.page 33 Conn. page 33 socket 3


page 34

Audio AMP
RJ45 page 45
RTC CKT. page 36
page 43 EC
Conductive/B ENE KB926D3
Power USB/B page39 HP/MIC
Power On/Off CKT. EXT Jack
page 40
page 42 page 45

USB I/O Conn. Int.KBD
DC/DC Interface CKT. CIR Touch Pad page40
page41
page 48
LID SW BIOS
4 4
page41
Power Circuit DC/DC Debug port
page 42
page 48,49,50,52
53,54,55,56
TPM Security Classification Compal Secret Data Compal Electronics,Ltd.
Issued Date 2009/02/04 Deciphered Date 2010/09/14 Title

CHARGER LED MB Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
page 51 page 47 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBLB2 M/B LA-5412P Schematic
Date: Friday, November 13, 2009 Sheet 2 of 61
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DDR3 Voltage Rails
1 1




EC SM Bus1 address EC SM Bus2 address
+5VS Device Address Device Address
power
plane +3VS Smart Battery 0001 011X b EMCI 1402 100_1100X b
+1.5VS EEPROM(24C16/02) 1010 000X b NVIDIA N10P-GE1
+5VALW +CPU_CORE
+B +1.5V +VGA_CORE
+5VALW
+3VALW +1.8VS
+0.75VS
Battery EEPROM
State +1.05VS
+1.1VS_VTT SMB1 +3VALW
+1.5VS_VRAM +3VS
EC VGA Thermal
VGA PCH for thermal
Sensor Mornitor
2 2

S0 SMB2 2B7002
O O O O
S1
O O O O
S3
+3VALW
O O O X +3VALW

S5 S4/AC DDR VREF WLAN1 New Card CLK_GEN
O O X X
S5 S4/ Battery only
O X X X 2B7002


S5 S4/AC & Battery SMB
don't exist X X X X
DDR VREF WLAN2 DIMMI1 DIMMI2




PCH
+3VALW
GPIO PIN Define
3 3



SML0
ID3 ID2 ID1 ID0
NBLB2(1100 ) R358 R361 R766 R765
For system
Reserve (1101 ) X X X X +3VALW +3VS thermal mornitor
Reserve (1110 ) X X X X
Reserve (1111 ) X X X X EC_SMB1
NBLB1 (0000 ) R353 R350 R766 R765
Reserve( 0001 ) X X X X SML1 2B7002
Reserve( 0010 ) X X X X
Reserve( 0011 ) X X X X
Reserve( 0100 ) X X X X
Reserve( 0101 ) X X X X
Reserve (0110 ) X X X X
Reserve (0111 ) X X X X
4 4
Reserve (1000 ) X X X X
Reserve (1001 ) X X X X
Reserve (1010 ) X X X X
Reserve (1011 ) X X X X
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/04 Deciphered Date 2010/02/04 Title
MB Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBLB2 M/B LA-5412P Schematic
Date: Friday, November 13, 2009 Sheet 3 of 61
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VGA (Madison)
+3VS_DELAY
power +1.8VS
plane +VGA_CORE
State +1.5VS_VRAM
+1.1VS

S0
1
O O 1
S1
O O
S3
S5 S4/AC
X X
S5 S4/ Battery only
X X
S5 S4/AC & Battery
X X
don't exist X X

Ref:46039_m97_ds_nda_1.00
M97 sequence

M97 has the following requirements with regards to power supply sequencing to avoid damaging the ASIC.
All the ASIC supplies must fully reach their respective nominal voltages within 20 ms of the start of the ramp-up
sequence, though a shorter ramp-up duration is preferred.
VDDC should ramp before or simultaneously with VDDCI.
VDDCI should ramp before VDDR1.
VDDC should ramp before VDDR4.
2 2
VDDC should ramp before DPx_VDD18, DPx_VDD10, and DPx_PVDD.
PWRGOOD must not be asserted, and must not exceed 300 mV, before all of VDDC, VDD_CT, and VDDR3 have
ramped up. Asserting PWRGOOD only after all ASIC supplies have ramped up is preferred for forward
compatibility.
PWRGOOD must be de-asserted, and must be brought below 300 mV, before ramping down any of VDDC,
VDD_CT, or VDDR3.
DDC3DATA_DP3_AUXN, DDC4DATA_DP4_AUXN, DDC3CLK_DP3_AUXP, and DDC4CLK_DP4_AUXP
must be pulled high either before or after both VDDC and VDD_CT have ramped up.
For power down, reversing the ramp-up sequence is recommended.



POWER UP/DOWN Sequence



t0>=0
3 3
(VDDC) +VGA_CORE

+VDDCI


(DPX_PDD10) +1.0VS


(VDDR1) +1.5VS_VRAM


(VDD_CT,DPX_PVDD,DPX_VDD18) +1.8VS


(VDDR3) +3VS_DELAY

<=20ms <=20ms
4 4




Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/24 Deciphered Date 2010/02/24 Title
VGA Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBLB2 M/B LA-5412P Schematic
Date: Friday, November 13, 2009 Sheet 4 of 61
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5 4 3 2 1

JCPU1E

JCPU1A R151 AJ13
PEG_IRCOMP RSVD32
PEG_ICOMPI B26 1 2 49.9_0402_1% RSVD33 AJ12
PEG_ICOMPO A26
DMI_PTX_HRX_N0 A24 B27 R152 AP25
DMI_PTX_HRX_N1 C23 DMI_RX#[0] PEG_RCOMPO EXP_RBIAS RSVD1
DMI_RX#[1] PEG_RBIAS A25 1 2 750_0402_1% AL25 RSVD2 RSVD34 AH25
DMI_PTX_HRX_N2 B22 AL24 AK26
DMI_PTX_HRX_N3 A21 DMI_RX#[2] PCIE_GTX_C_MRX_N15 RSVD3 RSVD35
DMI_RX#[3] PEG_RX#[0] K35 AL22 RSVD4
J34 PCIE_GTX_C_MRX_N14 AJ33 AL26
DMI_PTX_HRX_P0 PEG_RX#[1] PCIE_GTX_C_MRX_N13 RSVD5 RSVD36
B24 DMI_RX[0] PEG_RX#[2] J33 AG9 RSVD6 RSVD_NCTF_37 AR2
DMI_PTX_HRX_P1 D23 G35 PCIE_GTX_C_MRX_N12 M27
DMI_RX[1] PEG_RX#[3] RSVD7




DMI
DMI
DMI_PTX_HRX_P2 B23 G32 PCIE_GTX_C_MRX_N11 L28 AJ26
DMI_PTX_HRX_P3 DMI_RX[2] PEG_RX#[4] PCIE_GTX_C_MRX_N10 RSVD8 RSVD38
D A22 DMI_RX[3] PEG_RX#[5] F34 11 H_DIMMA_REF J17 RSVD9 (SA_DIMM_VREF) RSVD39 AJ27 D
F31 PCIE_GTX_C_MRX_N9 H17
DMI_HTX_PRX_N0 D24 PEG_RX#[6] PCIE_GTX_C_MRX_N8
12 H_DIMMB_REF RSVD10(SB_DIMM_VREF)
DMI_TX#[0] PEG_RX#[7] D35 G25 RSVD11
DMI_HTX_PRX_N1 G24 E33 PCIE_GTX_C_MRX_N7 G17
DMI_HTX_PRX_N2 F23 DMI_TX#[1] PEG_RX#[8] PCIE_GTX_C_MRX_N6 RSVD12
DMI_TX#[2] PEG_RX#[9] C33 E31 RSVD13 RSVD_NCTF_40 AP1
DMI_HTX_PRX_N3 H23 D32 PCIE_GTX_C_MRX_N5 E30 AT2
DMI_TX#[3] PEG_RX#[10] PCIE_GTX_C_MRX_N4 RSVD14 RSVD_NCTF_41
PEG_RX#[11] B32
DMI_HTX_PRX_P0 D25 C31 PCIE_GTX_C_MRX_N3 AT3
DMI_HTX_PRX_P1 F24 DMI_TX[0] PEG_RX#[12] PCIE_GTX_C_MRX_N2 RSVD_NCTF_42
DMI_TX[1] PEG_RX#[13] B28 RSVD_NCTF_43 AR1
DMI_HTX_PRX_P2 E23 B30 PCIE_GTX_C_MRX_N1
DMI_HTX_PRX_P3 G23 DMI_TX[2] PEG_RX#[14] PCIE_GTX_C_MRX_N0
DMI_TX[3] PEG_RX#[15] A31

J35 PCIE_GTX_C_MRX_P15 R153 AL28
PEG_RX[0] PCIE_GTX_C_MRX_P14 3.01K_0402_1% RSVD45
PEG_RX[1] H34 1 @ 2 CFG0 AM30 CFG[0] RSVD46 AL29
H33 PCIE_GTX_C_MRX_P13 CFG1 AM28 AP30
FDI_CTX_PRX_N0 PEG_RX[2] PCIE_GTX_C_MRX_P12 R154 CFG2 CFG[1] RSVD47
E22 FDI_TX#[0] PEG_RX[3] F35 AP31 CFG[2] RSVD48 AP32
FDI_CTX_PRX_N1 D21 G33 PCIE_GTX_C_MRX_P11 3.01K_0402_1% 1 2 CFG3 AL32 AL27
FDI_CTX_PRX_N2 FDI_TX#[1] PEG_RX[4] PCIE_GTX_C_MRX_P10 CFG[3] RSVD49
D19 FDI_TX#[2] PEG_RX[5] E34 1 @ 2 CFG4 AL30 CFG[4] RSVD50 AT31
FDI_CTX_PRX_N3 D18 F32 PCIE_GTX_C_MRX_P9 3.01K_0402_1% R155 CFG5 AM31 AT32
FDI_CTX_PRX_N4 FDI_TX#[3] PEG_RX[6] PCIE_GTX_C_MRX_P8 CFG6 CFG[5] RSVD51
G21 FDI_TX#[4] PEG_RX[7] D34 AN29 CFG[6] RSVD52 AP33
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
E19
F21
FDI_TX#[5]
FDI_TX#[6]
PCI EXPRESS -- GRAPHICS PEG_RX[8]
PEG_RX[9]
F33
B33
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_P6
R156
3.01K_0402_1%
1 @ 2 CFG7
CFG8
AM32
AK32
CFG[7]
CFG[8]
RSVD53
RSVD_NCTF_54
AR33
AT33
Intel(R) FDI
Intel(R) FDI

FDI_CTX_PRX_N7 G18 D31 PCIE_GTX_C_MRX_P5 CFG9 AK31 AT34




RESERVED
FDI_TX#[7] PEG_RX[10] PCIE_GTX_C_MRX_P4 CFG10 CFG[9] RSVD_NCTF_55
PEG_RX[11] A32 AK28 CFG[10] RSVD_NCTF_56 AP35
PEG_RX[12] C30 PCIE_GTX_C_MRX_P3 WW41 Recommend not pull down CFG11 AJ28 CFG[11] RSVD_NCTF_57 AR35
FDI_CTX_PRX_P0 D22 A28 PCIE_GTX_C_MRX_P2 PCIE2.0 Jitter is over on ES1 CFG12 AN30 AR32
FDI_CTX_PRX_P1 FDI_TX[0] PEG_RX[13] PCIE_GTX_C_MRX_P1 CFG13 CFG[12] RSVD58
C21 FDI_TX[1] PEG_RX[14] B29 AN32 CFG[13]
FDI_CTX_PRX_P2 D20 A30 PCIE_GTX_C_MRX_P0 CFG14 AJ32
FDI_CTX_PRX_P3 FDI_TX[2] PEG_RX[15] CFG15 CFG[14]
C18 FDI_TX[3] AJ29 CFG[15] RSVD_TP_59 E15
C FDI_CTX_PRX_P4 G22 L33 PEG_HTX_GRX_N15 C316 1 2 [email protected] 0.1U_0402_16V7K PCIE_MTX_C_GRX_N15 CFG16 AJ30 F15 C
FDI_CTX_PRX_P5 FDI_TX[4] PEG_TX#[0] PEG_HTX_GRX_N14 C315 [email protected] 0.1U_0402_16V7K PCIE_MTX_C_GRX_N14 CFG17 CFG[16] RSVD_TP_60
E20 FDI_TX[5] PEG_TX#[1] M35 1 2 AK30 CFG[17] KEY A2
FDI_CTX_PRX_P6 F20 M33 PEG_HTX_GRX_N13 C314 1 2 [email protected] 0.1U_0402_16V7K PCIE_MTX_C_GRX_N13 CFG18 H16 D15 R157
FDI_CTX_PRX_P7 FDI_TX[6] PEG_TX#[2] PEG_HTX_GRX_N12 C313 [email protected] 0.1U_0402_16V7K PCIE_MTX_C_GRX_N12 RSVD_TP_86 RSVD62 0_0402_5%
G19 FDI_TX[7] PEG_TX#[3] M30 1 2 RSVD63 C15
L31 PEG_HTX_GRX_N11 C312 1 2 [email protected] 0.1U_0402_16V7K PCIE_MTX_C_GRX_N11 AJ15 RSVD64_R 2 @ 1
FDI_FSYNC0 PEG_TX#[4] PEG_HTX_GRX_N10 C311 [email protected] 0.1U_0402_16V7K PCIE_MTX_C_GRX_N10 RSVD64 RSVD65_R 2 @
F17 FDI_FSYNC[0] PEG_TX#[5] K32 1 2 RSVD65 AH15 1
FDI_FSYNC1 E17 M29 PEG_HTX_GRX_N9 C310 1 2 [email protected] 0.1U_0402_16V7K PCIE_MTX_C_GRX_N9 R158
FDI_FSYNC[1] PEG_TX#[6] PEG_HTX_GRX_N8 C309 [email protected] 0.1U_0402_16V7K PCIE_MTX_C_GRX_N8 0_0402_5%
PEG_TX#[7] J31 1 2 B19 RSVD15
FDI_INT C17 K29 PEG_HTX_GRX_N7 C308 1 2 [email protected] 0.1U_0402_16V7K PCIE_MTX_C_GRX_N7 R160 A19
FDI_INT PEG_TX#[8] PEG_HTX_GRX_N6 C307 [email protected] 0.1U_0402_16V7K PCIE_MTX_C_GRX_N6 0_0402_5% RSVD16
PEG_TX#[9] H30 1 2
FDI_LSYNC0 F18 H29 PEG_HTX_GRX_N5 C306 1 2 [email protected] 0.1U_0402_16V7K PCIE_MTX_C_GRX_N5 1 @ 2 H_RSVD17_R A20
FDI_LSYNC1 FDI_LSYNC[0] PEG_TX#[10] PEG_HTX_GRX_N4 C305 [email protected] 0.1U_0402_16V7K PCIE_MTX_C_GRX_N4 @ H_RSVD18_R RSVD17
D17 FDI_LSYNC[1] PEG_TX#[11] F29 1 2