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1 2 3 4 5 6 7 8
PCB STACK UP
8L DIS V02A/R01A DIS BLOCK DIAGRAM
LAYER 1 : TOP
LAYER 2 : GND
A
PCIEx16 ATI A
LAYER 3 : IN1 DDRIII-SODIMM1 DDRIII 1333 MT/s
CPU Robson XT(64bit)
LAYER 4 : VCC
H=4mm PAGE 16 Seymour XT (64bit)
Sandy Bridge 35W Whistler LP (128bit)
LAYER 5 : IN2 PGA 988 29mm X 29mm
LAYER 6 : IN3
BGA 969
DDRIII-SODIMM2 DDRIII 1333 MT/s PAGE 18~22
LAYER 7 : GND H=8mm PAGE 17 PAGE 4~8
LAYER 8 : BOT
DDR3 2GB
FDI LINK DMI LINK 128Mx16bitx8 LEVEL SHIFTER HDMI CONN
2.5GT /s 2.5GT /s PG 23,24
INT HDMI PAGE 27 PAGE 27
iGFX Interfaces
SATA4 3G /S
E-SATA
INT CRT CRT Board
PAGE 28 PAGE 26
B B
INT Single CHANNEL LVDS
LCD CONN
SATA0 6G /S 1366 x 768 (HD) PAGE 25
SATA -HDD
Mobile Intel ESATA+USB2.0 USB Port x1
PAGE 31
PAGE 35 PAGE 29
Series 6 Chipset
USB2.0 USB[0] USB[2]
SATA1 6G /S
ODD
USB[11] USB[8]
PAGE 36
PCH Camera Card Reader
PAGE 30 RTL5128-GRPAGE 30
3-axis Fall Sensor SMBUS HM67
USB[4] USB[5]
PAGE 31
Couger Point WLAN WWAN
PAGE 34 PAGE 35
PCIE[1] PCIE[2]
BGA 989 PCI-E PCI-E
C Charger C
Keyboard Conn. LPC PAGE 49
25 mm X 25 mm PCIE[5] PCIE[3]
PAGE 42
USB3.0 Controller 3/5V
KBC LAN PAGE 50
Touch Pad PAGE 36
PAGE 42
ITE 8518 Realtek
1.5V_SUS/0.75V_DDR
RTL8111EL PAGE 51
PAGE 9~15 PAGE 39
USB3.0 Ports x2
IHDA PAGE 37 1.8V_RUN
PAGE 32 PAGE 52
25MHz
SPI 1.05V_VTT/PCH
IHDA PAGE 53
25MHz 32.768KHz
SPI ROM SPI ROM
PWM FAN
512KB 4MB
RJ45 IO Board VCCSA
PAGE 54
&Thermal PAGE 39 PAGE 33
PAGE 45 PAGE 41 PAGE 41
DGFX_CORE
Audio Codec PAGE 55
ALC 269
D D
PAGE 38 CPU_CORE
PAGE 56
Speaker Jack Digital-MIC Quanta Computer Inc.
MB Side PAGE 38 X2 PAGE 38 PAGE 38
PROJECT : V02A/RO1A
Size Document Number Rev
1A
BLOCK DIAGRAM
Date: W ednesday, January 19, 2011 Sheet 1 of 61
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
power
A A
State
S0
S1
S3
B B
S4/S5 AC
S4/S5
DC Only
AC/DC
No Exist
C C
SMBCLK
SMBDATA
SMB_CLK_ME1
SMB_DAT_ME1
AB1A_CLK
AB1A_DATA
D D
Quanta Computer Inc.
PROJECT : V02A/RO1A
Size Document Number Rev
1A
Power Rails
Date: W ednesday, January 19, 2011 Sheet 2 of 61
1 2 3 4 5 6 7 8
5 4 3 2 1
D D
C C
B B
A A
Quanta Computer Inc.
PROJECT : V02A/RO1A
Size Document Number Rev
1A
BLANK
Date: W ednesday, January 19, 2011 Sheet 3 of 61
5 4 3 2 1
5 4 3 2 1
DP & PEG Compensation
+1.05V_PCH
Sandy Bridge Processor (DMI,PEG,FDI)
U16A
PEG_ICOMPO 12mil
D J22 PEG_COMP PEG_ICOMPI, PEG_RCOMPO 4mil, D
PEG_ICOMPI R21 24.9/F_4 eDP_COMP
PEG_ICOMPO J21
9 DMI_TXN0 B27 DMI_RX#[0] PEG_RCOMPO H22
9 DMI_TXN1 B25 DMI_RX#[1] PEG_RXN[0..15] 18 eDP_COMPIO and ICOMPO signals should
9 DMI_TXN2 A25 DMI_RX#[2] be shorted near balls and
B24 K33 PEG_RXN0
9 DMI_TXN3 DMI_RX#[3] PEG_RX#[0] routed within 500 mils
M35 PEG_RXN1
PEG_RX#[1] PEG_RXN2
9 DMI_TXP0 B28 DMI_RX[0] PEG_RX#[2] L34
B26 J35 PEG_RXN3
9 DMI_TXP1 DMI_RX[1] PEG_RX#[3]
DMI
A24 J32 PEG_RXN4
9 DMI_TXP2 DMI_RX[2] PEG_RX#[4] +1.05V_PCH
B23 H34 PEG_RXN5
9 DMI_TXP3 DMI_RX[3] PEG_RX#[5]
H31 PEG_RXN6
PEG_RX#[6] PEG_RXN7
9 DMI_RXN0 G21 DMI_TX#[0] PEG_RX#[7] G33
E22 G30 PEG_RXN8
9 DMI_RXN1 DMI_TX#[1] PEG_RX#[8]
F21 F35 PEG_RXN9 R47 24.9/F_4 PEG_COMP
9 DMI_RXN2 DMI_TX#[2] PEG_RX#[9]
D21 E34 PEG_RXN10
9 DMI_RXN3 DMI_TX#[3] PEG_RX#[10]
E32 PEG_RXN11
PEG_RX#[11] PEG_RXN12
9 DMI_RXP0 G22 DMI_TX[0] PEG_RX#[12] D33
D22 D31 PEG_RXN13
9 DMI_RXP1 DMI_TX[1] PEG_RX#[13]
PCI EXPRESS* - GRAPHICS
F20 B33 PEG_RXN14
9 DMI_RXP2 DMI_TX[2] PEG_RX#[14]
C21 C32 PEG_RXN15 PEG_RXP[0..15] 18 PEG_ICOMPI and RCOMPO signals should
9 DMI_RXP3 DMI_TX[3] PEG_RX#[15]
be routed within 500 mils
J33 PEG_RXP0
PEG_RX[0] PEG_RXP1
PEG_RX[1] L35
K34 PEG_RXP2 PEG_ICOMPO signals should
PEG_RX[2] PEG_RXP3
9 FDI_TXN0 A21 FDI0_TX#[0] PEG_RX[3] H35 be routed within 500 mils
H19 H32 PEG_RXP4
9 FDI_TXN1 FDI0_TX#[1] PEG_RX[4]
E19 G34 PEG_RXP5
9 FDI_TXN2 FDI0_TX#[2] PEG_RX[5]
F18 G31 PEG_RXP6
Intel(R) FDI
9 FDI_TXN3 FDI0_TX#[3] PEG_RX[6]
C B21 F33 PEG_RXP7 C
9 FDI_TXN4 FDI1_TX#[0] PEG_RX[7]
C20 F30 PEG_RXP8
9 FDI_TXN5 FDI1_TX#[1] PEG_RX[8]
D18 E35 PEG_RXP9
9 FDI_TXN6 FDI1_TX#[2] PEG_RX[9]
E17 E33 PEG_RXP10
9 FDI_TXN7 FDI1_TX#[3] PEG_RX[10]
F32 PEG_RXP11
PEG_RX[11] PEG_RXP12
PEG_RX[12] D34
A22 E31 PEG_RXP13
9 FDI_TXP0 FDI0_TX[0] PEG_RX[13]
G19 C33 PEG_RXP14
9
9
FDI_TXP1
FDI_TXP2 E20
FDI0_TX[1]
FDI0_TX[2]
PEG_RX[14]
PEG_RX[15] B32 PEG_RXP15
PEG_TXN[0..15] 18
eDP Hot-plug (Disable)
9 FDI_TXP3 G18 FDI0_TX[3]
B20 M29 PEG_TXN0_C C487 0.1U/10V_4 PEG_TXN0
9 FDI_TXP4 FDI1_TX[0] PEG_TX#[0] +1.05V_PCH
C19 M32 PEG_TXN1_C C482 0.1U/10V_4 PEG_TXN1
9 FDI_TXP5 FDI1_TX[1] PEG_TX#[1]
D19 M31 PEG_TXN2_C C478 0.1U/10V_4 PEG_TXN2
9 FDI_TXP6 FDI1_TX[2] PEG_TX#[2]
F17 L32 PEG_TXN3_C C471 0.1U/10V_4 PEG_TXN3
9 FDI_TXP7 FDI1_TX[3] PEG_TX#[3]
L29 PEG_TXN4_C C467 0.1U/10V_4 PEG_TXN4
PEG_TX#[4] PEG_TXN5_C C52 0.1U/10V_4 PEG_TXN5
9 FDI_FSYNC0 J18 FDI0_FSYNC PEG_TX#[5] K31
J17 K28 PEG_TXN6_C C45 0.1U/10V_4 PEG_TXN6 R20
9 FDI_FSYNC1 FDI1_FSYNC PEG_TX#[6]
J30 PEG_TXN7_C C44 0.1U/10V_4 PEG_TXN7 *10K_4_NC
PEG_TX#[7] PEG_TXN8_C C43 0.1U/10V_4 PEG_TXN8
9 FDI_INT H20 FDI_INT PEG_TX#[8] J28
H29 PEG_TXN9_C C40 0.1U/10V_4 PEG_TXN9
PEG_TX#[9] PEG_TXN10_C C38 0.1U/10V_4 PEG_TXN10 INT_eDP_HPD
9 FDI_LSYNC0 J19 FDI0_LSYNC PEG_TX#[10] G27
H17 E29 PEG_TXN11_C C35 0.1U/10V_4 PEG_TXN11
9 FDI_LSYNC1 FDI1_LSYNC PEG_TX#[11]
F27 PEG_TXN12_C C30 0.1U/10V_4 PEG_TXN12
PEG_TX#[12] PEG_TXN13_C C29 0.1U/10V_4 PEG_TXN13
PEG_TX#[13] D28
F26 PEG_TXN14_C C27 0.1U/10V_4 PEG_TXN14
PEG_TX#[14] PEG_TXN15_C C24 0.1U/10V_4 PEG_TXN15
PEG_TX#[15] E25 PEG_TXP[0..15] 18 CAD Note: Place PU resistor within 2 inches
eDP_ICOMPO 12mil eDP_COMP
A18 eDP_COMPIO PEG_TXP0_C C488 0.1U/10V_4 PEG_TXP0 of CPU
A17 eDP_ICOMPO PEG_TX[0] M28
eDP_COMPIO 4mil INT_eDP_HPD B16 M33 PEG_TXP1_C C481 0.1U/10V_4 PEG_TXP1
B eDP_HPD PEG_TX[1] PEG_TXP2_C C477 0.1U/10V_4 PEG_TXP2 B
PEG_TX[2] M30
PEG_TXP3_C C470 0.1U/10V_4 PEG_TXP3
This signal can be left as no connect if
PEG_TX[3] L31
C15 L28 PEG_TXP4_C C466 0.1U/10V_4 PEG_TXP4 entire eDP interface is disabled.
eDP_AUX PEG_TX[4] PEG_TXP5_C C47 0.1U/10V_4 PEG_TXP5
D15 eDP_AUX# PEG_TX[5] K30
eDP
K27 PEG_TXP6_C C46 0.1U/10V_4 PEG_TXP6
PEG_TX[6] PEG_TXP7_C C42 0.1U/10V_4 PEG_TXP7
PEG_TX[7] J29
C17 J27 PEG_TXP8_C C41 0.1U/10V_4 PEG_TXP8
eDP_TX[0] PEG_TX[8] PEG_TXP9_C C37 0.1U/10V_4 PEG_TXP9
F16 eDP_TX[1] PEG_TX[9] H28
Programing Disable eDP interface(BIOS) C16 G28 PEG_TXP10_C C36 0.1U/10V_4 PEG_TXP10
eDP_TX[2] PEG_TX[10] PEG_TXP11_C C33 0.1U/10V_4 PEG_TXP11
G15 eDP_TX[3] PEG_TX[11] E28
F28 PEG_TXP12_C C32 0.1U/10V_4 PEG_TXP12
PEG_TX[12] PEG_TXP13_C C28 0.1U/10V_4 PEG_TXP13
C18 eDP_TX#[0] PEG_TX[13] D27
E16 E26 PEG_TXP14_C C26 0.1U/10V_4 PEG_TXP14
eDP_TX#[1] PEG_TX[14] PEG_TXP15_C C25 0.1U/10V_4 PEG_TXP15
D16 eDP_TX#[2] PEG_TX[15] D25
F15 eDP_TX#[3]
0.22uF AC coupling Caps for PCIE GEN1/2/3
CPU-989P-rPGA
A A
Quanta Computer Inc.
PROJECT : V02A/RO1A
Size Document Number Rev
1A
Sandy Bridge 1/5
Date: W ednesday, January 19, 2011 Sheet 4 of 61
5 4 3 2 1
5 4 3 2 1
Sandy Bridge Processor (CLK,MISC,JTAG)
U16B
SNB_IVB# N.A at SNB EDS #27637 0.7v1
BCLK A28 CLK_CPU_BCLKP 13
MISC
CLOCKS
12 H_SNB_IVB# H_SNB_IVB# C26 A27 CLK_CPU_BCLKN 13
PROC_SELECT# BCLK#
AN34 R310 1K_4
D 32 H_CPUDET# SKTOCC#
A16 CLK_DP_P_R R306 *0_4_NC CLK_DP_P 13
Schematic C/L_v1.0, P56 (PU,PD 1k/J) D
DPLL_REF_CLK
DPLL_REF_CLK# A15 CLK_DP_N_R R307 *0_4_NC CLK_DP_N 13 (Intel and PD3)
R311 1K_4 +1.05V_PCH
Reserve (Intel confirm now)
AL33 CATERR#
THERMAL
32 PECI_EC R73 43_4 AN33 R8 CPU_DRAMRST#
PECI SM_DRAMRST#
DDR3
MISC
32,44,47 IMVP7_PROCHOT# R77 56/J_4 H_PROCHOT# AL32 AK1 SM_RCOMP_0 R66 140/F_4
PROCHOT# SM_RCOMP[0] SM_RCOMP_1 R23 25.5/F_4
SM_RCOMP[1] A5
SM_RCOMP_2 R26 200/F_4
SM_RCOMP_0, SM_RCOMP_1 20mil
SM_RCOMP[2] A4
SM_RCOMP_2 15mil,
Over 130 degree C will 14 PM_THRMTRIP# AN32 THERMTRIP#
drive low
+1.05V_PCH
PRDY# AP29
PREQ# AP27
XDP_TMS R333 51/J_4
AR26 XDP_TCLK XDP_TDI R328 51/J_4
TCK
PWR MANAGEMENT
XDP_TMS XDP_TDO R334 51/J_4
JTAG & BPM
TMS AR27
9 H_PM_SYNC AM34 AP30 XDP_TRST# R322 51/J_4 IMVP7_PROCHOT# R76 62/J_4
PM_SYNC TRST#
C AR28 XDP_TDI C
TDI XDP_TDO XDP_TCLK R335 51/J_4
TDO AP26
14 H_PW RGOOD AP33 +3.3V_RUN
UNCOREPWRGOOD
R231 10K_4
AL35 XDP_DBRST# R319 1K_4
SM_DRAMPW ROK DBR#
V8 SM_DRAMPWROK
XDP_DBRST# use a 1k pull-up to 3.3V_S
BPM#[0] AT28 TRST# use a 51ohm pull down.
+1.05V_PCH R81 *75_4_NC AR29
BPM#[1]
BPM#[2] AR30
CPU_PLTRST# R82 *43/J_4_NC CPU_PLTRST#_R AR33 AT30 When MP, JTAG PU/PD resistor
RESET# BPM#[3]
BPM#[4] AP32
AR31 can be removed?
BPM#[5]
BPM#[6] AT31 Need to confirm with Intel
BPM#[7] AR32
CPU_PLTRST R497,R126 U19,C544,R81,R82 +3.3V_SUS
Option1 POP NC CPU-989P-rPGA
Option2 NC POP
C544 Boot S3 S3 RSM
U19 *0.1U/10V_NC
1 NC VCC 5
12,18,32,33,35 PLTRST# 2 IN
B
+1.5V_CPU B
3 4 CPU_PLTRST#
R497 GND OUT
1.5K *74LVC1G07GW _NC DRAM_PWRGD
100 ns after +1.5V_CPU
SYS_PWROK reaches 80%
CPU_PLTRST#_R
IN OUT SM_DRAMPWROK
R126
L L 750/F Follow #DG1.0 436735 P107 +1.5V_SUS
DRAMRST# Routing Illustration
H High-Z
R51
1K/F_4 Q2
Change OD part same with PDC R45 2N7002W -7-F
1K/F_4
Pin1 Pin2 Pin4 DDR3_DRAMRST#_R 3 1 CPU_DRAMRST#
Copy from PDC +3.3V_SUS 16,17 DDR3_DRAMRST#
L L L
2
+1.5V_CPU
L H L
13 DDR_HVREF_RST_PCH
H L L R43
C156 4.99K/F_4
R118 0.1U/10V H H H C39
A
200_4 R109 0.047U/10V A
200/F_4
5
U4
9 PM_DRAM_PW RGD 2
4 SM_DRAMPW ROK_R R108 130/F_4 SM_DRAMPW ROK
9 SYS_PW ROK 1