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1 2 3 4 5 6 7 8
PCB STACK UP
8L HDI
PS-Note, CULV BLOCK DIAGRAM 01
CPU CPU THERMAL
Top-GND-IN1-IN2-SVCC-IN3-GND-Bot SENSOR
14.318MHz
A Penryn SFF Page 4 A
956P (BGA)
Page 3,4,5 CLK_CPU_BCLK,CLK_CPU_BCLK#
CLK_MCH_BCLK,CLK_MCH_BCLK# CK505
CLOCK GEN
FSB 667/800/1067
Page 2
Battery Charger
ISL88731A
Page 30
LCD CONN
DDRIII 1067 MTs NORTH BRIDGE Page 20
3V/5V DDRIII-SODIMM0
ISL6237IRZ-T Page 12
Cantiga SFF
Page 31 HDMI CON
GS45/ GS40 Page 21
DDRIII 1067 MTs 1363P (FCBGA)
B
CPU CORE DDRIII-SODIMM1 B
RT8152B Page 13 CRT CON
Page 32 Page 22
Page 6,7,8,9,10,11
32.768KHz
DDR3, VTT
DMI LINK NBSRCCLK, NBSRCCLK#
TPS51116REGR
USB2.0
Page 33
SATA - 2.5" HDD/ SSD
SATA0 150MB
Page 25
SOUTH BRIDGE USB2.0 Ports Webcam BlueTooth Mini PCI-E Card Card Reader Controller
1.05V/ 1.5V
X3 Page 23,27 Page 20 Page 23 X2 Page 26 Realtek RTS5158/5159
RT8204
Page 34
ICH9-M SFF 4 in 1 socket
Page 27
PCI-E
569P (FCBGA)
NB CORE
C MAX8796GTJ+ PAGE 26~29 Azalia C
Page 37
Page 14,15,16,17 Mini PCI-E
Giga LAN Card WLAN Mini PCI-E
CODEC Realtek Card WWAN
S5 power, LDO
32.768KHz LPC Conexant RTL8111DL
CX20582
Page 36
Page 18
Page 19 Page 26 Page 26
Keyboard T/P
Page 24 ITE EC
INT MIC
IT8502E RJ45 SIM socket
Page 18 Page 19 Page 26
Accelerometer Sensor
Page 28
Page 23
D
Audio Jacks INT Speaker D
HP/ SPDIF MIC Page 18
Page 27
FAN SPI PROJECT :PS1
Page 25 Page 28 Quanta Computer Inc.
Size Document Number Rev
Custom 1A
Block Diagram
Date: Saturday, October 31, 2009 Sheet 1 of 41
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
02
4,7,10,12,13,14,15,16,17,18,19,20,21,22,23,25,26,27,28,29,31,32,34,35,37 +3V
3,4,5,6,7,9,10,14,17,34,35,37 +1.05V
+3V
L40
1 2 +3V_CK_MAIN
HCB1608KF(1.5A,180) U16
C329
C272 C326 C335 C273 C296 +3V_CK_MAIN
+3V .1U/10V/X7_4 .1U/10V/X7_4 .1U/10V/X7_4
23
16
VDDPLL3 CPUCLKT0 61
60
CLK_CPU_BCLK 3 CPU Differential Host Clock
A VDD48 CPUCLKC0 CLK_CPU_BCLK# 3 A
10U/6.3V/X5_8 .1U/10V/X7_4 .1U/10V/X7_4 9
4
VDDPCI
VDDREF
CK505 CPUCLKT1 58 CLK_MCH_BCLK 6 NB Differential Host Clock
L32 46 57
VDDSRC CPUCLKC1 CLK_MCH_BCLK# 6
1 2 +3V_CK_CPU +3V_CK_CPU 62 VDDCPU
HCB1608KF(1.5A,180)
+3V_CK_MAIN2 CPUT2_ITP/SRCT8 54 CLK_PCIE_WWAN 26 WWAN EC-20090726A-4
19 VDD96I/O CPUC2_ITP/SRCC8 53 CLK_PCIE_WWAN# 26
+1.05V C242 C248 27
10U/6.3V/X5_8 .1U/10V/X7_4 VDDPLL3I/O
+3V L42
33
43
VDDSRCI/O DOTT_96/SRCT0 20
21
DREFCLK 7 NB Display PLLA Differential Clock
VDDSRCI/O DOTC_96/SRCC0 DREFCLK# 7
1 2 52 VDDSRCI/O
HCB1608KF(1.5A,180)
L41 56
27MHz_Nonss/SRCCLK1/SE1 24
25
DREFSSCLK 7 NB Display PLLB Differential Clock
VDDCPU_IO 27Mhz_ss/SRCCLC1/SE2 DREFSSCLK# 7
1 2 +3V_CK_MAIN2 55
*HCB1608KF-181T15_6 NC
SRCCLKT2/SATACL 28
29
CLK_PCIE_LAN 19 PCI-E LAN
SRCCLKC2/SATACL CLK_PCIE_LAN# 19
C338 C334 C287 C254 C316 C255 C336 CG_XIN 3
.1U/10V/X7_4 .1U/10V/X7_4 .1U/10V/X7_4 CG_XOUT X1 *PAD T18
2 X2 SRCCLKT3/CR#_C 31
10U/6.3V/X5_8 .1U/10V/X7_4 .1U/10V/X7_4 .1U/10V/X7_4 32 *PAD T19
SRCCLKC3/CR#_D
*100K/F_4 R139
VDDIO selection SRCCLKT4 34
35
CLK_PCIE_3GPLL 7 NB Differential PCI Express based
SRCCLKC4 CLK_PCIE_3GPLL# 7
+3V Graphics/DMI Clock
15 CK_PWG 63 CK_PWRGD/PD# PCI_STOP# 45 PM_STPPCI# 15
CPU_BSEL1 R138 *0_4S FSB 64 44
FSLB/TEST_MODE CPU_STOP# PM_STPCPU# 15
SRCCLKT6 48
47
CLK_PCIE_ICH 16 SB
SRCCLKC6 CLK_PCIE_ICH# 16
R156
2.2K/F_4
R157
2.2K/F_4 12,13,26,29 CGCLK_SMB
7 SCLK SRCCLKT7/CR#_F 51 R_CLK_WWAN_OE#
*PAD
R140
T17
475/F_4
CLK_WWAN_OE# 26 EC-20090726A-4
6 SDATA SRCCLKC7/CR#_E 50
B Q10 12,13,26,29 CGDAT_SMB B
2
2N7002E
22
SRCCLKT9 37
38
CLK_PCIE_SATA 14 SATA
GND SRCCLKC9 CLK_PCIE_SATA# 14
3 1 CGDAT_SMB 26
15 PDAT_SMB GND
18
59
GND48 SRCCLKT10 41
42
CLK_PCIE_WLAN 26 WLAN
GNDCPU SRCCLKC10 CLK_PCIE_WLAN# 26
15 GNDPCI
+3V 1 GNDREF SRCCLKT11/CR#_H 40 R_CLK_WLAN_OE#
R_CLK_SATA_OE#
R163
R174
475/F_4
475/F_4
CLK_WLAN_OE# 26 EC-20090726A-3
30 GNDSRC SRCCLKC11/CR#_G 39 CLK_SATA_OE# 15
Q9 36 GNDSRC
2
2N7002E 49 GNDSRC R_CLK_LAN_OE# R161 475/F_4
PCICLK0/CR#_A 8 CLK_LAN_OE# 19
3 1 CGCLK_SMB 10 R_CLK_MCH_OE# R173 475/F_4
15 PCLK_SMB PCICLK1/CR#_B CLK_MCH_OE# 7
11 TME R172 33_4
PCICLK2/TME PCLK_LPC_DEBUG 26
12 R_PCLK_KBC R180 33_4
PCICLK3 PCLK_LPC_8512 28
13 27M_SEL
PCICLK4/27_SELECT
65 ITP_EN R190 33_4
EPAD PCLK_ICH 16
14 R202 33_4
PCI_F5/ITP_EN CLK_48M_USB 15
Y2
17 FSA R201 2.2K/F_4 CPU_BSEL0
CG_XIN 1 CG_XOUT USB_48MHZ/FSLA R152 10K/F_4 CPU_BSEL2
2
5 FSC R154 33_4
FSLC/TST_SL/REF CLK_14M_ICH 15
XTAL_14.318MHZ
1
1
+3V ICS9LPRS365BKLFT
C258 C259
33P/50V/COG_4 33P/50V/COG_4
2
2
+3V
2
C CLK_MCH_OE# R169 2 1 10K/F_4 C
R176
10K/F_4 CLKREQ SRC Port EC-20090726A-3 CLK_WLAN_OE# R167 1 10K/F_4
TME=High 2
1
CR#_B SRC 1,4 CLK_MCH_OE# SRC4
TME OC of CPU and SRC are not allowed.
CR#_A SRC 0,2 CLK_LAN_OE# SRC2 CLK_LAN_OE# R162 2 1 10K/F_4
27M_SEL
CR#_G SRC 9 CLK_SATA_OE# SRC9
CLK_SATA_OE# R175 10K/F_4
27M_SEL= LOW UMA
2
CR#_H SRC 10 CLK_MINI_OE# SRC10
R182
10K/F_4
CR#_F SRC 8 CLK_WWAN_OE# SRC 8 CLK_WWAN_OE# R31 2 1 10K/F_4
1
C322 *33P/50V/NPO_4 PCLK_LPC_8512
C327 *27P/50V_4 PCLK_ICH
C304 *33P/50V/NPO_4 PCLK_LPC_DEBUG
CPU_BSEL0 R207 1K/F_4
3 CPU_BSEL0 MCH_BSEL0 7
ITP_EN R_PCLK_KBC
C333 *10P/50V_4 CLK_48M_USB
R200 1K/F_4
2
2
C285 *33P/50V/NPO_4 CLK_14M_ICH
R181 CPU_BSEL1 R133 1K/F_4
D 3 CPU_BSEL1 MCH_BSEL1 7 D
*10K/F_4
R187
10K/F_4
1
1
+1.05V R134 1K/F_4
CPU_BSEL2 R148 1K/F_4
3 CPU_BSEL2 MCH_BSEL2 7
Disable ITP. PROJECT :PS1
+1.05V R149 1K/F_4 Quanta Computer Inc.
Size Document Number Rev
Custom 1A
Clock Generator
Date: Saturday, October 31, 2009 Sheet 2 of 41
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
H_A#[3..35] EC-20091002C-2
U19A T38 *PAD
03
6 H_A#[3..35] 2,4,5,6,7,9,10,14,17,34,35,37 +1.05V
H_A#3 P2 M4
A[3]# ADS# H_ADS# 6
H_A#4 V4 J5
A[4]# BNR# H_BNR# 6
H_A#5 W1 L5
A[5]# BPRI# H_BPRI# 6
H_A#6 T4 A[6]#
ADDR GROUP 0
H_A#7 AA1 N5 H_D#[0..63] U19B H_D#[0..63]
A[7]# DEFER# H_DEFER# 6 6 H_D#[0..63] H_D#[0..63] 6
H_A#8 AB4 F38 H_D#0 F40 AP44 H_D#32
A[8]# DRDY# H_DRDY# 6 D[0]# D[32]#
H_A#9 T2 J1 H_D#1 G43 AR43 H_D#33
A[9]# DBSY# H_DBSY# 6 D[1]# D[33]#
H_A#10 AC5 +1.05V Place close to CPU H_D#2 E43 AH40 H_D#34
A[10]# H_BR0# 6 D[2]# D[34]#
CONTROL
H_A#11 AD2 M2 H_D#3 J43 AF40 H_D#35
A[11]# BR0# D[3]# D[35]#
DATA GROUP 0
H_A#12 AD4 R34 56.2/F_4 H_D#4 H40 AJ43 H_D#36
H_A#13 A[12]# H_IERR# 1 H_D#5 D[4]# D[36]# H_D#37
AA5 A[13]# IERR# B40 2 +1.05V H44 D[5]# D[37]# AG41
H_A#14 R19 H_D#6 H_D#38
DATA GROUP 2
AE5 A[14]# INIT# D8 H_INIT# 14 G39 D[6]# D[38]# AF44
H_A#15 AB2 *51/F_4 H_D#7 E41 AH44 H_D#39
A
H_A#16 A[15]# H_D#8 D[7]# D[39]# H_D#40 A
AC1 A[16]# LOCK# N1 H_LOCK# 6 L41 D[8]# D[40]# AM44
Y4 H_D#9 K44 AN43 H_D#41
6 H_ADSTB#0 H_REQ#[0..4] ADSTB[0]# D[9]# D[41]#
G5 H_RESET# H_D#10 N41 AM40 H_D#42
6 H_REQ#[0..4] RESET# H_RESET# 6 D[10]# D[42]#
H_REQ#0 R1 K2 H_D#11 T40 AK40 H_D#43
REQ[0]# RS[0]# H_RS#0 6 D[11]# D[43]#
H_REQ#1 R5 H4 H_D#12 M40 AG43 H_D#44
REQ[1]# RS[1]# H_RS#1 6 D[12]# D[44]#
H_REQ#2 U1 K4 Layout Note: H_D#13 G41 AP40 H_D#45
REQ[2]# RS[2]# H_RS#2 6 D[13]# D[45]#
H_REQ#3 P4 L1 Place voltage H_D#14 M44 AN41 H_D#46
REQ[3]# TRDY# H_TRDY# 6 D[14]# D[46]#
H_REQ#4 W5 H_D#15 L43 AL41 H_D#47
H_A#[3..35] REQ[4]# divider within D[15]# D[47]#
HIT# H2 H_HIT# 6 6 H_DSTBN#0 K40 DSTBN[0]# DSTBN[2]# AK44 H_DSTBN#2 6
H_A#17 AN1 A[17]# HITM# F2 H_HITM# 6