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5 4 3 2 1
Model Name: 945GME-DS2 Revision 3.0
SHEET TITLE SHEET TITLE
01 COVER SHEET 28 REAR AUDIO JACK
D
02 BLOCK DIAGRAM 29 DISCRETE POWER D
03 BOM & PCB MODIFY HISTORY 30 VCORE PWM_ISL6312
04 P4_LGA775_A 31 ATX, OTHERS POWER
05 P4_LGA775_B 32 REALTEK RTL8110SC
06 P4_LGA775_C 33 FRONT PANEL
07 P4_LGA775_D,E,F,G
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08 GMCH-LAKEPORT_HOST
09 GMCH-LAKEPORT_DDRII
C C
10 GMCH-LAKEPORT_PCI E, DMI
11 GMCH-LAKEPORT_INT VGA
12 GMCH-LAKEPORT_GND
13 GMCH-LAKEPORT_PWR
14 DDRII CHANNEL A 1 Digitally signed by dd
15 DDRII CHANNEL B 2 DN: cn=dd, o=dd,
16 DDRII TERMINATION ou=dd,
B
17 PCI EXPRESS*16 SLOT email=dddd@yahoo. B
18 ICH7 PCI, USB, DMI, LAN
com, c=US
19 ICH7 IDE, GPIO, SATA, CTRL
Date: 2010.01.19
20 ICH7 VCC, GND
21 GB/CK410M-OC CLOCK.
19:10:43 +07'00'
22 PCI SLOT 1,2,3
23 IDE/FLOPPY
24 ITE 8718 GBIX
25 COM_LPT
A A
26 BIOS,CI,HWM,KB/MS
27 AZALIA ALC888
Gigabyte Technology
Title
Cover Sheet
Size Document Number Rev
Custom 945GME-DS2 3.0
Date: Thursday, February 08, 2007 Sheet 1 of 33
5 4 3 2 1
5 4 3 2 1
BLOCK DIAGRAM
INTEL Pentium4
LGA775
D
CLOCK GENERATOR D
VCORE = 1.4V
VCC3
CKVDD = 3.3V
PCI EXPRESS X16
VDDQ = 1.5V (AGP POWER 4X)
CHANNEL A
VCC3 = 3.3V
+12V = 12V DDRII DIMM X 1
3VDUAL = 3.3V
VCC = 5V GMCH
LAKEPORT(945G) MAA0~14
1.8VSTR = 1.8V(MEMORY,SUSPEND POWER)
VTT_DDR = 0.9V
PAGE 14,15
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MAA_CPC1~5
MAB_CPC1~5
MDD0~63 CHANNEL B
-DQSD0~7
DM0~7
DDRII DIMM X 1
1.8VSTR = 1.8V(MEMORY,SUSPEND POWER)
VCORE = 1.75V / SLEEP : 1.3V VTT_DDR = 0.9V
2_5VSTR = 2.5V(MEMORY) PAGE 16,17
VDDQ = 1.5V (AGP POWER 4X, HUBLINK)
C C
IDE Primary
ICH7
VCC = 5V PAGE 28
USB PORTS 0~7 SERIAL ATA
VCC25 = 2.5V(I/O,MEMORY/I,VLINK/I)
VCC = 5V 3VDUAL = 3.3V(SUSPEND POWER)
5VSB = 5V VCC3 = 3.3V
5VUSB = 5V RTCVDD = 3.3V VCC = 5V PAGE 21
PCI BUS
B FWH/HWMO B
PCI SLOT 1,2,3
VCC = 5V
+12 = 12V VCC3 = 3V PAGE 27
-12 = -12V
VCC = 5V
VCC3 = 3V
3VDUAL = 3V
REALTEK RTL8110SC LPC BUS
AZALIA ALC888 LPC I/O ITE8718GB
+12V = 12V
VCC3 = 3.3V VCC = 5V
VCC = 5V 5VSB = 5V
AVDD = 5V PAGE 33 VBAT = 3V PAGE 39
A AUDIO PORTS : FRONT AUDIO FRONT PANEL /CPU FAN I/O PORTS : A
LIN_ OUT LINE_IN MIC VCC = 5V
5VSB = 5V
CD_IN +12 = 12V
PVCC = 5V
COMA COMB LPT PS2 FDD
PAGE 34,35 PAGE 29,40
Gigabyte Technology
Title
BOM & PCB MODIFY HISTORY
Size Document Number Rev
Custom 945GME-DS2 3.0
Date: Thursday, February 08, 2007 Sheet 2 of 33
5 4 3 2 1
5 4 3 2 1
Model Name:945GME-DS2 Circuit or PCB layout change
for next version
Version: 3.0
DATE Change Item Reason
D D
Component value change
history 2007/02/07
Data Change Item Reason
2006/04/14 1.RENAME 945ZM-S2-->8I945GZME-RH
(8I945GZME SPEC,)
2006/04/17 SWAP NET
2006/04/18 U87 ADD MASK GND PIN9
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2006/04/20 BAT LIB/EMI
2006/05/21 R1.0 LAYOUT 1. MODIFY EMI ISSUE
2.MODIFY PWM+VCC1_5(S3)+RESET+-THRMTRIP
C 2006/06/06 PVT SCH SEND C
2006/07/03 COMP8 CHANGE 30/6/1
VTT_PWRGD# ADD RC DELAY TIME BOM:9M945GZMER-00-10B
PCB R2.0:AUDIO(VISTA)+SB_HS+SMD
2006/08/29 FUSE+VCORE(8C VCORE 5PCS E-CAP
CAP)+CHOKE+
2006/09/05 MODIFY AUDIO 1X3-->2X3 JACK.
2006/09/18 MODIFY NAME:945GZM-S2
2006/09/21 MODIFY CHOKE FOOTPRINT
2006/09/22 MODIFY NAME:945PLM-DS2 R20
2006/10/11 PBOM:9M945PLMDR-00-20B
B
2006/10/16 MODIFY NAME:945GCM-DS2 R20 FROM 945PLM-DS2 R20 1.CHIPSET 945G SUPPORT FSB1066 B
2006/10/17 945GCM-DS2 R2.1 OC FSB1066(ICS954148)
2006/10/20 945PLM-DS2 R2.1 OC FSB1066(ICS954148)
2006/10/30 945GCM-S2 R2.1 OC FSB1066(ICS954148)
2006/11/20 Dynamic O.C ISSUE REMOVE R1911,R1580
CHANG AP9T18GH LOW THRESOLD FIX MOS BURN OUT
R1707/R1905-->4.7/6 PBOM:9M945CMS2R-00-21B
2006/11/23 REV 2.11:MODIFY CHOKE
2006/12/13 R3.0 MODIFY LAN RTL8110SC
2006/12/14 MODIFY 78L05 SMD
2007/01/22 REMOVE R252 FOR DOTCLK PBOM:9M945GMEDR-00-30A
A A
2007/02/07 FIXE INTEL D STEPPING CPU F_PBOM:9M945GMEDR-00-30B
Gigabyte Technology
Title
BOM & PCB MODIFY HISTORY
Size Document Number Rev
Custom 945GME-DS2 3.0
Date: Thursday, February 08, 2007 Sheet 3 of 33
5 4 3 2 1
5 4 3 2 1
R422
124/6/1
GTLREF1
VTT_OR
VCORE VCORE
R424 C262
210/6/1 1u/6/Y5V/10V/Z
R1
124/6/1
+
+
+
+
BC5 BC6 BC7 BC8 EC1 EC2 EC3 EC4 GTLREF0
VTT_OR
10u/12/X7R/6.3V/K 10u/12/X7R/6.3V/K 10u/12/X7R/6.3V/K 10u/12/X7R/6.3V/K 100U/2V/SPCAP/X 100U/2V/SPCAP/X 100U/2V/SPCAP/X 100U/2V/SPCAP/X
D D
R2 C1
210/6/1 1u/6/Y5V/10V/Z
VCORE
SP-CAP-MASK
BC1 BC2 BC3 BC4
10u/12/X7R/6.3V/K 10u/12/X7R/6.3V/K 10u/12/X7R/6.3V/K 10u/12/X7R/6.3V/K R3 62/6 -IERR
VTT_OR
R4 62/6 -BR0
VTT_OL
R5 62/6 -CPURST
VTT_OR
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LGA775-D [DIP TYPE]
RN1 62/8P4R/6
HA[3..16] LGA775A 7 8 TESTHI10
[8] HA[3..16] VTT_OL
HA3 L5 D2 -HADS 5 6 TESTHI9
C A<3>* ADS* -HADS [8] C
A<4>* LGA775
HA4 P6 C2 -BNR 3 4 TESTHI8
BNR* -BNR [8]
HA5 M5 D4 -HIT 1 2
A<5>* HIT* -HIT [8]
HA6 L4 A<6>* (1/8) RSP* H4
HA7 M4 G8 -BPRI
A<7>* BPRI* -BPRI [8]
HA8 R4 B2 -DBSY
A<8>* DBSY* -DBSY [8]
HA9 T5 C1 -DRDY
A<9>* DRDY* -DRDY [8]
HA10 U6 E4 -HITM
A<10>* HITM* -HITM [8]
HA11 T4 AB2 -IERR
HA12 A<11>* IERR* -HINIT
U5 A<12>* INIT* P3 -HINIT [19]
HA13 U4 C3 -HLOCK
A<13>* LOCK* -HLOCK [8]
HA14 V5 E3 -HTRDY C2
A<14>* TRDY* -HTRDY [8]
HA15 V4 AD3 33P/4/NPO/50V/J
HA16 A<15>* BINIT* -DEFER
W5 A<16>* DEFER* G7 -DEFER [8]
N4 RSVD_3
P5 AB3 CR
-HREQ0 RSVD_4 MCERR* CPU RETAINTION/X
[8] -HREQ0 K4 REQ<0>*
-HREQ1 J5 U2
[8] -HREQ1 REQ<1>* AP<0>*
-HREQ2 M6 U3
[8] -HREQ2 REQ<2>* AP<1>*
-HREQ3 K6
[8] -HREQ3 REQ<3>*
-HREQ4 J6 F3 -BR0
[8] -HREQ4 REQ<4>* BR<0>* -BR0 [8]
HA[17..31] -HADSTB0 R6 G3 TESTHI8
[8] HA[17..31] [8] -HADSTB0 ADSTB<0>* TESTHI_8
HA17 AB6 G4 TESTHI9
HA18 A<17>* TESTHI_9 TESTHI10
W6 A<18>* TESTHI_10 H5
B HA19 Y6 B
HA20 A<19>*
Y4 A<20>*
HA21 AA4 J16
HA22 A<21>* DP<0>*
AD6 A<22>* DP<1>* H15
HA23 AA5 H16
HA24 A<23>* DP<2>*
AB5 A<24>* DP<3>* J17
HA25 AC5
HA26 A<25>* GTLREF0
AB4 A<26>* GTLREF0 H1
HA27 AF5 H2 GTLREF1
HA28 A<27>* GTLREF1 MCH_GTLREF
AF4 A<28>* GTLREF2 E24 MCH_GTLREF [8]
HA29 AG6 H29 GTL_DET
A<29>* GTLREF_SEL GTL_DET [6,8]
HA30 AG4
HA31 A<30>*
AG5 A<31>*
AH4 G23 -CPURST
A<32>* RESET* -CPURST [8]
AH5 A<33>*
AJ5 A<34>*
AJ6 B3 -RS0 C4
A<35>* RS<0>* -RS0 [8]
AC4 F5 -RS1 22p/4/NPO/50V/J
RSVD_1 RS<1>* -RS1 [8]
AE4 A3 -RS2
RSVD_2 RS<2>* -RS2 [8]
-HADSTB1 AD5
[8] -HADSTB1 ADSTB<1>*
CPU-SK/775/D/GF
A A
Gigabyte Technology
Title
P4_LGA775-A
Size Document Number Rev
B 945GME-DS2 3.0
Date: Thursday, February 08, 2007 Sheet 4 of 33
5 4 3 2 1
5 4 3 2 1
RN2 470/8P4R/6
7 8 FSBSEL0
LGA775B VTT_GMCH
HD[0..15] 5 6 FSBSEL22
[8] HD[0..15] HD[32..47] [8]
HD0 B4 G16 HD32 3 4 FSBSEL1
D<0>* D<32>*
HD1 C5 D<1>* LGA775 D<33>* E15 HD33 1 2
HD2 A4 E16 HD34
D<2>* D<34>*
HD3 C6 D<3>* (2/8) D<35>* G18 HD35
D HD4 A5 G17 HD36 D
HD5 D<4>* D<36>* HD37 RN5 62/8P4R/6
B6 D<5>* D<37>* F17
HD6 B7 F18 HD38 7 8 -BPM1
HD7 D<6>* D<38>* VTT_OR
A7 E18 HD39 5 6 -BPM0
HD8 D<7>* D<39>* HD40 -BPM5
A10 D<8>* D<40>* E19 3 4
HD9 A11 F20 HD41 RN61 2 -BPM4
HD10 D<9>* D<41>* HD42 -BPM2
B10 D<10>* D<42>* E21 7 8
HD11 C11 F21 HD43 5 6 -BPM3
HD12 D<11>* D<43>* HD44 TDI
D8 D<12>* D<44>* G21 3 4
HD13 B12 E22 HD45 C14 1 2 TMS
HD14 D<13>* D<45>* HD46 0.1u/6/Y5V/25V/Z 62/8P4R/6
C12 D<14>* D<46>* D22
HD15 D11 G22 HD47 R35 62/6 TDO
-DBI0 D<15>* D<47>* -DBI2
[8] -DBI0 A8 DB1<0>* DBI<2>* D19 -DBI2 [8]
STBN0 C8 G20 STBN2 R27 470/6 VR_RDY
[8] STBN0 DSTBN<0>* DSTBN<2>* STBN2 [8]
HD[16..31] STBP0 B9 G19 STBP2
[8] HD[16..31] [8] STBP0 HD16 DSTBP<0> DSTBP<2> STBP2 [8] HD[48..63] [8]
G9 D20 HD48 R36 62/6 -TRST
HD17 D<16>* D<48>* HD49 R37 62/6 TCK
F8 D<17>* D<49>* D17
HD18 F9 A14 HD50
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HD19 D<18>* D<50>* HD51
E9 D<19>* D<51>* C15
HD20 D7 C14 HD52
HD21 D<20>* D<52>* HD53 FSBSEL0 R39 8.2K/4 BSEL0
E10 D<21>* D<53>* B15 [21] FSBSEL0 BSEL0 [11]
HD22 D10 C18 HD54 FSBSEL1 R40 8.2K/4 BSEL1
HD23 D<22>* D<54>* [21] FSBSEL1 BSEL1 [11]
F11 B16 HD55 FSBSEL2 R41 8.2K/4 BSEL2
HD24 D<23>* D<55>* [21] FSBSEL2 BSEL2 [11]
F12 A17 HD56
HD25 D<24>* D<56>* HD57
D13 D<25>* D<57>* B18
HD26 E13 C21 HD58
HD27 D<26>* D<58>* HD59
G13 D<27>* D<59>* B21
C
HD28 F14 B19 HD60 C
HD29 D<28>* D<60>* HD61
G14 D<29>* D<61>* A19
HD30 F15 A22 HD62
HD31 D<30>* D<62>* HD63
G15 D<31>* D<63>* B22
-DBI1 G11 C20 -DBI3
[8] -DBI1 STBN1 DB1<1>* DBI<3>* -DBI3 [8]
G12 A16 STBN3
[8] STBN1
[8] STBP1
STBP1 E12
DSTBN<1>*
DSTBP<1>
DSTBN<3>*
DSTBP<3> C17 STBP3
STBN3 [8]
STBP3 [8]
CPU
NA FSB FSA
CPU-SK/775/D/GF
FSBSEL3 FSBSEL1 FSBSEL0 Clock
1 0 1 100MHz X
0 0 1 133MHz
0 1 1 166MHz
0 1 0 200MHz
VTT_GMCH
0 0 0 266MHz
LGA775D
A29
TCK AE1 TCK LGA775 VTT_1
VTT_2 B25 Support 1066 FSB
TDI AD1 B29
TDO AF1
TDI
(4/8) VTT_3 B30
force 800 CPU
B TDO VTT_4 B
TMS AC1 C29 VCC FSBSEL1
TMS VTT_5
3
-TRST AG1 A26
-BPM0 TRST* VTT_6
AJ2 BPM<0>* VTT_7 B27
-BPM1 R1862 D Q303
AJ1 BPM<1>* VTT_8 C28
-BPM2 AD2 A25 8.2K/4/X 2N7002/SOT23/25pF/5/X
-BPM3 BPM<2>* VTT_9 G S
AG2 BPM<3>* VTT_10 A28
-BPM4 AF2 A27
-BPM5 BPM<4>* VTT_11 VTT_GMCH
2
1
AG3 BPM<5>* VTT_12 C30
-SYS_RST AC2 A30
[19,21,33] -SYS_RST
3
DBR* VTT_13
AK3 ITPCLK<0> VTT_14 C25
AJ3 C26 Q304
FSBSEL0 ITPCLK<1> VTT_15 R1864 MMBT2222A/SOT23/600mA/40/X
G29 BSEL<0> VTT_16 C27
FSBSEL1 R1863 2.2/6 FSBSEL11 H30 B26 1K/4/1/X
FSBSEL2 R1913 2.2/6/X FSBSEL22 BSEL<1> VTT_17 FSBSEL0
G30 BSEL<2> VTT_18 D27
2
1
N5 SPARE0 VTT_19 D28
C9 SPARE1 VTT_20 D25
E7 SPARE2 VTT_21 D26
R1914 R1893 AE6 B28
2.2/6 1K/4/X SPARE4 VTT_22
D16 NC_DSS2 VTT_23 D29
A20 NC_DSS3 VTT_24 D30