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1 1
IALAA
2
Minnesota 10A/10AG 2
LA3631P REV 1A Schematic
3 3
AMD Turion,Sempron/ATI RX690/RS690MC / ATI SB600
2007-05-04 Rev. 1A
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/5/4 Deciphered Date 2008/5/4 Title
Cover
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B IALAA-Minnesota10A LA3631P 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 14, 2007 Sheet 1 of 45
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Compal confidential IALAA Minnesota10A FUNCTION BLOCK DIAGRAM
File Name : IALAA Minnesota10A LA3631P
P/N :
Clock Generator Thermal Sensor AMD S1 CPU 638 pin
ICS951462AGLFT GMT G781P8F 533/667MHz FANController PAGE 41
(1.8V) SO-DIMM x 2(DDRII)
4
PAGE 13 PAGE 6 Turion 64 X2 Memory Bus BANK 0,1,2,3
4
PAGE 8,9
Turion 64 RTC Battery PAGE 22
CPU VID Sempron
PAGE 1,2,3,4,5,6,7
DC/DC Interface PAGE 42
PAGE 6 HT
16x16 1000MHZ
Power Buttom
CRT Conn. x1 PCI-E HD DVD PAGE 39
page 15
PAGE 24
ATI-RX/RS690MC x1 PCI-E Mini Card-WLAN
LVDS Conn
page 27
PAGE 24
VGA M26P Embeded
TV-OUT Conn. x1 PCI-E New Card
3 3
page 14 465 pin BGA PAGE 28 RJ-45
PAGE 10,11,12 PAGE 25
LAN
HDMI Conn. VGA Conn x1 PCI-E
RTL8111B-1G
page 20 page 15 RTL8101E-10/100M
MiniCard w/ 3G (Port 8) Finger Printer (Port 5)
A-Link Express II PAGE 24 PAGE 29
PAGE 25
x4 PCIE
USB 2.0 480MHz(5V) USB Port * 2 (Port 0, 1) Int. Camera (Port 7)
33MHz (3.3V) PCI USB Port 0 be debug port. PAGE 29
PAGE 29
ATI-SB600
Primary SATA RealTek WLAN (Port3) Bluetooth (Port 4)
CardBus/ 5IN1/ 1394 548 pin BGA 3.3V,5V PAGE 24 PAGE 29
1.5GHz(150MB/s)
PCI8412-1394/CardBus/5IN1 SATA SATA HDD0
PAGE 16,17,18,19 PAGE 21
USB/B (Port 6, 2) NewCard (Port 9)
PAGE 29 PAGE 28
Secondary
2
PAGE 22, 23
PATAATA-100 (5V) IDE ODD DCIN&DETECTOR 2
PAGE 28 PAGE 36
LPC
33MHz (3.3V) BATT CONN/OTP
PAGE 37
CARD BUS Azalia
1394-Port 5 IN 1 Conn Debug Port Embedded Controller 24MHz(3.3V) CHARGER
SOCKET PAGE 34 HD CODEC Audio Amplifier PAGE 38
PAGE 22 PAGE 23 PAGE 22 ENE KB926 PAGE 30 ALC268-GR APA2057APAGE 27
PAGE 26
Int. 3V/5V/
K/B PAGE 39
SPI PS2
Matrix
MDC w/Rev1.5
Track Scan PAGE 28
1.8V/1.2V
BIOS PAGE 40
Pad KB
PAGE 31 PAGE 33 PAGE 33
2.5V/0.9V/1.5V
PAGE 41
1 1
CPU_CORE
PAGE 42
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/5/4 Deciphered Date 2008/5/4 Title
Black Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS CustomIALAA-Minnesota10A LA3631P 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 14, 2007 Sheet 2 of 45
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SIGNAL
Voltage Rails STATE SLP_S3# SLP_S5# +VALW +V +VS Clock
Full ON HIGH HIGH ON ON ON ON
Power Plane Description S1 S3 S5
S1(Power On Suspend) HIGH HIGH ON ON ON LOW
VIN Adapter power supply (19V) ON ON ON
1 B+ AC or battery power rail for power circuit. ON ON ON S3 (Suspend to RAM) LOW HIGH ON ON OFF OFF 1
+RTCVCC RTC power ON ON ON
S4 (Suspend to Disk) LOW LOW ON OFF OFF OFF
+VSB B+ switched power rail ON ON ON
+5VALW 5V always on power rail ON ON ON S5 (Soft OFF) LOW LOW ON OFF OFF OFF
+3VALW 3.3V always on power rail ON ON ON
+1.2VALW 1.2V always on power rail ON ON ON
+1.8V 1.8V power rail ON ON OFF
ID Table for AD channel
+0.9V 0.9V switched power rail ON ON OFF
+5VS 5VS switched power rail ON OFF OFF Vcc 3.3V +/- 5%
+3VS 3.3VS switched power rail ON OFF OFF Ra 100K +/- 5%
+2.5VS 2.5VS switched power rail ON OFF OFF Board ID Rb V AD_BID min V AD_BID typ V AD_BID max
+1.8VS 1.8VS switched power rail ON OFF OFF 0 0 0 V 0 V 0 V
+1.5VS 1.5VS switched power rail ON OFF OFF 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+CPU_CORE Core voltage for CPU ON OFF OFF 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+1.2V_HT 1.2VS switched power rail ON OFF OFF 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
2 2
4 56K +/- 5% 1.036 V 1.185 V 1.264 V
5 100K +/- 5% 1.453 V 1.650 V 1.759 V
6 200K +/- 5% 1.935 V 2.200 V 2.341 V
7 NC 2.500 V 3.300 V 3.300 V
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
External PCI Devices
Device IDSEL# REQ#/GNT# Interrupts BTN_ID BTO BOM STURCTURE
1394/ CardBus/ 5IN1 AD20 2/ 2 PIRQE/F/G 0
1
2
3
EC SM Bus1 address EC SM Bus2 address 4
5
3 3
Device HEX Address Device HEX Address 6
Smart Battery 16H 0001 011X b CPU Thermal-G781P8F 98H 1001 100X b 7
24C16 A0H 1010 000X b VGA Thermal-
ATi SB600 SM Bus address
SM Bus0 address SM Bus1 address
Device HEX Address
Clock GEN.
(ICS951462AGLFT)
DDR DIMM0 A4
DDR DIMM1 A6
4
Mini Card-WLAN 4
Mini Card-3G
New Card
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/5/4 Deciphered Date 2008/5/4 Title
Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS CustomIALAA-Minnesota10A LA3631P 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 14, 2007 Sheet 3 of 45
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5 4 3 2 1
H_CADIP[0..15] H_CADOP[0..15]
<10> H_CADIP[0..15] H_CADOP[0..15] <10>
D D
H_CADIN[0..15] H_CADON[0..15]
<10> H_CADIN[0..15] H_CADON[0..15] <10>
+1.2V_HT
JP27A
D4 VLDT_A3 VLDT_B3 AE5 1 2
VLDT=500mA D3 AE4 C107 4.7U_0805_10V4Z
VLDT_A2 VLDT_B2
D2 VLDT_A1 VLDT_B1 AE3
D1 VLDT_A0 VLDT_B0 AE2
H_CADIP15 N5 T4 H_CADOP15
H_CADIN15 L0_CADIN_H15 L0_CADOUT_H15 H_CADON15
P5 L0_CADIN_L15 L0_CADOUT_L15 T3
H_CADIP14 M3 V5 H_CADOP14
H_CADIN14 L0_CADIN_H14 L0_CADOUT_H14 H_CADON14
M4 L0_CADIN_L14 L0_CADOUT_L14 U5
H_CADIP13 L5 V4 H_CADOP13
H_CADIN13 L0_CADIN_H13 L0_CADOUT_H13 H_CADON13
M5 L0_CADIN_L13 L0_CADOUT_L13 V3
H_CADIP12 K3 Y5 H_CADOP12
H_CADIN12 L0_CADIN_H12 L0_CADOUT_H12 H_CADON12
K4 W5
H_CADIP11
H_CADIN11
H_CADIP10
H3
H4
L0_CADIN_L12
L0_CADIN_H11
L0_CADIN_L11
L0_CADOUT_L12
L0_CADOUT_H11
L0_CADOUT_L11
AB5
AA5
H_CADOP11
H_CADON11
H_CADOP10
+1.2V_HT
250 mil
VLDT CAP.
G5 L0_CADIN_H10 L0_CADOUT_H10 AB4
H_CADIN10 H5 AB3 H_CADON10
H_CADIP9 L0_CADIN_L10 L0_CADOUT_L10 H_CADOP9
F3 L0_CADIN_H9 L0_CADOUT_H9 AD5
H_CADIN9 F4 AC5 H_CADON9 1 1 1 1 1 1
C H_CADIP8 L0_CADIN_L9 L0_CADOUT_L9 H_CADOP8 C102 C103 C101 C104 C106 C112 C
E5 L0_CADIN_H8 L0_CADOUT_H8 AD4
H_CADIN8 F5 AD3 H_CADON8 4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J
L0_CADIN_L8 L0_CADOUT_L8
HTT Inter face
H_CADIP7 N3 T1 H_CADOP7
H_CADIN7 L0_CADIN_H7 L0_CADOUT_H7 H_CADON7 2 2 2 2 2 2
N2 L0_CADIN_L7 L0_CADOUT_L7 R1
H_CADIP6 L1 U2 H_CADOP6
H_CADIN6 L0_CADIN_H6 L0_CADOUT_H6 H_CADON6
M1 L0_CADIN_L6 L0_CADOUT_L6 U3
H_CADIP5 L3 V1 H_CADOP5
H_CADIN5 L2
L0_CADIN_H5
L0_CADIN_L5
L0_CADOUT_H5
L0_CADOUT_L5 U1 H_CADON5 Near CPU Socket
H_CADIP4 J1 W2 H_CADOP4
H_CADIN4 L0_CADIN_H4 L0_CADOUT_H4 H_CADON4
K1 L0_CADIN_L4 L0_CADOUT_L4 W3
H_CADIP3 G1 AA2 H_CADOP3
H_CADIN3 L0_CADIN_H3 L0_CADOUT_H3 H_CADON3
H1 L0_CADIN_L3 L0_CADOUT_L3 AA3
H_CADIP2 G3 AB1 H_CADOP2
H_CADIN2 L0_CADIN_H2 L0_CADOUT_H2 H_CADON2
G2 L0_CADIN_L2 L0_CADOUT_L2 AA1
H_CADIP1 E1 AC2 H_CADOP1
H_CADIN1 L0_CADIN_H1 L0_CADOUT_H1 H_CADON1
F1 L0_CADIN_L1 L0_CADOUT_L1 AC3
H_CADIP0 E3 AD1 H_CADOP0
H_CADIN0 L0_CADIN_H0 L0_CADOUT_H0 H_CADON0
E2 L0_CADIN_L0 L0_CADOUT_L0 AC1
<10> H_CLKIP1 J5 L0_CLKIN_H1 L0_CLKOUT_H1 Y4 H_CLKOP1 <10>
<10> H_CLKIN1 K5 L0_CLKIN_L1 L0_CLKOUT_L1 Y3 H_CLKON1 <10> C1447 Near H_CADIP/N[2..4] and
<10> H_CLKIP0 J3 L0_CLKIN_H0 L0_CLKOUT_H0 Y1 H_CLKOP0 <10> H_CLKIP/N0 near CPU BOT Side
<10> H_CLKIN0 J2 L0_CLKIN_L0 L0_CLKOUT_L0 W1 H_CLKON0 <10> 1 2
C497 @ 0.01U_0402_25V4Z
+1.2V_HT
R52 2 1 51_0402_1% P3 T5 C1448 Near H_CADIP/N[5..7] and
R51 L0_CTLIN_H1 L0_CTLOUT_H1
2 1 51_0402_1% P4 L0_CTLIN_L1 L0_CTLOUT_L1 R5 H_CTLIP/N0 near CPU BOT Side
1 2
H_CTLIP0 N1 R2 H_CTLOP0 C503 @ 0.01U_0402_25V4Z
B <10> H_CTLIP0 L0_CTLIN_H0 L0_CTLOUT_H0 H_CTLOP0 <10> B
H_CTLIN0 P1 R3 H_CTLON0
<10> H_CTLIN0 L0_CTLIN_L0 L0_CTLOUT_L0 H_CTLON0 <10>
FOX_PZ63823-284S-41F 1 2 C1449 Near H_CADOP/N[0..1]
C496 @ 0.01U_0402_25V4Z near CPU BOT Side
Athlon 64 S1
Processor Socket
AMD : 49.9 1%
ATI : 51 1% VCC GND GND1
For IALAA Only--
Change Layer Bridge for HOST3 CADOP/N[0..7]
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/5/4 Deciphered Date 2008/5/4 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
S1g1 HT I/F
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom IALAA-Minnesota10A LA3631P 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 14, 2007 Sheet 4 of 45
5 4 3 2 1
A B C D E
Processor DDR2 Memory Interface
<9> DDR_B_D[63..0]
JP27C
DDR_A_D[63..0] <8>
+1.8V DDR_B_D63 AD11 AA12 DDR_A_D63
DDR_B_D62 MB_DATA63 MA_DATA63 DDR_A_D62
AF11 MB_DATA62 MA_DATA62 AB12
DDR_B_D61 AF14 AA14 DDR_A_D61
MB_DATA61 MA_DATA61
2
DDR_B_D60 AE14 AB14 DDR_A_D60
R91 DDR_B_D59 MB_DATA60 MA_DATA60 DDR_A_D59
Y11 MB_DATA59 MA_DATA59 W11
1K_0402_1% DDR_B_D58 AB11 Y12 DDR_A_D58
+CPU_M_VREF DDR_B_D57 MB_DATA58 MA_DATA58 DDR_A_D57
4 AC12 MB_DATA57 MA_DATA57 AD13 4
DDR_B_D56 AF13 AB13 DDR_A_D56
1
DDR_B_D55 MB_DATA56 MA_DATA56 DDR_A_D55
AF15 MB_DATA55 MA_DATA55 AD15
1000P_0402_25V8J
0.1U_0402_16V4Z
DDR_B_D54 AF16 AB15 DDR_A_D54
MB_DATA54 MA_DATA54
2
1 1 DDR_B_D53 AC18 AB17 DDR_A_D53
MB_DATA53 MA_DATA53
C151
C156
R90 DDR_B_D52 AF19 Y17 DDR_A_D52
1K_0402_1% DDR_B_D51 MB_DATA52 MA_DATA52 DDR_A_D51
AD14 MB_DATA51 MA_DATA51 Y14
DDR_B_D50 AC14 W14 DDR_A_D50
2 2 DDR_B_D49 MB_DATA50 MA_DATA50 DDR_A_D49
AE18 W16
1
DDR_B_D48 MB_DATA49 MA_DATA49 DDR_A_D48
AD18 MB_DATA48 MA_DATA48 AD17
PLACE CLOSE TO PROCESSOR DDR_B_D47 AD20 Y18 DDR_A_D47
DDR_B_D46 MB_DATA47 MA_DATA47 DDR_A_D46
WITHIN 1.5 INCH AC20 MB_DATA46 MA_DATA46 AD19
+CPU_M_VREF DDR_B_D45 AF23 AD21 DDR_A_D45
JP27B +0.9V DDR_B_D44 MB_DATA45 MA_DATA45 DDR_A_D44
AF24 MB_DATA44 MA_DATA44 AB21
DDR_A_CLK2 DDR_B_D43 AF20 AB18 DDR_A_D43
DDR_B_D42 MB_DATA43 MA_DATA43 DDR_A_D42
W17 M_VREF VTT1 D10 1