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A B C D E
SYSTEM DC/DC
Project code: 91.4J001.001--D45
D45/D46 Block Diagram
TPS51125 34
91.4K001.001--D46 INPUTS OUTPUTS
PCB P/N : 07248 DCBATOUT
5V_S5(5A)
3D3V_S5(5A)
REVISION : SA
CLK GEN.
Mobile CPU SYSTEM DC/DC
4 4
ICS9LPRS365YGLFT-GP Penryn G7921 TPS51124 36
20
3 PCB STACKUP INPUTS OUTPUTS
RTM875T-606-VD-GRT
4, 5 1D05V_M(11A)
TOP DCBATOUT
1D8V_S3(10A)
HOST BUS 667/800/[email protected] VCC
S RT9026 35
800/667MHz WXGA/SXGA+ S DDR_VREF_S0
DDR2 socket Cantiga LVDS
15"LCD 14 GND 1D8V_S3
(1.5A)
12,13
AGTL+ CPU I/F ATI BOTTOM
DDR_VREF_S3
DDR Memory I/F PCI-EG M82M RGB CRT
CRT G9131 35
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INTEGRATED GRAHPICS VRAMx4 256MB 13
800/667MHz LVDS, CRT I/F 41~47 3D3V_S0 2D5V_S0
DDR2 socket 71.CNTIG.00U 6,7,8,9,10,11
S-Video
S-Video
(300mA)
13
12,13 X4 DMI APL5912 35
3 C-Link0 3
400MHz 1D8V_S3 1D5V_S0
Headphone Out
Codec AZALIA
ALC269 ICH9M NB DC/DC
PCI-E/USB 2.0 New card G577 ISL6263A 37
29 6 PCIe ports
25
25
MIC In INPUTS OUTPUTS
PCI/PCI BRIDGE
ACPI 1.1 MS/MS Pro/
29 DCBATOUT GFX_CORE
4 SATA PCI-E USB Cardreader
INT.MIC JMICRO380 26 MMC/SD
12 USB 4 in 1 26
1394 CHARGER
29 BQ24745 38
High Definition Audio PCI-E
RJ45 INPUTS OUTPUTS
INT.SPKR LPC I/F LAN 23 TXFM24 24
2 Serial Peripheral I/F TRL8111C CHG_PWR 2
18V 4.0A
PCI-E /USB 2.0 DCBATOUT
Mini Card UP+5V
Kedron a/b/g/n 25 5V 100mA
PCI-E /USB 2.0 Mini Card
UMTS(3G) 25
MODEM 71.ICH9M.00U CPU DC/DC
RJ11 MDC Card 16,17,18,19
LPC BUS ISL6266A
22 33
SATA
USB0
USB
INPUTS OUTPUTS
SATA
SATA
KBC SPI I/F BIOS LPC
BlueTooth Winbond 4M byte DEBUG VCC_CORE_S0
22 DCBATOUT
WPC773 28 0~1.3V 47A
28 CONN. 27
1
USB
Touch INT.
Digitally signed by dd 1
HDD CDROM eSATA CAMERA Pad 27 KB 27
21 21
/USB 22 3 Port22 DN: cn=dd, o=dd, ou=dd,
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
14
Title
email=dddd@yahoo.
Taipei Hsien 221, Taiwan, R.O.C.
Size Document Number
com, c=US
BLOCK DIAGRAM
Rev
A3
Date: 2009.12.04
D45/D46
Date: Friday, March 14, 2008 Sheet
PD
1 of 47
A B C D 19:36:51 +07'00'
E
A B C D E
ICH9M Integrated Pull-up Cantiga chipset and ICH9M I/O controller
ICH9M Functional Strap Definitions Rev.1.5 page 92 Hub strapping configuration
Signal
ICH9 EDS 642879
Usage/When Sampled Comment
and Pull-down Resistors Montevina Platform Design guide 22339
page 218
0.5
ICH9 EDS 642879 Rev.1.5
HDA_SDOUT XOR Chain Entrance/ Allows entrance to XOR Chain testing when TP3 Pin Name Strap Description Configuration
PCIE Port Config1 bit1, pulled low.When TP3 not pulled low at rising edge SIGNAL Resistor Type/Value
Rising Edge of PWROK of PWROK,sets bit1 of RPC.PC(Config Registers: CL_CLK[1:0] PULL-UP 20K CFG[2:0] FSB Frequency 000 = FSB1067
Select 011 = FSB667
offset 224h). This signal has weak internal pull-down 010 = FSB800
CL_DATA[1:0] PULL-UP 20K
others = Reserved
4 HDA_SYNC PCIE config1 bit0,
Rising Edge of PWROK.
This signal has a weak internal pull-down.
Sets bit0 of RPC.PC(Config Registers:Offset 224h)
CL_RST0# PULL-UP 20K
CFG[4:3] Reserved
4
DPRSLPVR/GPIO16 PULL-DOWN 20K CFG8
GNT2#/ PCIE config2 bit2, This signal has a weak internal pull-up. CFG[15:14]
GPIO53 Rising Edge of PWROK. Sets bit2 of RPC.PC2(Config Registers:Offset 0224h) ENERGY_DETECT PULL-UP 20K CFG[18:17]
GPIO20 Reserved This signal should not be pulled high. HDA_BIT_CLK PULL-DOWN 20K
CFG5 DMI x2 Select 0 = DMI x2
GNT1#/ ESI Strap (Server Only) ESI compatible mode is for server platforms only. HDA_DOCK_EN#/GPIO33 PULL-UP 20K 1 = DMI x4 (Default)
GPIO51 Rising Edge of PWROK This signal should not be pulled low for desttop CFG6 iTPM Host 0= The iTPM Host Interface is enabled(Note2)
and mobile. HDA_RST# PULL-DOWN 20K Interface 1=The iTPM Host Interface is disalbed(default)
HDA_SDIN[3:0] PULL-DOWN 20K 0 = Transport Layer Security (TLS) cipher
Top-Block Sampled low:Top-Block Swap mode(inverts A16 for CFG7 Intel Management suite with no confidentiality
GNT3#/ Swap Override. all cycles targeting FWH BIOS space). HDA_SDOUT PULL-DOWN 20K engine Crypto strap 1 = TLS cipher suite with
GPIO55 Rising Edge of PWROK. Note: Software will not be able to clear the confidentiality (default)
Top-Swap bit until the system is rebooted HDA_SYNC PULL-DOWN 20K
0 = Reverse Lanes,15->0,14->1 ect..
without GNT3# being pulled down. GLAN_DOCK# The pull-up or pull-down active when configured for nativeCFG9 PCIE Graphics Lane 1= Normal operation(Default):Lane
GLAN_DOCK# functionality and determined by LAN controller Numbered in order
GNT0#: Boot BIOS Destination Controllable via Boot BIOS Destination bit GNT[3:0]#/GPIO[55,53,51] PULL-UP 20K
SPI_CS1#/ Selection 0:1. (Config Registers:Offset 3410h:bit 11:10). 0 = Enable (Note 3)
GPIO[20] PULL-DOWN 20K CFG10 PCIE Loopback enable 1= Disabled (default)
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GPIO58 Rising Edge of PWROK. GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC.
Integrated TPM Enable, Sample low: the Integrated TPM will be disabled. GPIO[49] PULL-UP 20K 00 = Reserve
Rising Edge of CLPWROK Sample high: the MCH TPM enable strap is sampled CFG[13:12] XOR/ALL 10 = XOR mode Enabled
SPI_MOSI low and the TPM Disable bit is clear, the LDA[3:0]#/FHW[3:0]# PULL-UP 20K 01 = ALLZ mode Enabled (Note 3)
11 = Disabled (default)
Integrated TPM will be enable.
LAN_RXD[2:0] PULL-UP 20K
3 DMI Termination Voltage, The signal is required to be low for desktop LDRQ[0] PULL-UP 20K
CFG16 FSB Dynamic ODT 0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled (Default) 3
Rising Edge of PWROK. applications and required to be high for
GPIO49 mobile applications. LDRQ[1]/GPIO23 PULL-UP 20K 0 = Normal operation(Default):
CFG19 DMI Lane Reversal Lane Numbered in Order
PME# PULL-UP 20K
1 = Reverse Lanes
PCI Express Lane Signal has weak internal pull-up. Sets bit 27 PWRBTN# PULL-UP 20K DMI x4 mode[MCH -> ICH]:(3->0,2->1,1->2and0->3)
SATALED# Reversal. Rising Edge of MPC.LR(Device 28:Function 0:Offset D8) DMI x2 mode[MCH -> ICH]:(3->0,2->1)
of PWROK. SATALED# PULL-UP 15K
SPKR No Reboot. If sampled high, the system is strapped to the SPI_CS1#/GPIO58/CLGPIO6 PULL-UP 20K Digital Display Port 0 = Only Digital Display Port
Rising Edge of PWROK. "No Reboot" mode(ICH9 will disable the TCO Timer (SDVO/DP/iHDMI) or PCIE is operational (Default)
system reboot feature). The status is readable SPI_MOSI PULL-DOWN 20K CFG20 Concurrent with PCIe 1 =Digital display Port and PCIe are
via the NO REBOOT bit. operting simulataneously via the PEG port
SPI_MISO PULL-UP 20K
0 =No SDVO Card Present (Default)
TP3 XOR Chain Entrance. This signal should not be pull low unless using SPKR PULL-DOWN 20K SDVO_CTRLDATA SDVO Present
Rising Edge of PWROK. XOR Chain testing. 1 = SDVO Card Present
TACH_[3:0] PULL-UP 20K
0 = LFP Disabled (Default)
GPIO33/ Flash Descriptor Sampled low:the Flash Descriptor Security will be TP[3] PULL-UP 20K Local Flat Panel
HDA_DOCK Security Override Strap overridden. If high,the security measures will be L_DDC_DATA (LFP) Present 1= LFP Card Present; PCIE disabled
_EN# Rising Edge of PWROK in effect.This should only be enabled in manufacturing USB[11:0][P,N] PULL-DOWN 15K
environments using an external pull-up resister. NOTE:
1. All strap signals are sampled with respect to the leading edge of
the (G)MCH Power OK (PWROK) signal.
2. iTPM can be disabled by a 'Soft-Strap' option in the
2 Flash-decriptor section of the Firmware. This 'Soft-Strap' is 2
activated only after enabling iTPM via CFG6.
Only one of the CFG10/CFG/12/CFG13 straps can be enabled at any time.
SMBus
SMBC_G792 Thermal
MXM
KBC
BAT_SCL
BATTERY
page 17
USB Table
PCI Routing USB
IDSEL INT REQ GNT Pair Device
G:CARDBUS 0 0 0 Combo(ESATA/USB)
TI7412 AD22 B:1394
F:Flash Media 1 NC
G:SD Host 2 USB2
SMB_CLK
3 USB4 LAN UMA
1 ICH9M 1
4 USB3
PCIE Routing 5 BLUETOOTH Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
6 WEBCAM Taipei Hsien 221, Taiwan, R.O.C.
LANE2 MiniCard WLAN 7 FT Title
SMBC_ICH CK505
LANE3 NewCard WLAN 8 MINICARD Reference
Size Document Number Rev
9 NEW1 DDR D45/D46 PD
Date: Friday, March 14, 2008 Sheet 2 of 47
A B C D E
A B C D E
3D3V_S0
3D3V_S0
3D3V_S0
3D3V_CLKGEN_S0 1 2
1 R582 3D3V_48MPWR_S0
2 3D3V_CLKPLL_S0 2 1 R2790R0603-PAD
1
1
1
1
1
1
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
0R0603-PAD R2820R0603-PAD C393 C719 C723 C703 C701 C397
SC4D7U6D3V3KX-GP
1
1
1
1
1
1
1
1
1
1
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C730 C721 EC110 C704 C400 C702 C724 C718 C722 C399
SC1U16V3ZY-GP
DY SC4D7U10V5ZY-3GP
2
2
2
2
2
2
SC4D7U10V5ZY-3GP
2
2
2
2
2
2
2
2
2
2
PD DY
4 4
U18
3D