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A B C D E




YUHINA Block Diagram SYSTEM DC/DC

INPU TS
MAX1999
OUTPU TS
33

4 Project code: 91.49V01.001 5V_S 5
4




Mobile CPU
5V_S 3
5V_S 0
PCB P/N : 48.49V01.0SC DCBATO UT
3D3V_S 5
3D3V_S 3
CLK GEN. Portability 3D3V_S 0
CY28346 Mobile P4 REVISION : 03207-SC 3D3V_LAN AC

SYSTEM DC/DC
3 4, 5 G768D CRT
MAX1 715 30
HOST BUS 133MHz 16 CONN CPU DC/DC INPU TS OUTP UTS
12
MAX1546ETL 31,32 2D5V_S 3

DDR*2 RGB CM2843ACIM25 31 DCBATO UT
1D5V_S 0

LVDS LCD
333MHz 266/33 3MHz GMCH XGA/S XGA+
INPU TS OUTP UTS
LP29 96 30
9,10 Montara-GT 11 DCBATO UT +VCC_ CORE
1.3V 44A
2D5V_S 3 1D25V_ S0

3 3

6,7,8 +VID
1.2V 0 .3A
HUB I/F 66MHz
MAXIM CHARGER
CARDBUS CARDBUS MAX1 645
PCI BUS
Line In PCI 1520 PWR SW TWO SLOT 34
Mic In 23 AC'97 AC-Link GHK TPS2224A
CODEC 25/B /1
INPU TS OUTP UTS
26
CS4299XQ 27 27
BT+
22
18V 4 .0A
DCBATO UT
UP+ 5V
ICH4-M 5V 10 0mA

2 2


LAN PCB LAYER
RTL 8101L L1: Signal 1
21/D /4 19,20
Mini-PCI L2: VCC/GN D
Line Out OP AMP
23 G1421 802.11A /B/G L3: Signa l 2
23
21
L4: Signal 3
LPC BUS
L5: GND
13,14,15
L6: Signal 4
MODEM+BT
SIDE




INT.SPKR MDC Card PIDE NS SIO KBC FWH LPC
23 18 M38857 4MB DEBUG
PC87392 PLCC 32 CONN.
1
CD ROM 28 25 SOIC 4024 24
Wistron Corporation
1




HDD 17 USB 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

17 4 PO RT18 Title
BLOCK DIAGRAM
PRN FIR Touch Size Document Number Rev
Port Pad INT KB Custom
SC
29 28 25 25 YUHINA
Date: Monday, April 28, 2003 Sheet 1 of 39

A B C D E
1D2V_VID 1D2V_VID 4,5,31

1D5V_S0 1D5V_S0 6,7,8,13,15,24,30,39

1D5V_S5 1D5V_S5 15,33


2D5V_S0 2D5V_S0 8,36

2D5V_S3 2D5V_S3 6,8,9,10,30,36




3D3V_S0 3D3V_S0 3,6,8,9,11,12,13,14,15,16,17,18,19,21,22,24,25,26,27,28,30,31,36,38,39

3D3V_S3 3D3V_S3 11,22,25,36,39

3D3V_S5 3D3V_S5 3,4,13,14,15,18,22,33,36,37,39

2D5V_LAN_S5 2D5V_LAN_S5 19

3D3V_LAN_S5 3D3V_LAN_S5 18,19,20,36

VCC_RTC_S5 VCC_RTC_S5 14



5V_USB1_S0 5V_USB1_S0 18

5V_USB3_S0 5V_USB3_S0 18


5V_CRT_S0 5V_CRT_S0 12

5VA_AUD_S0 5VA_AUD_S0 22,23,38

5V_S0 5V_S0 11,12,14,15,16,17,18,21,22,23,24,25,27,28,29,31,32,34,36,39

5V_S3 5V_S3 30,33,36,38

5V_S5 5V_S5 15,33


+5V_UP_S5 +5V_UP_S5 11,25,34,35,37,39

5V_AUX_S5 5V_AUX_S5 16,35,37,38,39



LCDVDD LCDVDD 11


AD+ AD+ 34,35,39



DCBATOU T DCBATOU T 11,30,32,33,34,36,37,39



ICH_VBIAS ICH_VBIAS 14

RTC_AUX_S5 RTC_AUX_S5 14




FAN1_VCC FAN1_VCC 16
PCI DEVICE RESOURCE ASSIGNMENT
BUS DEV ICE IDSE L PCI_R EQ# PCI_G NT# INT_I RQ# A_SKT_VCC_S0 A_SKT_VCC_S0 26,27

A_SKT_VPP_S0 A_SKT_VPP_S0 27




LAN 1 5 PCI_A D26 REQ# 4 GNT# 4 IRQ D#

Card Bus 1 9 PCI_A D20 REQ# 1 GNT# 1 IRQB#/IR QA#

Mini PCI 1 6 PCI_A D21 REQ# 2 GNT# 2 IRQ E#




Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Table of Content / HISTORY
Size Document Number Rev
A3
YUHINA SC
Date: Thursday, May 29, 2003 Sheet 2 of 39
RN5 SRN33-2-U2
VCCD_CKG CLKH_CPU 4
U19 1 4 R442
1 2 49D9R3F
2 3 R441
1 2 49D9R3F
8 52 CLK_CPU_1 CLKH_CPU# 4
14 VDDPCI CPUCLKT0 51 RN6 SRN33-2-U2
CLK_CPU#_1 CLKH_MCH 7
VDDPCI CPUCLKC0 1 4 R443
1 2 49D9R3F

13 CLKPCIF_ICH VCCA_CKG
50
46 VDDCPU
VDDCPU
CK-408 CPUCLKT1
CPUCLKC1
49
48
CLK_MCH_1
CLK_MCH#_1
2 3 R444
1 2 49D9R3F
CLKH_MCH# 7
VCCA_CKG48 26
37 VDDA
VDD48
V1.1 CPUCLKT2
CPUCLKC2
45
44
CLK_ITP_R_1
CLK_ITP#_R_1
RN7
1
2
SRN33-2-U2
4 CLKH_ITP
3 CLKH_ITP#
R445 1
R446 1
2 49D9R3F
2 49D9R3F
CLKH_ITP 4,5

32
VDD3V66 3D3V_S0 3D3V_S0 CLKH_ITP# 4,5
R155 19
1 2 33R2 1 VDD3V66 55 CKG_FS1_1
VDDREF FS1 SB




1



1
54 CKG_FS0
FS0 R628 R629
R156
1 2 33R2 TP70TPAD30 PCICLK_F0 5 DUMMY-R3 DUMMY-R3
26 PCLK_PCM PCICLK_F0 R449
CLKPCIF_ICH_1 6 Free running ** 39 CLK48_ICH_1 1 2 33R2
R157 PCICLK_F1 48MHZ_USB/FS2 CLK48_ICH 13
19 PCLK_LAN 1 2 33R2 PCLK_CBUS_1 7 * 38 R132
ASEL/PCICLK_F2 48MHZ_DOT 1 2 33R2
R158 CLK48_DREF_GMCH_1 CLK48_DAC 6




2



2
25 PCLK_KBC 1 2 33R2 ** 35 FS3
PCLK_LAN_1 10 3V66_1/VCH_CLK/FS3 33 FS4
1
R159
2 33R2 PCLK_KBC_1 11
PCICLK0 ** ** 3V66_0/FS4
ICS950813(PIN40->TESTPAD,R450->10K)
28 PCLK_SIO E_PCICLK1/PCICLK1 CY28346-2(PIN40->PL 10K TO GND,R450->DUMMY)
PCLK_SIO_1 12
PCICLK2
1 R160 2 33R2 13 ** * 43
24 PCLK_FWH PCLK_FWH_1
TP71TPAD30 PCICLK4 16 E_PCICLK3/PCICLK3 * MULTSEL 53
CK-408_MULT0
SB PM_STPCPU# 14,31
PCICLK4 CPU_STOP#
*
PCLK_MINI_1 17 40 FS2 1 2
LPC_DB_PCICLK_1 18 PCICLK5 *PWRSAVE# 34 R614 10KR2
R161 PCICLK6 PCI_STOP# PM_STPPCI# 14
21 PCLK_MINI 1 2 33R2
R162 42 IREF_1 2 R127 1 475R3F
1 2 33R2 IREF
24 PCLK_DEBUGBD CLK66_DREF_GMCH_1 21 56
CLK66_ICH_1 22 3V66_2 REF
R163 3V66_3
6 CLK66_MCH 1 2 33R2 CLK66_LVDS_1 23 CLK14_ICH_1 R130
1 2 10R2 CLK14_ICH 14
CLK66_AGP_1 24 3V66_4 R131
1 2 10R2
R164 3V66_5 CLK14_SIO 28
13 CLK66_ICH 1 2 33R2 4
R165 CKG-PD# 25 * GND 9
6 CLK66_LVDS
SB 1 2 22R2 SMBD_ICH 29
PD# GND
15 ICS950 813
SMBC_ICH 30 SDATA GND 20
R166 SCLK GND
TP10 TPAD30 CLK66_AGP 1 2 33R2 28 27
VTT_PWRGD# GND
SB R168 GND
47 Frequency Setting
3D3V_S0 1 2 CKG_CLKEN#_1BC39 41 CPU AGP PCI
1 2 CK-408_GEN_X1 2 GND 36
10KR3 X1 GND FS1/0 = 00 100.00MHz 66.67MHz 33.33MHz
3 31
X2 GND


1
SC10P50V2JN-1 2 FS1/0 = 01 133.33MHz 66.67MHz 33.33MHz
X1 R144 CY28346-2ZCT FS1/0 = 10 200.00MHz 66.67MHz 33.33MHz
9,14 SMBD_ICH SMBD_ICH FS1/0 = 11 166.66MHz 66.67MHz 33.33MHz
X-14D31818M-1 DUMMY-R3 * These inputs have 120K internal pull-u p resistor to VDD
1




SMBC_ICH BC38 CLK66_DREF_GMCH_1 1 2
9,14 SMBC_ICH
2


1 2 CK-408_GEN_X2 FS2 = 0 unbuffer mode (disable 66MHz-IN)
** Internal pull-down resi stors to ground
C523 DUMMY-C3 FS2 = 1 buffer mode
SC10P50V2JN-1 Placed within 500 Primary Source: ICS950813 TSSOP CLK66_ICH_1 1 2
No stuf f: mils of CK-408 Secondary Source: CY28346-2 TSSOP Mult0 = 0 Rr=221,Iref=5mA
caps a re C524 DUMMY-C3 =>[email protected]
2




R167 internal to CLK66_LVDS 1 2 Mult0 = 1 Rr=475,Iref=2.32mA
0R2-0 CK-TITA N. =>[email protected]
C525 DUMMY-C3
1




CLK66_AGP 1 2 CY283 46-2
If S1 doesn't support power down
14 CKG_CLKEN#
mode, this AND gate can be dummy 3D3V_S5 C526 DUMMY-C3
Frequency Setting
U18 3D3V_S0
1 5
CPU AGP PCI
14,15,22,25,30,33,36 PM_SLP_S3# A VCC FS1/0 = 00 66.00MHz 66.67MHz 33.33MHz
CLK48_ICH_1 1 2
14 PM_SLP_S1# 2 FS1/0 = 01 100.00MHz 66.67MHz 33.33MHz
B R450 DUMMY-10KR3
3 4 CKG-PD# FS1/0 = 10 200.00MHz 66.67MHz 33.33MHz
GND Y
FS1/0 = 11 133.33MHz 66.67MHz 33.33MHz
DUMMY-NC7SZ08-U
SB
3D3V_S0 FS2 = 0 unbuffer mode (disable 66MHz-IN)
R465 DUMMY-R3 FS2 = 1 buffer mode
1 2
1




R448 Mult0 = 0 Rr=221,Iref=5mA
10KR3 =>[email protected]
SB Mult0 = 1 Rr=475,Iref=2.32mA
2




CPU & MEMORY Freq . Selection Save two 4.7u F capacitor =>[email protected]
CK-408_MULT0
3D3V_S0 CPU BSEL1 BSEL0
1




VCCA_CKG 3D3V_S0
400MHz 0 0 R146
R447 1 2
DUMMY-R3 VCCA_CKG48 3D3V_S0
533MHz 0 1
1




1




1




2D2R5 R128 0R5
R135 R129 C518 C128 1 2
2




1KR3 1KR3 SCD1U16V SC10U6D3V5MX
SB
2




300 [email protected]
C504 C115
600mA
2




2




R125 0R3-0-U 3D3V_S0 SCD1U16V DUMMY-SC4D7U10V5ZY
CKG_FS1_1 1 2 VCCD_CKG
BSEL0 4,6
R133
CKG_FS0 1 2 1 2
0R5
1




R618 DUMMY-R3
C514 C503 C502 C505 C492
R126 SCD1U16V SCD1U16V SCD1U16V SCD1U16V DUMMY-SC4D7U10V5ZY
DUMMY-R3 CKG FS1 FS0
CY28346 300 [email protected] Wistron Corporation
100MHz 0 1 600mA 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
2