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XEROX
PALO ALTO RESEARCH CENTER
Systems Science Laboratory
LSI Systems Area
June 4, 1979
For Xerox Internal Use Only
To: NoteTaker Interest Group
From: Doug Fairbairn
Subject: Subsystems Analysis: NoteTaker I
stored: [ISIS]SAR.memo
This report is the collection point of an moans, groans, and gripes about the NoteTaker I system. If
there is something you want changed about the current NoteTaker design, be it physical or
electronic, and it isn't on this list, please send a message to "Resnick" (cc: Fairbairn) immediately.
Updated copies of this report will be available periodically. Comments are surely encouraged.
I. NoteTaker System
A. Physical characteristics
1. Size: 7" x 14" x 22" (2107 cu. in.)
2. \Veight: 40.5 lbs. wlo batteries; 48 lbs. wI batteries
3. Power Consumption:
a. +36v: ???
b. +43v: 400 rna.
c. + 12v: 2.65 amps (31.8 watts) wi disk running
1.3 amps (15.6 watts) wlo disk running
d. + 5v: 7.8 amps (39 watts) wi disk running
7.3 amps (36.5 watts) w/o disk running
C. - 20y: ???
4. Chip count: 387 including memory
307 logic only
5. Cost: $8700.00 or so...
B. What's wrong
2
1. Chips can faU out of board sockets
2. Can't plug boards into machine with power on.
3. The timing and loading of the system bus needs to be evaluated.
4. There is currently no serial number wired into the NT. On the Alto, this was
taken care of by wire-wrapping on the backplane. We don't have enough spare
pins on the NoteTaker. What should we do??
5. Power consumption numbers need to be verified.
C. What's right
D. Debugging problems
a. Field Maintenance
b. Untrained personnel
c. Test point accessiblity
d. Signature ananlysis?
E. Possible changes for NT2
1. New housing
2. Solder in 2 pins of each chip?
3. Use in-board socket pins?
4. Increase maintainability
3
II. Emulation processor
A. Physical characteristics
1. Size: 8.8" x 5.8" x 0.6" (30.6 cu. in.)
2. Weight: 12 oz.
3. Power Consumption:
a. + 5v: 900 rna. (4.5 watts)
4. Chip count: 56
a. Processor and support:
b. Boot interface logic:
c. Local memory control logic:
d. Parity error detection logic:
e. Local memory: 16 chips
f. Main memory control logic:
5. Cost: $624.00
B. What's wrong
1. Too big, too much power
2. The parity error flip flop can be reset by any good read of data.
3. Can the LEDs be used to better advantage?
4. The LEDs are not on a visible edge of the board.
5. The illegal address sensor may cause an interrupt too late and will not work if
there are other intermpts pending at the same time. Its output needs to be latched.
6. The design must be tested at 8 Mhz. to see if there are problems at this speed.
7.
C. \Vhat's right
1. Basically \'lorks.
D. Debugging problems
1. Doesn't have its own ROM so it requires a different debug board from the lOP.
2. ROM overlaps the address space in funny ways.
E. Possible modifications for NT2
1. TRy to get memory control logic into hybrid chip and put 2 processors on one
4
board.
2. Use 4816 style chips to allow EPROMs and RAM to be mixed.
3. Put PPI on board with 2 processors and allow either to talk to it. This would
mean no external debug board.
4. Do away with parity error logic if 2k x 8 RAMs are used.
5
III. IO Processor Nlodule
A. Physical characteristics
1. Size: 8.8" x 5.8" x 0.6" (30.6 cu. in.)
2. Weight: 12 oz.
3. Power Consumption:
a. +5v: 1500 rna. (7.5 watts)
b. -20v:
c. +12v:
4. Chip count: 58 dips
a. Processor/support: 10 chips
b. External interface: 0.5 chips
c. Boot logic: 4 chips
d. Ex ternal memory control: 16 chips
e. Local memory control: 7 chips
f. Keyboard interface: 5.0 chips
g. DAC: 10 chips = 22 discretes
h. Tablet drivers: 0.5 chips + 12 discretes
i. Voltage regulators: 3 chips
j. Misc.: 1 chip
5. Cost: $602.00
B. What's wrong
1. Too big, too much power
2. Reliability of power-on reset needs to be verified.
3. Can the ROM be left in high memory?
4. Can the keyboard UART be combined with the EIA UART
5. The DAC/S/H is too noisy
6. The DAC amplifier is not really optimized yet.
7. The output of the DAC needs a better filter
8. Are the voltage regulators doing OK? Arc they overloaded?
6
9. Is the way the stereo is controlled on the SIR the proper method? Can we do
better?
10. Do we need more or less control over the speed of the DAC?
11. \Ve would like to have a PPI type output from the lOP.
12. Board is too congested.
13. One of the regulator chips has too large of heat sink and this interferes with
neighboring boards.
14. The speaker should be a 45 ohm model so the low end frequency response is
better.
15. Does not work at 5 mhz.
16. The disk controller is the item which limits the speed of the current local
memory operations. This seems to be a waste in that the other things will run
much faster. This will be even truer in the future when high speed EPROMs
become available. We need to see if we can separare the timing of the UO
subsystem from that of the memory operations or perhaps get selected WD1791s or
????
C. What's right
1.
D. Debugging problems
1. How should we include signature analysis techniques?
2. What test points can be added to improve diagnosis?
E. Possible NT2 plans
1. May combine with EP
2. PPI on board
3. Hybrid module for memory control
7
IV. Disk/Display Module
A. Physical characteristics
1. Size: 8.8" x 5.8" x 0.6" (30.6 cu. in.)
2. Weight: 12 oz.
3. Power consumption:
a. +5v: 1400ma. (7.0 watts)
b. +12v:
c. -5v:
4. Chip count: 60
a. General support: 7
b. Disk Interface: 6 + 9 discretes
c. Display interface: 33
d. AID converter: 7 + 7 discretes
e. EIA interface: 7 + 7 discretes
5. Cost: $512.00
B. What's wrong?
1. Double density operation has not been proven yet.
2. Power switching to disk causes glitches - relays are a problem.
3. Don't have control over motor on without modifying disk drive.
4. Is the display controller the best we can do?
5. Speed range adequate on AID converter?
6. Is noise a problem on A/D convereter?
7. Can the same UART be used for the EIA interface and the keyboard interface?
8. Board is too congested
9. Too big, too much power.
10. Method of getting around false address select is a bit flaky on the display
controller
C. What's right?
1. Seems to fulfill basic functions
8
D. Debugging problems
1. Should it be possible to debug without processor attached?
2. What test points can be identified which will ease debug?
3. How can signature analysis be used effectively?
E. Possible NT2 modifications
1. LSI the display controller?
2. Combine the EIA interface and the keyboard interface into one UART.
3. Make the keyboard interface a true RS232 port with proper levels going out
the keyboard itself could still genereate standard TIL levels but its input would
have to' be modified slightly to accept EIA levels coming in.
4.
9
V. Memory Control module
A. Physical characteristics
1. Size: 8.8" x 5.8" x 0.6" (30.6 cu. in.)
2. Weight: 12 oz.
3. Power consumption:
a. + 5v: 1900 rna. (9.0 watts)
4. Chip count: 67
5. Cost: $409.00
B. What's wrong?
1. Too big, too much power
2. Does not seems to run smoothly over wide frequency range.
3. Have not proven error logging.
4. Is it as fast as it could be?
5. Error correction w/ procesor still needs to be checked.
6. Can't write bad syndromes to check error correction logic.
C. What's right:
1. Seems to work OK at 17 mhz.
D. Debugging problems
1. Timing is too complicated.
2. Need to identify test points or some special tools to aid debug. (signature
analysis?)
E. Possible changes for NT2:
1. Reduce size/power by moving some of the functions to the LSI chip and using
F series logic where Shottkey is now.
2. A total redesign may be necessary to simplify and make it compatible with LSI
chip.
10
VI. Memory Data module
A. Physical characteristics
1. Size: 8.8" x 5.8" x 0.6" (30.6 cu. in.)
2. Weight: 12 oz.
3. Power consumption:
a. +Sv: 980 rna. (4.9 watts)
4. Chip count: 48
5. Cost: $346.00
B. What's wrong?
1. Too big, too much power
2. Is it as fast as it could be?
3. Error correction w / procesor still needs to be checked.
4. Can't write bad syndromes to check error correction logic.
5.
C. vVhafs right:
1. Seems to work OK.
D. Debugging problems
E. Changes for NT2:
1. Replace with LSI chip.
11
VII. ~1emory