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8 7 6 5 4 3 2 1
MODEL : 8889 Revision 02 +3VA
VT8235
W83L950D
5uA
20mA
Contexts POWER STATES +CPU_CORE
CPU 30A
Title Page STATE
VOTAGE POWER ON
STR STD MEC-OFF +5V
USB PORT * 4 2A
COVER SHEET 1 (S3) (S4) (S5) REMARK
SIGNAL MIMIPCI 300mA
D
System Block Diagram 2 SUSB# - HIGH LOW LOW LOW CP2211 1A
D
Power Block Diagram 3 SUSC# - HIGH HIGH LOW LOW CRT 1A
+5VS HDD 1.5A
CPU-K8 (1/2) 4 ADP +19V O O O O ODD 1.8A
CPU-K8 (2/2) 5 BATTERY +12V O O O O MINIPCI 100mA
MDC 500mA
VIA K8N800 (1/2) 6 +5VA +5V O O O O TPA0212 1A
VIA K8N800 (2/2) 7 +3VA +3.3V O O O O ALC655 50mA
DDR_SODIMM (1/2) 8 +5VSB +5V O O O X +3VSB VT8235 160mA
DDR_SODIMM (2/2) 9 +3VSB +3.3V O O O X
Clock Generator/Buffer 10 +5V +5V O O X X +3V
CB1410 200mA
LVDS Transmitter VT1634 11 +3V +3.3V O O X X
VT6103L 130mA
Display CRT / LCD 12 +2.5V +2.5V O O X X MIMIPCI 380mA
TV Encoder VT1623M 13 +1.25V +1.25V O O X X
CP2211 1A
VT8235CE (1/3) 14 K8N800 400mA
+5VS +5V O X X X +3VS
VT8235CE (2/3) 15 CLK_GEN 360mA
C C
+3VS +3.3V O X X X LCDVCC 1A
VT8235CE (3/3) 16 VT8235 15mA
IDE INTERFACE 17 +2.5VS +2.5V O X X X CB1410 15mA
ALC655 200mA
USB 18 +2.5VDDA +2.5V O X X X LPC BIOS ROM 15mA
ENE CB1410 19 +1.5VS +1.5V O X X X VT6103L 10mA
MIMIPCI 430mA
LAN (VT6103) & MDC 20 +1.2VLDTA +1.2V O X X X W83L950D 20mA
MiNi-PCI 21 +CPU_CORE +1.2V O X X X
+2.5VSB VT8235 6mA
Audio CODEC ALC655 / AMP TPA0212 22
CPU 3A
KBC (W83L950D) 23 IDSEL I2C / SMB Address +2.5V DDR_DIMM 4A
BIOS / TP / HOLE 24 IDSEL CHIP
DEVICE WRITE ADDRESS READ ADDRESS
ADP IN & BATT IN 25 AD20 CardBus +2.5VS
VT8235 400mA
CLK GEN D2 D3
+5V,+3V 26 AD21 MiniPCI VT1634 44mA
DIMM0 A0 A1
+2.5V,+1.25VS 27
DIMM1 A2 A3
+5VS,+3VS,+2.5VS,+1.5VS,+2.5VDDA,+1.2VLDTA 28 K8N800
G781 98 99 +1.5VS
1A
B
+CPU_CORE 29 B
Charger 30 +1.25V DDR_DIMM
1A
History 31
BUS MASTER +1.2VLDT K8N800 200mA
REQ/GNT CHIP CPU 500mA
-REQ0/-GNT0 CardBus
-REQ1/-GNT1
-REQ2/-GNT2 MINI PCI
-REQ3/-GNT3
Board Stackup-up
COMP
PCIINT GND
PCIINT CHIP IN-1
DRAW DESIGN CHECK ISSUED INTA#
INTB#
VGA
CardBus
IN-2/GND
INTC# MiniPCI POWER
INTD# MiniPCI IN-3
INTE#
[email protected]
A GND A
SOLDER
Title
COVER SHEET
Size Document Rev
R02
Number 316685200002
Date: Monday, August 23, 2004 Sheet 1 of 30
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
8889 SYSTEM BLOCK DIAGRAM
200 Pin DDR SO-DIMM Socket*2
DDR SO-DIMM
D AMD Mobile K8 DDR SDRAM PC2100/PC2700/PC3200
D
Memory Bus 266/333/400MHz
CPU
uFCBGA 754 pin
VT1623M Hyper
TV-OUT Transport
TV Encoder
VT1634
VIA K8N800
C
TFT LCD LVDS Transmitter
C
NB
Mini-PCI socket BGA 587 pin
Type III A
124pin CRT
V-Link interface
PCI interface MII interface VT6103L
RJ45
VT 8235 CE SSOP 48
SB AC' link
E-IDE MDC RJ11
IC CARD BGA 539 pin
Socket Type
B ENE CB1410 II X 1 B
PCMCIA ALC655
LPC interface Audio Codec External
PQFP 48 Microphone
PQFP 144 CP2211 USB 2.0
Power Switch BIOS
SSOP 16
PLCC 32
External 8 OHM
TPA0212 Speaker 1W
Cover Switch Audio Amplifier
Primery EIDE
(HDD) TSSOP 28 Internal
Speaker
KeyBoard
Secondary EIDE (DVD 26PIN
COMBO /DVD-R/RW)
W83L950D
A
Touch PAD A
TQFP100
Power Button
Fan
Title
System Block DIAGRAM
Size Document Rev
R02
Number 316685200002
Date: Monday, August 23, 2004 Sheet 2 of 30
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
+5VA +3VA
POWER BLOCK DIAGRAM OF THE 8889
LDO LDO
LP2951-02BM TC55RP3302EMB
D D
+3VS +1.2VLDTA
Diode PWR_ON +3VSB
MOSFET LDO
Protector SI4778CY AME8824
3.3V&5V +5VSB +5VS
Self- Diode DC to DC Convertor MOSFET
ADAPTOR discharge I_Limit SI4778CY +2.5VS
Rsense Protector LTC3728L
SWITCH
MOSFET PG_CPU_CORE
MAINPWR SI4778CY +VCC_CORE
learning Vcc Core
C C
DC to DC Convertor
Discharge Adaptor / Battery
Change MAX1937
Battery Switch DVMAIN PG_2.5VDDA +2.5VDDA
Pack
+3V LDO
+2.5VSB
MOSFET AME8804AEEY
+2.5VSB +1.5VS
SI4778CY
DC to DC Convertor +5V LDO
SC1470 G965
MOSFET
SI4778CY +2.5V
+1.25V
Charge
SUSC#
B
MOSFET LDO B
SI4778CY LP2996
ADINP High
Low Choke Rsense
Side
W83L950D ADINP_2 Li-ovp
Charging current sense
ADINP_1 PWM
Charging current sense Diode
[email protected]
A
I_LIMIT Charge IC A
A/D MAX1772 Protector
ADEN#
CC setting by SUSC#
D/A(but on/off only) CHG_ON SUSC# L: Ichg=2A
SUSC# H: Ichg=1A Title
Power Block Diagram
Size Document Rev
R02
Number 316685200002
Date: Monday, August 23, 2004 Sheet 3 of 30
8 7 6 5 4 3 2 1
5 4 3 2 1
CPU-K8(1/2)
CPU_MD[0..63]
CPU_MD[0..63] [8]
U507A MEMADD_A[0..13] U507B
[8,9] MEMADD_A[0..13]
CPUCK+ AJ21 Y27 L0_CLKIN_H0 MEMADD_A0 N5 AJ16 CPU_MD0
CLKIN_H L0_CLKIN_H[0] L0_CLKIN_H0 [6] MEMADDA[0] MEMDATA[0]
CPUCK- AH21 Y25 L0_CLKIN_H1 MEMADD_A1 T3 AJ14 CPU_MD1
CLKIN_L L0_CLKIN_H[1] L0_CLKIN_H1 [6] MEMADDA[1] MEMDATA[1]
TP22 1 B23 Y28 L0_CLKIN_L0 MEMADD_A2 T5 AJ12 CPU_MD2
CORE_SENSE L0_CLKIN_L[0] L0_CLKIN_L0 [6] MEMADDA[2] MEMDATA[2]
REFB_H A23 W25 L0_CLKIN_L1 MEMADD_A3 V5 AG11 CPU_MD3
[29] COREFB_H COREFB_H L0_CLKIN_L[1] L0_CLKIN_L1 [6] MEMADDA[3] MEMDATA[3]
REFB_L A24 J29 L0_CLKOUT_H0 MEMADD_A4 Y3 AJ15 CPU_MD4
[29] COREFB_L COREFB_L L0_CLKOUT_H[0] L0_CLKOUT_H0 [6] MEMADDA[4] MEMDATA[4]
DBRDY AH17 J26 L0_CLKOUT_H1 MEMADD_A5 AB4 AH15 CPU_MD5
D DBRDY L0_CLKOUT_H[1] L0_CLKOUT_H1 [6] MEMADDA[5] MEMDATA[5] D
DBREQ# AE19 K29 L0_CLKOUT_L0 MEMADD_A6 Y5 AJ11 CPU_MD6
DBREQ_L L0_CLKOUT_L[0] L0_CLKOUT_L0 [6] MEMADDA[6] MEMDATA[6]
width:20/8/5/8/20 R561 2 1 80.6 AH19 J27 L0_CLKOUT_L1 MEMADD_A7 AD3 AH11 CPU_MD7
FBCLKOUT_H L0_CLKOUT_L[1] L0_CLKOUT_L1 [6] MEMADDA[7] MEMDATA[7]
0603 1% AJ19 T29 L0_CTLIN_H0 MEMADD_A8 AB5 AJ10 CPU_MD8
R345 must be <1" FBCLKOUT_L L0_CTLIN_H[0] L0_CTLIN_H0 [6] MEMADDA[8] MEMDATA[8]
AJ28 R27 L0_CTLIN_H1 MEMADD_A9 AE5 AJ9 CPU_MD9
KEY0 L0_CTLIN_H[1] L0_CTLIN_L0 MEMADD_A10 MEMADDA[9] MEMDATA[9] CPU_MD10
from CPU A28 KEY1 L0_CTLIN_L[0] R29 L0_CTLIN_L0 [6] M5 MEMADDA[10] MEMDATA[10] AH5
R26 L0_CTLIN_L1 MEMADD_A11 AF3 AG5 CPU_MD11
L0_CADIN_H[0..15] L0_CTLIN_L[1] L0_CTLOUT_H0 MEMADD_A12 MEMADDA[11] MEMDATA[11] CPU_MD12
[6] L0_CADIN_H[0..15] L0_CTLOUT_H[0] P28 L0_CTLOUT_H0 [6] AE6 MEMADDA[12] MEMDATA[12] AH9
L0_CADIN_H0 AD27 N25 L0_CTLOUT_H1 1 TP21 MEMADD_A13 E10 AJ7 CPU_MD13
L0_CADIN_H1 L0_CADIN_H[0] L0_CTLOUT_H[1] L0_CTLOUT_L0 MEMADD_B[0..13] MEMADDA[13] MEMDATA[13] CPU_MD14
AD29 L0_CADIN_H[1] L0_CTLOUT_L[0] P27 L0_CTLOUT_L0 [6] [8,9] MEMADD_B[0..13] MEMDATA[14] AJ6
L0_CADIN_H2 AB27 P25 L0_CTLOUT_L1 1 TP20 MEMADD_B0 M3 AJ5 CPU_MD15 DDR_CLK5 DDR_CLK4
L0_CADIN_H3 L0_CADIN_H[2] L0_CTLOUT_L[1] MEMADD_B1 MEMADDB[0] MEMDATA[15] CPU_MD16
AB29 L0_CADIN_H[3] T4 MEMADDB[1] MEMDATA[16] AJ3
1
1
L0_CADIN_H4 Y29 AE26 L0_REF0 MEMADD_B2 U5 AH3 CPU_MD17
L0_CADIN_H5 L0_CADIN_H[4] L0_REF0 L0_REF1 MEMADD_B3 MEMADDB[2] MEMDATA[17] CPU_MD18 R164 R163
V27 L0_CADIN_H[5] L0_REF1 AF27 W5 MEMADDB[3] MEMDATA[18] AF1
L0_CADIN_H6 V29 AJ27 R112 1 0/NA 2 0402 LDTSTOP# MEMADD_B4 Y4 AE2 CPU_MD19 120 120
L0_CADIN_H[6] LDTSTOP_L LDTSTOP# [16] MEMADDB[4] MEMDATA[19] 0402 0402
L0_CADIN_H7 T27 R109 1 2 0402 LDTSTOP_NB# MEMADD_B5 AB3 AJ4 CPU_MD20
L0_CADIN_H[7] LDTSTOP_NB# [6] MEMADDB[5] MEMDATA[20]
L0_CADIN_H8 AD25 A19 BRN# 0 MEMADD_B6 AA5 AG3 CPU_MD21
L0_CADIN_H9 L0_CADIN_H[8] NC_A19 MEMADD_B7 MEMADDB[6] MEMDATA[21] CPU_MD22 DDR_CLK5# DDR_CLK4#
2
2
AC27 L0_CADIN_H[9] NC_A25 A25 AD4 MEMADDB[7] MEMDATA[22] AE3
L0_CADIN_H10 AB25 AA2 MEMADD_B8 AC5 AE1 CPU_MD23
L0_CADIN_H11 L0_CADIN_H[10] NC_AA2 MEMADD_B9 MEMADDB[8] MEMDATA[23] CPU_MD24
AA27 L0_CADIN_H[11] NC_AA3 AA3 AD5 MEMADDB[9] MEMDATA[24] AD1
L0_CADIN_H12 W27 AE21 For REV. Ax only MEMADD_B10 M4 AC2 CPU_MD25
L0_CADIN_H13 L0_CADIN_H[12] NC_AE21 MEMADD_B11 MEMADDB[10] MEMDATA[25] CPU_MD26 DDR_CLK7 DDR_CLK6
V25 L0_CADIN_H[13] NC_AE22 AE22 AF4 MEMADDB[11] MEMDATA[26] Y1
L0_CADIN_H14 U27 AE23 R121 1 1K/NA2 0402 MEMADD_B12 AF6 W2 CPU_MD27
L0_CADIN_H[14] NC_AE23 MEMADDB[12] MEMDATA[27]
1
1
L0_CADIN_H15 T25 AE24 1 TP19 MEMADD_B13 E9 AC3 CPU_MD28
L0_CADIN_H[15] NC_AE24 MEMADDB[13] MEMDATA[28] CPU_MD29 R167 R152
NC_AE9 AE9 MEMDATA[29] AC1
L0_CADIN_L[0..15] L0_CADIN_L0 AD28 AF18 R111 1 0 2 0402 DDR_BAA0 H3 W3 CPU_MD30 120 120
[6] L0_CADIN_L[0..15] L0_CADIN_L[0] NC_AF18 +2.5V [8,9] DDR_BAA0 DDR_BAA1 MEMBANKA[0] MEMDATA[30] 0402 0402
L0_CADIN_L1 AC29 AF21 R125
1 1K/NA2 0402 K3 W1 CPU_MD31
L0_CADIN_L[1] NC_AF21 [8,9] DDR_BAA1 DDR_BAB0 MEMBANKA[1] MEMDATA[31]
L0_CADIN_L2 AB28 AF22 R124 1 1K/NA2 0402 J5 M1 CPU_MD32
L0_CADIN_L[2] NC_AF22