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5 4 3 2 1

Digitally signed by
fdsf
DN: cn=fdsf, o=fsdfsd,
ou=ffsdf,
email=fdfsd@fsdff,
D D

c=US
Date: 2010.02.15
18:47:35 +07'00'

C Mini (EFL50) ATI VGA/B M52-P C

www.kythuatvitinh.com
Revision 1.0

B B

A A

Security Classification Compal Secret Data
Title
Compal Electronics, Inc.
Issued Date 2005/12/22 Deciphered Date 2006/12/22
Cover Sheet
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS EFL50 LS-2766P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 12/23/05 14:40:19 Sheet 1 of 13
5 4 3 2 1
5 4 3 2 1

M54P/M52P BLOCK DIAGRAM
GDDR1
8M*32
D
DDRA MDA[0:63]
M54P/M52P PCIE D

DQ[0:31]
DQA[0:63] Connector
NMAA[0:13] PCIE_MTX_C_GRX_P[0:15], PCIE_MTX_C_GRX_N[0:15]
MAA[0:13] PCIE_TX[0:15]P, PCIE_TX[0:15]N
A[0:11] PCIE_GT_MRX_P[0:15], PCIE_GTX_MRX_N[0:15]
PCIE_RX[0:15]P, PCIE_RX[0:15]N
K4D553235F-GC2A

PCIE_REFCLKP, PCIE_REFCLKN CLK_PCIE_VGA CLK_PCIE_VGA# PLTRST_VGA#
PWRGD
Samsung

DVI_TXD[0:2](+,-); DVI_TXC+(-)
NMCLKA0/A0# CLKA[0:1] DVI
CLK/CLK# NMCLKA1/A1# CLKA[0:1]#
PAGE 8 VGA_TV_LUMA,VGA_TV_CRMA
TV_OUT

VGA_CRT_R, VGA_CRT_G, VGA_CRT_B, DACA_HSYNC, DACA_VSYNC
VGA_OUT
8M*32 VGA_DDC_CLK, VGA_DDC_DAT
DDRB MDB[0:63]
DDC1_I2C
MDB[0:63]
DQ[0:31]
NMAB[0:13]
NMAB[0:13]
C A[0:11] C
K4D553235F-GC2A

LVDS Bus
I2CC_SCL
DVPDATA[18:19]
I2CC_SDA
Samsung

NMCLKB0/B0# CLKB[0:1]
CLK/CLK# NMCLKB1/B1# CLKB[0:1]#
DIGON VGA_ENVDD
PAGE 9

BLON VGA_ENBKL
27MHz
OSC_IN +1.2VS +1.5VS +1.5VS
SPREAD PCIE_VDDR
+1.2VS
APW7057KC-TR +5VS +5VS
CLOCK OSC_SPREAD PCIE_PVDD PAGE 11
B+
ASM3P1819N-SR
PAGE 4 +3VS
B B
+1.8VS
ACES 88069-1600A
+2.5VS
PAGE 3
D+/D-
THERMAL +VDD_CORE +VDD_CORE B+
SENSOR THERM_SDA, THERM_SCL
VDDC
GPIO5 POWER_SEL SL6225BCA-T
PAGE 11
MAX6649MUA THER_ALERT
GPIO_AUXWIN
PAGE 4
+3.3VS
VDDR3
VDDR4
VDDR5

+1.8VS
VDDR1

VDD25, LVDDR, +2.5VS
TXVDDR, AVDD,
A A
A2VDD
PAGE 4,5,6,7

Security Classification Compal Secret Data
Title
Compal Electronics, Inc.
Issued Date 2005/12/22 Deciphered Date 2006/12/22
Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS EFL50 LS-2766P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 12/23/05 14:40:19 Sheet 2 of 13
5 4 3 2 1
5 4 3 2 1

PCIE_GTX_MRX_P[0:15]
PCIE_GTX_MRX_P[0:15] <4>
PCIE_GTX_MRX_N[0:15]
PCIE_GTX_MRX_N[0:15] <4>

PCIE_MTX_C_GRX_P[0:15]
PCIE_MTX_C_GRX_P[0:15] <4>
PCIE_MTX_C_GRX_N[0:15]
PCIE_MTX_C_GRX_N[0:15] <4>

161
D JP1 D
VGA_CRT_R 2 1

G1
<4> VGA_CRT_R 2 1 B+
VGA_CRT_G 4 3
<4> VGA_CRT_G 4 3
VGA_CRT_B 6 5
<4> VGA_CRT_B 6 5
CRT_VSYNC 8 7
<4> CRT_VSYNC 8 7
CRT_HSYNC 10 9
<4> CRT_HSYNC 10 9
12 12 11 11
PCIE_MTX_C_GRX_P0 14 13 VGA_TV_Y
14 13 VGA_TV_Y <4>
PCIE_MTX_C_GRX_N0 16 15 VGA_TV_C
16 15 VGA_TV_C <4>
18 17 VGA_TV_COMP
18 17 VGA_TV_COMP <4>
PCIE_MTX_C_GRX_P1 20 19
PCIE_MTX_C_GRX_N1 20 19 PCIE_GTX_C_MRX_P0
22 22 21 21 C2 1 2 0.1U_0402_16V4Z PCIE_GTX_MRX_P0
24 23 PCIE_GTX_C_MRX_N0 C3 1 2 0.1U_0402_16V4Z PCIE_GTX_MRX_N0
PCIE_MTX_C_GRX_P2 24 23
26 26 25 25
PCIE_MTX_C_GRX_N2 28 27 PCIE_GTX_C_MRX_P1 C4 1 2 0.1U_0402_16V4Z PCIE_GTX_MRX_P1
28 27 PCIE_GTX_C_MRX_N1 C5 0.1U_0402_16V4Z PCIE_GTX_MRX_N1
30 30 29 29 1 2
PCIE_MTX_C_GRX_P3 32 31
PCIE_MTX_C_GRX_N3 32 31 PCIE_GTX_C_MRX_P2
34 34 33 33 C6 1 2 0.1U_0402_16V4Z PCIE_GTX_MRX_P2
36 35 PCIE_GTX_C_MRX_N2 C7 1 2 0.1U_0402_16V4Z PCIE_GTX_MRX_N2
PCIE_MTX_C_GRX_P4 36 35
38 38 37 37
PCIE_MTX_C_GRX_N4 40 39 PCIE_GTX_C_MRX_P3 C8 1 2 0.1U_0402_16V4Z PCIE_GTX_MRX_P3
40 39 PCIE_GTX_C_MRX_N3 C9 0.1U_0402_16V4Z PCIE_GTX_MRX_N3
42 42 41 41 1 2
PCIE_MTX_C_GRX_P5 44 43
PCIE_MTX_C_GRX_N5 44 43 PCIE_GTX_C_MRX_P4
46 46 45 45 C10 1 2 0.1U_0402_16V4Z PCIE_GTX_MRX_P4
48 47 PCIE_GTX_C_MRX_N4 C11 1 2 0.1U_0402_16V4Z PCIE_GTX_MRX_N4
PCIE_MTX_C_GRX_P6 48 47
50 50 49 49
PCIE_MTX_C_GRX_N6 52 51 PCIE_GTX_C_MRX_P5 C12 1 2 0.1U_0402_16V4Z PCIE_GTX_MRX_P5
52 51 PCIE_GTX_C_MRX_N5 C13 0.1U_0402_16V4Z PCIE_GTX_MRX_N5
54 54 53 53 1 2
PCIE_MTX_C_GRX_P7 56 55
PCIE_MTX_C_GRX_N7 56 55 PCIE_GTX_C_MRX_P6
C 58 58 57 57 C14 1 2 0.1U_0402_16V4Z PCIE_GTX_MRX_P6 C
60 59 PCIE_GTX_C_MRX_N6 C15 1 2 0.1U_0402_16V4Z PCIE_GTX_MRX_N6
PCIE_MTX_C_GRX_P8 60 59
62 62 61 61
PCIE_MTX_C_GRX_N8 64 63 PCIE_GTX_C_MRX_P7 C16 1 2 0.1U_0402_16V4Z PCIE_GTX_MRX_P7
64 63 PCIE_GTX_C_MRX_N7 C17 0.1U_0402_16V4Z PCIE_GTX_MRX_N7
66 65 1 2

www.kythuatvitinh.com
PCIE_MTX_C_GRX_P9 66 65
68 68 67 67
PCIE_MTX_C_GRX_N9 70 69 PCIE_GTX_C_MRX_P8 C18 1 2 0.1U_0402_16V4Z PCIE_GTX_MRX_P8
70 69 PCIE_GTX_C_MRX_N8 C19 0.1U_0402_16V4Z PCIE_GTX_MRX_N8
72 72 71 71 1 2
PCIE_MTX_C_GRX_P10 74 73
PCIE_MTX_C_GRX_N10 74 73 PCIE_GTX_C_MRX_P9
76 76 75 75 C20 1 2 0.1U_0402_16V4Z PCIE_GTX_MRX_P9
78 77 PCIE_GTX_C_MRX_N9 C21 1 2 0.1U_0402_16V4Z PCIE_GTX_MRX_N9
PCIE_MTX_C_GRX_P11 78 77
80 80 79 79
PCIE_MTX_C_GRX_N11 82 81 PCIE_GTX_C_MRX_P10 C22 1 2 0.1U_0402_16V4Z PCIE_GTX_MRX_P10
82 81 PCIE_GTX_C_MRX_N10 C23 0.1U_0402_16V4Z PCIE_GTX_MRX_N10
84 84 83 83 1 2
PCIE_MTX_C_GRX_P12 86 85
PCIE_MTX_C_GRX_N12 86 85 PCIE_GTX_C_MRX_P11 C24
88 88 87 87 1 2 0.1U_0402_16V4Z PCIE_GTX_MRX_P11
90 89 PCIE_GTX_C_MRX_N11 C25 1 2 0.1U_0402_16V4Z PCIE_GTX_MRX_N11
PCIE_MTX_C_GRX_P13 90 89
92 92 91 91
PCIE_MTX_C_GRX_N13 94 93 PCIE_GTX_C_MRX_P12 C26 1 2 0.1U_0402_16V4Z PCIE_GTX_MRX_P12
94 93 PCIE_GTX_C_MRX_N12 C27 0.1U_0402_16V4Z PCIE_GTX_MRX_N12
96 96 95 95 1 2
PCIE_MTX_C_GRX_P14 98 97
PCIE_MTX_C_GRX_N14 98 97 PCIE_GTX_C_MRX_P13 C28
100 100 99 99 1 2 0.1U_0402_16V4Z PCIE_GTX_MRX_P13
102 101 PCIE_GTX_C_MRX_N13 C29 1 2 0.1U_0402_16V4Z PCIE_GTX_MRX_N13
PCIE_MTX_C_GRX_P15 102 101
104 104 103 103
PCIE_MTX_C_GRX_N15 106 105 PCIE_GTX_C_MRX_P14 C30 1 2 0.1U_0402_16V4Z PCIE_GTX_MRX_P14
106 105 PCIE_GTX_C_MRX_N14 C31 0.1U_0402_16V4Z PCIE_GTX_MRX_N14
108 108 107 107 1 2
VGA_CRT_CLK 110 109
<4> VGA_CRT_CLK VGA_CRT_DAT 110 109 PCIE_GTX_C_MRX_P15 C32
<4> VGA_CRT_DAT 112 112 111 111 1 2 0.1U_0402_16V4Z PCIE_GTX_MRX_P15
114 113 PCIE_GTX_C_MRX_N15 C33 1 2 0.1U_0402_16V4Z PCIE_GTX_MRX_N15
B 114 113 B
<5> DVI_TXC+ 116 116 115 115
<5> DVI_TXC- 118 118 117 117
<5> DVI_TX0+ 120 120 119 119
<5> DVI_TX0- 122 122 121 121 VGA_DVI_DET <5>
124 123 VGA_DVI_CLK
124 123 VGA_DVI_DAT VGA_DVI_CLK <5>
<5> DVI_TX1+ 126 126 125 125 VGA_DVI_DAT <5>
128 127 DAC_BRIG
<5> DVI_TX1- 128 127 DAC_BRIG <10>
130 129 DISPOFF#
<5> DVI_TX2+ 130 129 DISPOFF# <10>
132 131 INVT_PWM
<5> DVI_TX2- 132 131 INVT_PWM <10>
134 133 PCIE_RST#
134 133 PCIE_RST# <4>
<4> CLK_PCIE_VGA 136 136 135 135 susp# <10,11>
138 137 VGA_ENBKL TP7
<4> CLK_PCIE_VGA# 138 137 VGA_ENBKL <4>
140 139 LCD_ID#
140 139 LCD_ID# <10>
+5VALW 142 142 141 141 +1.5VS
144 144 143 143
146 146 145 145 +3VS_D
148 148 147 147
+2.5VS 150 150 149 149
152 152 151 151 +1.8VS_D
+1.8VS_D 154 154 153 153
156 156 155 155
158 158 157 157
G2

160 160 159 159

ACES_88396-1G41
162

A A

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/12/22 Deciphered Date 2006/12/22 Title
VGA Connector PCIE Connector
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom EFL50 LS-2766P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 12/23/05 14:40:19 Sheet 3 of 13
5 4 3 2 1
5 4 3 2 1

PCIE_GTX_MRX_P[0:15] U2A +3VS
<3> PCIE_GTX_MRX_P[0:15] Straps: (Internal pull down)
PCIE_GTX_MRX_N[0:15] CLK_PCIE_VGA AL28 AD4 R63 1 2 @ 10K_0402_5% Transmitter power GPIO[0] 0: 50% TX output swing
<3> PCIE_GTX_MRX_N[0:15] <3> CLK_PCIE_VGA PCIE_REFCLKP GPIO_0
CLK_PCIE_VGA# AK28 AD2 R14 1 2 10K_0402_5%
<3> CLK_PCIE_VGA# PCIE_REFCLKN GPIO GPIO_1
GPIO_2 AD1
saving enable 1: Full TX output swing
PCIE_GTX_MRX_P0 AK27 AD3 Transmitter GPIO[1] 0: TX de-emphasis disable
PCIE_MTX_C_GRX_P[0:15] PCIE_TX0P GPIO_3
<3> PCIE_MTX_C_GRX_P[0:15]
PCIE_GTX_MRX_N0 AJ27 PCIE_TX0N GPIO_4 AC1 R13 1 2 @ 10K_0402_5% de-emphasis enable 1: TX de-emphasis enable
PCIE_GTX_MRX_P1 AJ25 AC2 R80 1 2 10K_0402_5%
PCIE_MTX_C_GRX_N[0:15] PCIE_GTX_MRX_N1 PCIE_TX1P GPIO_5
<3> PCIE_MTX_C_GRX_N[0:15] AH25 PCIE_TX1N GPIO_6 AC3 Debug Access GPIO[4] 0: OFF
PCIE_GTX_MRX_P2 AH28 AB2 VGA_ENBKL
PCIE_TX2P GPIO_7_BLON VGA_ENBKL <3> 1: ON
PCIE_GTX_MRX_N2 AG28 PCIE_TX2N GPIO_8 AC6 R16 1 2 10K_0402_5%
PCIE_GTX_MRX_P3 AG27 AC5 GPIO9 Current bias for GPIO[5] GPIO5 = 1
PCIE_GTX_MRX_N3 PCIE_TX3P GPIO_9 TP4 the PCI Express PHY PLL (must be pulled to 3.3V at reset using)
D AF27 PCIE_TX3N GPIO_10 AC4 D
PCIE_GTX_MRX_P4 AF25 AB3 GPIO11
PCIE_GTX_MRX_N4 PCIE_TX4P GPIO_11 GPIO12
AE25 AB4 ROM ID Config GPIO[9, GPIO[9]=1 External ROM Attached
PCI-Express Data Bus Lane Reversal and Polarity Inversion

PCIE_GTX_MRX_P5 PCIE_TX4N GPIO_12 GPIO13
PCIE_GTX_MRX_N5
AE28 PCIE_TX5P GPIO_13 AB5 13:11] GPIO[9]=0 No External ROM
AD28 PCIE_TX5N GPIO_14 AD5
PCIE_GTX_MRX_P6 AD27 AB8 POWER_SEL For No External ROM:
PCIE_TX6P GPIO_15 POWER_SEL <11>
PCIE_GTX_MRX_N6 AC27 AA8 OSC_SPREAD GPIO[13,12] is for MEM_AP_SIZE[1,0]
PCIE_GTX_MRX_P7 PCIE_TX6N GPIO_16 THER_ALERT# (Internal
AC25 AB7 GPIO[11] don't care
PCIE_GTX_MRX_N7 PCIE_TX7P GPIO_17 Pull-down)
AB25 PCIE_TX7N NC AB6
PCIE_GTX_MRX_P8 AB28 PCIE_TX8P
R53 2 1 499_0402_1% +3VS
PCIE_GTX_MRX_N8 AA28 PCIE_TX8N VREFG AC8 R54 1 2 499_0402_1% VIP_DEVICE VSYNC 0: Slave VIP host device present
PCIE_GTX_MRX_P9 AA27 C130 1 2 1: No slave VIP host device present
PCIE_GTX_MRX_N9 PCIE_TX9P 0.1U_0402_16V4Z
Y27 PCIE_TX9N
PCIE_GTX_MRX_P10 Y25 AK4 * The readback of this strap is the
PCIE_GTX_MRX_N10 PCIE_TX10P NC_DVOVMODE_0 inverted with respect to the value
W25 PCIE_TX10N NC_DVOVMODE_1 AL4
PCIE_GTX_MRX_P11 on the pin
W28 PCIE_TX11P
PCIE_GTX_MRX_N11 V28 AF2 Low -> VDDC=1.0V+-5% Performance Mode for M52
PCIE_GTX_MRX_P12 PCIE_TX11N DVPCNTL_0
V27 AF1 High -> VDDC=0.95V+-5% Battery Mode for M52

VIP HOST/ EXTERNAL TMDS
PCIE_GTX_MRX_N12 PCIE_TX12P DVPCNTL_1
U27 PCIE_TX12N DVPCNTL_2 AF3
PCIE_GTX_MRX_P13 U25 AG1
PCIE_GTX_MRX_N13 PCIE_TX13P DVPCLK
T25 PCIE_TX13N DVPDATA_0 AG2
PCIE_GTX_MRX_P14 T28 AG3 POWER_SEL R97 1 2 10K_0402_5% +3VS