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CPU
755SA1 Purchase from www.A-PDF.com to remove the watermarkTHERMAL EC
A-PDF Watermark DEMO: 100/133/200MHZ
CPUCLK
CPUCLK#
Pentium 4
Socket 478
+3V
BLOCK DIAGRAM Vcore
HOST BUS
Page 3
ADM1032
Page 3
100/133/166MHZ DDR RAM BUS
D
755SA1 P/N: SIS648CLK
D
100/133/200MHZ SIS648CLK# North Bridge CRT Page 16
FWSDCLKO SIS
DDRCLK0 DDRCLK0# AGP
DDRCLK0 DDRCLK0#
DDRCLK1 DDRCLK1#
AGPCLK 66MHZ 648(FX) ATI M9+C LCD Page 17
DDRCLK1
DDRCLK2 DDR 2 DDRCLK1#
DDRCLK2#
DDRCLK2 DDR 1
+2.5V
DDRCLK2#
648ZCLK 66/133MHZ VDDQ +3V
+2.5V
+1.8V
+5V +2.5V
+3V +1.5V
+2.5V
Page 9
Page 9
+1.25V terminal
+1.5V Page 6
Page 11 S-Video TV
+1.25V terminal HyperZip BUS AGPCLK1 66MHZ Page 16
AC Link IDE
PCI BUS
South Bridge RTC
+3V +5V SIS
963 Page 21
AUDIO CODEC MDC 963ZCLK 66/133MHZ +3V
VT1612A
+3V +5V Page 27
963PCICLK 33MHZ
USB-48MHZ Vcore LAN(PHY) HDD CD-ROM
2.5"
+3V REALTEK RJ45/11
Page 23 963REF1 14.318MHZ +1.8V +5V +5V
963REF3 33MHZ RTL8201BL
AMPLIFIER MIC RJ45/11 Page 27 PRIMARY SECONDARY
C C
NS Page 18 MASTER MASTER
Page 25
LM4835 +5V CRYSTAL CRYSTAL
Page 24 24.576M HZ 25M HZ
INTERNAL PHONE JACK IEEE-1394 CRYSTAL
SPK * 2 CRYSTAL 32.768K
Page 24 Page 25 24.576M HZ TSB43AB22
+3V CRYSTAL
Page 26 12M HZ
PCLK_CB 33MHZ
1394 CONN
TI1410
+5V
+3V +5V +12V
Page 22 USB1-3 CARD READER WIRELESS CONN
Page 28 Page 28 Page 28
CRYSTAL
14.318MHz
B B
CPUCLK
CPUCLK# 68PIN-CONN
SIS648CLK 100/133MHZ LPC BUS
Clock Gen
SIS648CLK#
FWSDCLK +3V
CRYSTAL
AGPCLK 66MHZ
AGPCLK1 66MHZ
393-48MHZ
LPC_CLK_33MHZ
LPC 32.768K K/B CONTROLLER
PC87383 PCLK_EC 33MHZ NS
PC97551 +3V
648ZCLK 133MHZ Page 29 Page 31
ICS 963ZCLK 133MHZ
ICS952005
USB-48MHZ
393-48MHZ Parallel FLASH ROM
+5V +5V
963PCICLK 33MHZ
PCLK_CB 33MHZ
PCLK_M 33MHZ
INT K/B T/P FAN CHARGER BATTERY
Power Switch CONN & AC_IN.......Page 30 Page 30 Page 25 Page 36 Page 36
LPC_CLK 33MHZ
A
PCLK_EC 33MHZ A
DDRCLK0 Vcore......Page 32
DDRCLK0#
Clock Buf DDRCLK1 +2.5V,+1.5V,+1.25V.......Page 33
963REF1 14.318MHZ ICS 100/133/166MHZ
DDRCLK1#
963REF3 33MHZ
ICS93722 DDRCLK2 +1.8V.......Page 34
DDRCLK2# Unwill International Corp.
Title
+3V +3V +2.5V
Page 5 Page 5 +3V,+5V.......Page 35 755SA1
Size Document Number Rev
SYSTEM BLOCK DIAGRAM A
2410
Date: Monday, December 08, 2003 Sheet 1 of 38
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RA to RB
Modify 1 : Change R371 to 3.48k_1 for +1.8V
Modify 2 : Remove C392 for +1.8V Power ON Sequence
Modify 3 : Modify for Schematic Error
Modify 4 : Change R414 to 0 ohm for +3v_ON Voltage Level
Modify 5 : Modify for Schematic Error
Modify 6 : Add 2200P for Switching Power Quality
D
Modify 7 : Change PR12 to 0 ohm for EC Voltage Level D
Modify 8 : Modify R524 Connect to VCC_AMP for VR1
Modify 9 : Modify Schematic for S3 Power Sequence
Modify 10 : Add C660 for 648 Request
Modify 11 : Reserve C655,C656,C657,C658,C659,C661,C662 for 648 Request
Modify 12 : Add R830 470 ohm for HVREF
Modify 13 : Change PR2,PR4,PR6,PR8 for Total Power Accuracy
Modify 14 : Add R831 for CMOS Discharge Safety
Modify 15 : Remove 0 ohm for Software Bug
Modify 16 : Change Wireless CONN Pin Define for Design Issue
Modify 17 : Remove R for VRAM On Board
Modify 18 : Add 0 ohm for CPU Power Current Return Path
Modify 19 : Add Schematic and modify R557,R556 value for SPK volume
Modify 20 : Add Schematic for EC to select CPU frequency
Modify 21 : Add R839,R840 and DDR memory capacitance for DDR stability
Modify 22 : Add bypass capacitance for difference power plane
Modify 23 : Add capacitance for sis648 system stability
Modify 24 : Add capacitance for VGA system stability
Modify 25 : Add MEM_ID select for VRAM on Board
Modify 26 : Add for EC SMP fuction
C Modify 27 : Improve Audio Signal Quality C
Modify 28 : Add schematic for audio
Modify 29 : Modify for EMI
B B
A A
Unwill International Corp.
Title
755SA1
Size Document Number Rev
REVISION HISTORY A
2410
Date: Monday, December 08, 2003 Sheet 2 of 38
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+1.2V
30mil
TP45
TP47 TP44 R37 CPU_CORE
4.7K_OP TP2
TP42 ITP_CLK TP1
+1.25V +1.2V
ITP_CLK# TP49
TP39TP46 TP3 FERR# R115 61.9_1
6 HA#[3..31]
CPU_VID0
CPU_VID0 32
CPU_VID1 BREQ0# R106 51.1_1
6 RS#[0..2] CPU_VID1 32
CPU_VID2
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
Z0301
Z0302
Z0303
Z0304
AF3 Z0305
AC1 Z0306
V5 Z0307
Z0308
Z0309
Z0310
Z0311
CPU_VID2 32
RS#0
RS#1
RS#2
HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
CPU_VID3 PROCHOT# R127 61.9_1
CPU_VID3 32
TP50 ADS# CPU_VID4
CPU_VID4 32
AC26
AD26
D +3V CPUPWRGD R68 51.1_1 D
AB1
AE5
AE4
AE3
AE2
AE1
AF4
K25
K26
L25
J26
W1
W2
M6
M3
M4
M1
G5
N1
N2
N4
N5
R2
R3
U1
U3
R6
U4
K2
K4
K1
P3
P4
P6
V2
V3
Y1
F1
F4
T1
T2
T4
T5
U10A
L6
L3
L2
+1.2V BSEL0 R390 1K THERMTRIP# R123 61.9_1
IERR# AC3
RS0
RS1
RS2
HA3
HA4
HA5
HA6
HA7
HA8
HA9
HA10
HA11
HA12
HA13
HA14
HA15
HA16
HA17
HA18
HA19
HA20
HA21
HA22
HA23
HA24
HA25
HA26
HA27
HA28
HA29
HA30
HA31
HA32
HA33
HA34
HA35
VCCVID
VCCVIDPRG
ITP_CLK0
ITP_CLK1
AP0
AP1
DEP0
DEP1
DEP2
DEP3
VID0
VID1
VID2
VID3
VID4
Z0312 IERR BSEL1 R42 1K_OP A20M# R114 56.2_1
TP48 V6 MCERR
18 FERR#
FERR# B6 FERR VIDPWRGD AD2 Z0315 R38 4.7K_OP
STPCLK# Y4 STPCLK# R70 56.2_1
4,18 STPCLK# Z0313 STPCLK
TP43 AA3 BINIT BCLK0 AF22 CPUCLK CPUCLK 5
HTCK R125 27
INIT# W5 AF23 CPUCLK# CPUSLP# R23 56.2_1
18 INIT# Z0314 INIT BCLK1 CPUCLK# 5
TP40 AB2 HTRST# R113 680
RSP SMI# R118 56.2_1
6 DBSY# H5 DBSY
6 DRDY# H2 DRDY COMP0 L24 CPUCOM0 CPUCOM0 R92 61.9_1
6 HTRDY# J6 TRDY COMP1 P1 CPUCOM#0 INIT# R94 56.2_1
ADS# G1 CPUCOM#0 R104 61.9_1
6 ADS# ADS
G4 D1 INTR IGNNE# R124 56.2_1
6 HLOCK# LOCK LINT0 INTR 18
BREQ0# H6 E5 NMI
6 BREQ0# BRO LINT1 NMI 18
G2 INTR R107 56.2_1
6 BNR# BNR
6 HIT# F3 HIT HASTB#[0..1] 6
6 HITM# E3 HITM ADSTB0 L5 HASTB#0 NMI R119 56.2_1
6 BPRI# D2 BPR ADSTB1 R5 HASTB#1
6 DEFER# E2 DEFER DBRESET AE25 DBRESET HTMS R112 39
HTCK D4
HTDI TCK DBRESET R27 150_1
C1 TDI HDSTBP#[0..3] 6
HTMS F7 F21 HDSTBP#0
HTRST# TMS STBP0 HDSTBP#1 CPURST# R63 51.1_1
E6 TRST STBP1 J23
HTDO D5 P23 HDSTBP#2
PROCHOT# TDO STBP2 HDSTBP#3 HTDO R120 75_1
PROCHOT# C3 PROCHOT STBP3 W23
IGNNE# B2
18 IGNNE# IGNNE HDSTBN#[0..3] 6
SMI# B5 E22 HDSTBN#0 HTDI R105 150_1
18 SMI# SMI STBN0
C A20M# C6 K22 HDSTBN#1 C
18 A20M# A20M STBN1
CPUSLP# AB26 R22 HDSTBN#2 ITP_CLK R24 1K
18 CPUSLP# SLP STBN2
CPUPWRGD AB23 W22 HDSTBN#3
6 CPUPWRGD PWRGOOD STBN3
CPURST# AB25 ITP_CLK# R25 1K
6 CPURST# RESET
TEST_GROUP0 DBI#[0..3] 6
AD24 E21 DBI#0
TESTHI0 DB#0 DBI#1 BSEL1 BSEL0 Function BPM#3 R49
AA2 G25 61.9_1
TEST_GROUP1 TESTHI1 DB#1 DBI#2 BPM#4 R50
AC21 P26 L L 100MHz 61.9_1
TESTHI2 DB#2 DBI#3 BPM#2 R51
AC20 V21 L Hi-Z 133MHz 61.9_1
TESTHI3 DB#3 BPM#5 R54
AC24 HREQ#[0..4] 6 61.9_1
TESTHI4 HREQ#0
H L RSVD
AC23 TESTHI5 REQ0 J1
HREQ#1 H H RSVD TEST_GROUP0 R40 61.9_1
AA20 TESTHI6 REQ1 K5
AB22 J4 HREQ#2
TEST_GROUP2 TESTHI7 REQ2 HREQ#3 TEST_GROUP1 R31
U6 J3 61.9_1
TESTHI8 REQ3 HREQ#4
W4 TESTHI9 REQ4 H3
Y3 TEST_GROUP2 R41 61.9_1
R117 0 GHI# TESTHI10 THERMDA
CPU_GHI# A6 TESTHI11 THERMDA B3
DPSLP# AD25 C4 THERMDC
TESTHI12 THERMDC BAT54
THERMTRIP A2 THERMTRIP# 18
AC6 DPSLP# R26 61.9_1
BPM0 BSEL0 5,19 PM_CPU_STP#
AB5 AD6 GHI# R116 61.9_1
BPM#2 BPM1 BSEL0
AC4 BPM2 BSEL1 AD5 BSEL1 TP37 D13
BPM#3 Y6
BPM#4 BPM3 Z0322 TP5
AA5 BPM4 VCC_SENSE A5
BPM#5 AB4 A4 Z0323 TP4
BPM5 VSS_SENSE
Modify 20
G22 HD10
H21 HD11
C26 HD12
D23 HD13
J21 HD14
D25 HD15
H22 HD16
E24 HD17
G23 HD18
F23 HD19
F24 HD20
E25 HD21
F26 HD22
D26 HD23
L21 HD24
G26 HD25
H24 HD26
M21 HD27
L22 HD28
J24 HD29
K23 HD30
H25 HD31
M23 HD32
N22 HD33
P21 HD34
M24 HD35
N23 HD36
M26 HD37
N26 HD38
N25 HD39
R21 HD40
P24 HD41
R25 HD42
R24 HD43
T26 HD44
T25 HD45
T22 HD46