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8 7 6 5 4 3 2 1
Cover Sheet
Block Diagram
1
2
MS-6550 Version : 1.0A 06/11/2002 Update
INTEL (R) Brookdale Chipset
GPIO Spec. 3
D
Willamette/Northwood 478pin mPGA-B Processor Schematics D
Clock Generation 4
CPU:
mPGA478-B INTEL CPU Sockets 5-6
Willamette/Northwood mPGA-478B Processor
INTEL Brookdale MCH -- North Bridge 7-8
INTEL ICH2 -- South Bridge & IR 9 - 10 System Brookdale Chipset:
INTEL MCH (North Bridge) +
LPC I/O W83627HF 11
INTEL ICH2 (South Bridge)
AC'97 Codec 12
On Board Chipset: BIOS -- FWH
Audio Amp TL072 13 AC'97 Codec -- AD1881/1885
C
LPC Super I/O -- W83627HF C
FWH -- BIOS 14 Clock Generation -- CY28324 /ICS950208
LAN -- INTEL 82562ET/EM
DDR DIMM-184 * 2 15
AGP 4X SLOT (1.5V) 16 Expansion Slots: DDR DIMM SLOT * 2
AGP2.0 SLOT * 1
PCI SLOT 1 & 2 & 3 17 PCI2.2 SLOT *3
ISA SLOT * 1 (Share PCI3)
IDE CONNECTORS 18
Front Panel & Power Connectors 19 Note : Standard -> WO/ISA ;WO/LAN ;W/ADI1881
A -> With Intel LAN ( 82562ET + 93C46 )
USB & FAN Connectors 20 B -> With ISA (W83628 + W83629 )
B
C -> Support Audio Codec ADI1885 B
Game Port and CPU Thermal-strip 21 D -> Support Intel LAN ( 82562EM + 93C66 )
T -> With CPU Thermstrip Function
Votlage Regulator ( AGP & VCC_VID Power ) 22
MS6550/VER: 10A BOM :
Intersil HIP6301 PWM ( Vcore ) 23 MS6550L2_Option : L -> Note -> A + C => 6550-010 ( MP BOM )
MS6550L2_Option : I + L -> Note -> A + B +C => 6550-020 ( MP BOM )
IO Connectors ( COM & Parallel Port , FDD , Keyboard & Mouse ) 24 MS6550L2_Standard -> Note -> C =>6550-020 ( MP BOM ) -> 6550-030 ( MP BOM ) 7/June
MS6550L2_Option : I -> Note -> B + C =>6550-020 ( MP BOM ) -> 6550-040 ( MP BOM ) 7/June
LAN INTEL 82562EM/ET 25
1.Release ECR for L2 P.S. compatibility and Q51/MOSFET too hot issue. 2002/06/07
2.Creat 2 New-BOM from 6550L2/OPT:I+L (6550-020) to 6550L2/OPT:I & Stand for PM requested 2002/06/11
PCI TO ISA BRIDGE AND ISA SLOT 26,27 3.Modify ICH2 "RTC" issue . ( Reference to MS6551 )
DDR Damping Resistor 28
A XXX MS6550L2_Option : L -> Note -> A + B + C => 6550-03S ( ES BOM ) A
DDR ( Main & VTT) and ACPI Power and DDR Terminator R & C 29,30 XXX MS6550_Option : L -> Note -> A + C => 6550-04S ( ES BOM )
Title Rev
MANUAL & JUMPER SETTING 31,32 Micro-Star MS-6550 10A
Document Number
Design Guide & Power Delivery & HISTORY 33,34,35 Cover Sheet
Last Revision Date:
Thursday, June 27, 2002 Sheet 1 of 35
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8 7 6 5 4 3 2 1
D D
(478PINS)
(100MHz)
Power
Supply VRM Willamette/Northwood CK408 Clock
CONN 9.X Socket (mPGA478-B) (100MHz)
(400MHz) Scalable Bus Scalable Bus/2
4X (66MHz) AGP
AGP 4X
(1.5V) MCH: Memory
Controller HUB
(593PINS/FCBGA) (200MHz)
DIMM 1:2
VRM
AGP
CONN
( 66MHz X 4 ) HUB Interface
(14.318MHz)
C Hardware SM Bus C
Monitor ICH2: I/O PCI (33MHz)
PCI Slots 1:3
(360PINS/EBGA)
Controller HUB
IDE CONN 1&2
(48MHz)
PCI TO ISA BRIDGE ISA SLOT 1
(33MHz)
(33MHz)
LPC Bus AC Link
USB Port 0:3
AC '97 Audio
FWH: Firmware HUB AMP
Codec
SIO
Line Out
MIC In
B
Audio In B
LAN
Modem-In
PS2 Mouse & Parallel (1) Floppy Disk Stuffing
Options CD-ROM
Keyboard Serial (2) Drive CONN
RJ45
A A
Title Rev
Micro-Star MS-6550 10A
Document Number
Block Diagram
Last Revision Date:
Thursday, June 27, 2002 Sheet 2 of 35
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5 4 3 2 1
General Purpose I/O Spec.
FWH
ICH2 GPIO Pin PIN # Type Function
GPIO Pin PIN # Type Function
D GPI 0 6 I ATA IDE 1 Detect D
GPIO 0 M3 I PCI TO ISA REQA#
GPI 1 5 I ATA IDE 2 Detect
GPIO 1 L3 I Not Using (PREQ#5)
GPI 2 4 I Not Using
GPIO 2 N3 I Not Using (INTE#)
GPI 3 3 I Not Using
GPIO 3 N2 I Not Using (INTF#)
GPIO 4 N1 I Not Using (INTG#)
GPIO 5 M4 I Not Using (INTH#)
SIO
GPIO Pin PIN # Type Function
GPIO 6 Y11 I Reserved for futuer
GP32 71 I/OD Non Connect
GPIO 7 AA11 I Non Connect
GP24 89 I/OD Non Connect
GPIO 8 Y14 I LAN Wake Up
GP34 69 I/OD Non Connect
C
GPIO 9 Y22 I AC'97 Serial Data In 0 C
GP33 70 I/OD Non Connect
GPIO 10 I Non Connect
GPIO 11 AB17 I Not Using (SMB_ALERT)
GPIO 12 W14 I External SMI
GPIO 13 AB15 I LPC PME
GPIO 14~15 I Not Implemented DEVICE ICH INT Pin IDSEL
GPIO 16 L2 O PCI TO ISA GNTA#
PCI Slot 1 INTA# AD16
GPIO 17 L4 O Non Connect INTB#
INTC#
GPIO 18 A15 O Non Connect
INTD#
B
GPIO 19 D14 O Non Connect B
PCI Slot 2 INTB# AD17
GPIO 20 C14 O Non Connect
INTC#
GPIO 21 L1 O PCI TO ISA NOGO INTD#
INTA#
GPIO 22 B14 OD Non Connect
GPIO 23 A14 O BIOS Locked/Unlocked PCI Slot 3 INTC# AD18
INTD#
GPIO 24 V21 O Power-On Loss Control ( Set Low after Power-On )
***
INTA#
GPIO 25 W15 O LAN ENABLE/DISABLE INTB#
GPIO 26 O Non Connect
ISA SLOT AD22
GPIO 27 AB14 I/O LAN Enable/Disable Detected
GPIO 28 AA14 I/O Reserved ( for LAN ENABLE/DISABLE )
GPIO 29~31 I/O Not Implemented
A A
Title Rev
Micro-Star MS-6550 10A
Document Number
GPIO Spec.
Last Revision Date:
Thursday, June 27, 2002 Sheet 3 of 35
5 4 3 2 1
8 7 6 5 4 3 2 1
Put under Bead
*Trace less 0.5"
CP10 CLOCK GENERATOR BLOCK Shut Source Termination Resistors Pull-Down Capacitors
2 1
CPUCLK R146 49.9RST
U12 CPUCLK# R148 49.9RST CN13 X_10p
FB26 X_601S/0805 39 41 R143 33RST CPUCLK MCHCLK R156 49.9RST CPUCLK 8 7
VCC3 CPU_VDD CPU0 CPUCLK 5
R145 33RST CPUCLK# MCHCLK# R162 49.9RST CPUCLK#
+
CPU0# 40 CPUCLK# 5 6 5
CB61 CT11 CB56 CB60 MCHCLK 4 3
104P Rubycon 105P/0805 104P 36 38 R155 33RST MCHCLK MCHCLK# 2 1
CPU_GND CPU1 MCHCLK 7
37 R161 33RST MCHCLK#
CPU1# MCHCLK# 7
D ELS10/16-B D
46 C_STP C124 X_10p
for good filtering from 10K~1M MREF_VDD C_STP P_STP C126 X_10p
CB51 3VMREF/CPU_STP# 45
P_STP
Trace less 0.2"
3VMREF#/PCI_STP# 44
104P 43 49.9ohm for 50ohm M/B impedance CN14 10p
Put under Bead MREF_GND RN20 8P4R-33 MCH_66 8 7
32 31 1 2 MCH_66 ICH_66 6 5
CP9 3V66_VDD 3V66_0 MCH_66 7
30 3 4 ICH_66 AGPCLK 4 3
3V66_1 ICH_66 10
2 1 CB77 28 5 6 AGPCLK 3V66_4 2 1
R169 104P 29
3V66_2
27 3V66_3 7 8 3V66_4
AGPCLK 16 CLOCK STRAPPING RESISTORS
X_0/0805 3V66_GND 3V66_3
6 FS2 7 8 ICH_PCLK FS4 R144 10K VCC3V
FS2/PCI_F0 ICH_PCLK 9
FB25 X_601S/0805 VCC3V 9 7 FS3 5 6 FWH_PCLK FS3 R139 10K VCC3V
VCC3 PCI_VDD FS3/PCI_F1 FWH_PCLK 14
MODE SIO_PCLK ICH_PCLK C123 X_10P
+
MODE/PCI_F2 8 3 4 SIO_PCLK 11
CB139 CT10 CB46 CB57 1 2 FS1 R175 X_10K VCC3V FWH_PCLK C125 X_10P
104P Rubycon 105P/0805 104P FS4 5 BSEL0 R180 10K SIO_PCLK C127 X_10P
5 PCI_GND FS4/PCI0 10
11 RN15 8P4R-33
ELS10/16-B PCI1 ISAPCLK FS0 R168 10K VCC3V CN12 X_10p
18 PCI_VDD PCI2 12 7 8 ISAPCLK 26
14 5 6 PCICLK0 R172 X_10K PCICLK2 8 7
PCI3 PCICLK0 17
for good filtering from 10K~1M CB72 15 3 4 PCICLK1 PCICLK1 6 5
PCI4 PCICLK1 17
104P 13 16 1 2 PCICLK2 PCICLK0 4 3
PCI_GND PCI5 PCICLK2 17
*Put GND copper under Clock Gen. 17 R134 10K VCC3V ISAPCLK 2 1
PCI6 RN17 8P4R-33 FS2 R133 X_10K
connect to every GND pin 24 48_VDD FS0 R173 33 ICH_48
* 40 mils Trace on Layer 4 CB80 FS0/48MHz 22
FS1 R174 33 SIO_48
ICH_48 10
MODE R149 X_10K
FS1/24_48MHz 23 SIO_48 11
with GND copper around it 104P 21 ICH_48 C130 10P
48_GND SIO_48 C132 10P
* put close to every power pin R124 33 ICH_14
C 2 REF_VDD ICH_14 10 C
* Trace Width 7mils. 48 MUL0 R131 B_33 OSC MUL0 R136 X_10K VCC3V
VCC3 MUL0/REF0 OSC 27
CB50 1 MUL1 R137 10K
104P MUL1/REF1 R122 X_33 CODE_14 OSC C118 B_10P
* Same Group spacing 15mils 47 REF_GND CODE_14 12
MUL1 R138 10K VCC3V
* Different Group spacing 30mils 34 3 C120 22p R125 X_10K ICH_14 C116 10P
CORE_VDD X1 32pF
* Different mode spacing 7mils on itself R160 CB73 X3 14M-32pf-HC49S-D CODE_14 C114 X_10P
10K 104P 33 4 C119 22p CRST# R167 10K VCC3V
CORE_GND X2
SMBCLK 26 35 R166 475RST
10,11,15 SMBCLK SCLK IREF
SMBDATA 25 SMBCLK R384 1K used only for EMI issue
10,11,15 SMBDATA SDATA VCC3
20 CRST# R171 X_0 CLK_RST# SMBDATA R413 1K
RST# CLK_RST# 19
R165 0 19 42 R142 4.7K VCC3V
VTT_GD# PWR_DN# VCC3V
R178 220 ICS950213 C_STP R140 1K VCC3V
Trace less 0.2"
VCCP
P_STP R141 1K
Q11 R164 X_1K For Cypress
2N3904S
28324
+12V
RESET BLOCK
B B
R150
R181 T_4.7K 100K_T-X
VCCP
R177 T_4.7K R179 220 R359 330 R358 180
21 LATCH VCC3 VCC3
PCIRST# 1 2 PCIRST# 3 4
9 PCIRST# PCIRST#1 7 PCIRST#2 11,16,17
Q10
5 SKTOC# 2N3904S U21A U21B
D7 C129 DM7407-SOIC14_#A C194 DM7407-SOIC14_#B
T_1N4148-S-LL34 105P/0805_X-T (VCC5_SB) (VCC5_SB)
X_10P
R157
10K_T-X
VCC3 R317 1K
VCC5
R316 HD_RST#
HD_RST# 18
4.7K
R315 4.7K Q29
A 2N3904S A
PCIRST# R350 4.7K Q28
2N3904S
Title Rev
R349
10K
Micro-Star MS-6550 10A
Document Number
Clock CY28323/4
Last Revision Date:
Thursday, June 27, 2002 Sheet 4 of 35
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8 7 6 5 4 3 2 1
CPU SIGNAL BLOCK
VCCPS+ 23
7 HA#[3..31] VCCPS- 23
VID[0..4] 11,23
HA#31
HA#30
HA#29
HA#28
HA#27
HA#26
HA#25
HA#24
HA#23
HA#22
HA#21
HA#20
HA#19
HA#18
HA#17
HA#16
HA#15
HA#14
HA#13
HA#12
HA#11
HA#10
HA#9
HA#8
HA#7
HA#6
HA#5
HA#4
HA#3
VID2
VID1
VID0
VID4
VID3
AD26
AC26
AE25
D D
AB1
AE1
AE2
AE3
AE4
AE5
W2
W1
M1
M4
M3
M6
U4
R6
U3
U1
R3
R2
N5
N4
N2
N1
Y1
V3
V2
P6
P4
P3
K1
K4
K2
A5
A4
T5
T4
T2
T1
L2
L3
L6
U14A
VCC_SENSE
VSS_SENSE
A35#
A34#
A33#
A32#
A31#
A30#
A29#
A28#
A27#
A26#
A25#
A24#
A23#
A22#
A21#
A20#
A19#
A18#
A17#
A16#
A15#
A14#
A13#
A12#
A11#
A10#
A9#
A8#
A7#
A6#
A5#
A4#
A3#
DBR#
ITP_CLK1
ITP_CLK0
VID4#
VID3#
VID2#
VID1#
VID0#