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Z05 SYSTEM BLOCK DIAGRAM
CPU CORE / VDDNB
(ISL6265A)
PAGE 26
D D
NB_CORE +1.1V DDRII-SODIMM1 DDRII 667/800 MHz Lion CPU THERMAL
(RT8202)
PAGE 28 PAGE 6 AMD Griffin Sabie SENSOR CPU Fan
PAGE 23
S1G2 Processor PAGE 4
+1.1V_NB
DDRII-SODIMM2 DDRII 667/800 MHz 638P (uPGA)/35W
(RT8202) PAGE 6 PAGE 2,3,4,5
PAGE 27
DDR II SMDDR_VTERM
HT3
1.8VSUS(TPS51116REGR) LINK
PAGE 29
SYSTEM POWER
PCI-E
(ISL6237) LVDS LVDS PCIE4 PCIE3 PCIE2
PAGE 25 X1 X1 X1
PAGE 14
Mini PCI-E Express LAN
SYSTEM CHARGER Card Card BRODCOM RJ45
(ISL6251A)
CRT CRT BCM8764M
(Wireless LAN) (NEW CARD) PAGE 15
C
PAGE 24
PAGE 14
NORTH BRIDGE & (10/100/GagaLAN)
C
SOUTH BRIDGE PAGE 17 PAGE 17 PAGE 15
X1 X1
USB 8 USB 5
MCP77M USB2.0
SATA - HDD USB 0,1,7 USB 6 USB 3 USB 10 USB 2
SATA0 X3 X1 X1 X1 X1
PAGE 18 27mm X 27mm,
836pin BGA
USB2.0 Ports Bluetooth PC-cam Fingerprint Card Reader
Realtek
ODD(SATA)
SATA1 PAGE 16,24 PAGE 16 PAGE 14 PAGE 23 RTS5158E
PAGE 18 (7 in 1)
PAGE 19
14.318MHz
PAGE 7,8,9,10,
B
11,12,13 Azalia B
Azalia AudioController MDC 1.5
LPC RealTek ALC268 RJ11
PAGE 20 PAGE 20 PAGE 15
KBC
PCB STACK UP Keyboard
(WPCE775C)
PAGE 23 Audio
Int MIC
LAYER 1 : TOP PAGE 22 Amplifier
PAGE 20
PAGE 20
LAYER 2 : GND
LAYER 3 : IN1
LAYER 4 : IN2 SPIDF/Phone
Touch Pad SPI ROM Speaker
Jack
Line in MIC Jack
LAYER 5 : VCC PAGE 20 PAGE 21 PAGE 21 PAGE 21
PAGE 18 PAGE 22
LAYER 6 : BOT
A A
Quanta Computer Inc.
PROJECT : Z05
Size Document Number Rev
1A
Block Diagram
Date: Friday, March 07, 2008 Sheet 1 of 34
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PDF created with FinePrint pdfFactory Pro trial version http://www.fineprint.com
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HT_RXD#[15..0] HT_TXD[15..0]
<7> HT_RXD#[15..0] <7> HT_TXD[15..0]
HT_RXD[15..0] HT_TXD#[15..0]
<7> HT_RXD[15..0] <7> HT_TXD#[15..0]
D D
PROCESSOR HYPERTRANSPORT INTERFACE
VLDT_Ax AND VLDT_Bx ARE CONNECTED TO THE LDT_RUN POWER
SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED
ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE
VLDT_RUN
U14A
D1 HT LINK AE2 C399
VLDT_A0 VLDT_B0
D2 VLDT_A1 VLDT_B1 AE3
D3 AE4 Note:on MCP77,(HT=+1.1V) and CPU(HT=+1.2V)
VLDT_A2 VLDT_B2 4.7U_6
D4 VLDT_A3 VLDT_B3 AE5 and therefore cannot be connected to the
same HT power rail.
HT_RXD0 E3 AD1 HT_TXD0
C L0_CADIN_H0 L0_CADOUT_H0 C
HT_RXD#0 E2 AC1 HT_TXD#0
HT_RXD1 L0_CADIN_L0 L0_CADOUT_L0 HT_TXD1
E1 L0_CADIN_H1 L0_CADOUT_H1 AC2
HT_RXD#1 F1 AC3 HT_TXD#1 +1.2V_HT VLDT_RUN
HT_RXD2 L0_CADIN_L1 L0_CADOUT_L1 HT_TXD2
G3 L0_CADIN_H2 L0_CADOUT_H2 AB1
HT_RXD#2 G2 AA1 HT_TXD#2 L58
HT_RXD3 L0_CADIN_L2 L0_CADOUT_L2 HT_TXD3
G1 L0_CADIN_H3 L0_CADOUT_H3 AA2
HT_RXD#3 H1 AA3 HT_TXD#3 FBJ3216HS800_1206
HT_RXD4 L0_CADIN_L3 L0_CADOUT_L3 HT_TXD4
J1 L0_CADIN_H4 L0_CADOUT_H4 W2
HT_RXD#4 K1 W3 HT_TXD#4 L59
HT_RXD5 L0_CADIN_L4 L0_CADOUT_L4 HT_TXD5
L3 L0_CADIN_H5 L0_CADOUT_H5 V1
HT_RXD#5 L2 U1 HT_TXD#5 FBJ3216HS800_1206
HT_RXD6 L0_CADIN_L5 L0_CADOUT_L5 HT_TXD6
L1 L0_CADIN_H6 L0_CADOUT_H6 U2
HT_RXD#6 M1 U3 HT_TXD#6 80 ohm(4A) C401 C428 C427 C396 C394 C424
HT_RXD7 L0_CADIN_L6 L0_CADOUT_L6 HT_TXD7 4.7U_6 4.7U_6 .22U_4 .22U_4 180P_4 180P_4
N3 L0_CADIN_H7 L0_CADOUT_H7 T1
HT_RXD#7 N2 R1 HT_TXD#7
HT_RXD8 L0_CADIN_L7 L0_CADOUT_L7 HT_TXD8
E5 L0_CADIN_H8 L0_CADOUT_H8 AD4
HT_RXD#8 F5 AD3 HT_TXD#8
HT_RXD9 L0_CADIN_L8 L0_CADOUT_L8 HT_TXD9
F3 L0_CADIN_H9 L0_CADOUT_H9 AD5
HT_RXD#9 F4 AC5 HT_TXD#9
HT_RXD10 G5
L0_CADIN_L9 L0_CADOUT_L9
AB4 HT_TXD10 LAYOUT: Place bypass cap on topside of board
HT_RXD#10 L0_CADIN_H10 L0_CADOUT_H10 HT_TXD#10
H5 L0_CADIN_L10 L0_CADOUT_L10 AB3 NEAR HT POWER PINS THAT ARE NOT CONNECTED DIRECTLY
HT_RXD11 H3 AB5 HT_TXD11 TO DOWNSTREAM HT DEVICE, BUT CONNECTED INTERNALLY
HT_RXD#11 L0_CADIN_H11 L0_CADOUT_H11 HT_TXD#11
H4 L0_CADIN_L11 L0_CADOUT_L11 AA5 TO OTHER HT POWER PINS
B HT_RXD12 K3 Y5 HT_TXD12 PLACE CLOSE TO VLDT0 POWER PINS B
HT_RXD#12 L0_CADIN_H12 L0_CADOUT_H12 HT_TXD#12
K4 L0_CADIN_L12 L0_CADOUT_L12 W5
HT_RXD13 L5 V4 HT_TXD13
HT_RXD#13 L0_CADIN_H13 L0_CADOUT_H13 HT_TXD#13
M5 L0_CADIN_L13 L0_CADOUT_L13 V3
HT_RXD14 M3 V5 HT_TXD14
HT_RXD#14 L0_CADIN_H14 L0_CADOUT_H14 HT_TXD#14
M4 L0_CADIN_L14 L0_CADOUT_L14 U5
HT_RXD15 N5 T4 HT_TXD15
HT_RXD#15 L0_CADIN_H15 L0_CADOUT_H15 HT_TXD#15
P5 L0_CADIN_L15 L0_CADOUT_L15 T3
<7> HT_CPU_UPCLK0 J3 L0_CLKIN_H0 L0_CLKOUT_H0 Y1 HT_CPU_DWNCLK0 <7>
<7> HT_CPU_UPCLK#0 J2 L0_CLKIN_L0 L0_CLKOUT_L0 W1 HT_CPU_DWNCLK#0 <7>
<7> HT_CPU_UPCLK1 J5 L0_CLKIN_H1 L0_CLKOUT_H1 Y4 HT_CPU_DWNCLK1 <7>
<7> HT_CPU_UPCLK#1 K5 L0_CLKIN_L1 L0_CLKOUT_L1 Y3 HT_CPU_DWNCLK#1 <7>
<7> HT_CPU_UPCTL0 N1 L0_CTLIN_H0 L0_CTLOUT_H0 R2 HT_CPU_DWNCTL0 <7>
<7> HT_CPU_UPCTL#0 P1 L0_CTLIN_L0 L0_CTLOUT_L0 R3 HT_CPU_DWNCTL#0 <7>
<7> HT_CPU_UPCTL1 P3 L0_CTLIN_H1 L0_CTLOUT_H1 T5 HT_CPU_DWNCTL1 <7>
<7> HT_CPU_UPCTL#1 P4 L0_CTLIN_L1 L0_CTLOUT_L1 R5 HT_CPU_DWNCTL#1 <7>
Athlon 64 S1g2 SOCKET_638_PIN
Athlon 64 S1g2
A NO STUB R127 R122 Processor Socket A
*51/F_4 *51/F_4 SOCKET_638_PIN
for HT3
VLDT_RUN
Quanta Computer Inc.
PROJECT : Z05
Size Document Number Rev
1A
AMD Griffin HT I/F
Date: Monday, February 25, 2008 Sheet 2 of 34
5 4 3 2 1
PDF created with FinePrint pdfFactory Pro trial version http://www.fineprint.com
A B C D E
VDD_VTT_SUS_CPU IS CONNECTED TO THE VDD_VTT_SUS POWER
SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED
ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE
Processor DDR2 Memory Interface
U14C
+SMDDR_VTERM +SMDDR_VTERM MEM:DATA
<6> M_B_DQ[0..63] M_A_DQ[0..63] <6>
M_B_DQ0 C11 G12 M_A_DQ0
U14B M_B_DQ1 MB_DATA0 MA_DATA0 M_A_DQ1
PLACE THEM CLOSE TO A11 MB_DATA1 MA_DATA1 F12
+1.8VSUS M_B_DQ2 A14 H14 M_A_DQ2
4 CPU WITHIN 1" M_B_DQ3 MB_DATA2 MA_DATA2 M_A_DQ3
4
D10 VTT1 W10 B14 G14
C10 MEM:CMD/CTRL/CLK VTT5 AC10 M_B_DQ4 G11
MB_DATA3 MA_DATA3
H11 M_A_DQ4
VTT2 VTT6 M_B_DQ5 MB_DATA4 MA_DATA4 M_A_DQ5
B10 AB10 E11 H12
VTT3 VTT7 R103 M_B_DQ6 MB_DATA5 MA_DATA5 M_A_DQ6
AD10 AA10 D12 C13
R265 39.2/F_4 VTT4 VTT8 M_B_DQ7 MB_DATA6 MA_DATA6 M_A_DQ7
A10 A13 E13
M_ZP VTT9 2K/F_4 M_B_DQ8 MB_DATA7 MA_DATA7 M_A_DQ8
1 2 AF10 A15 H15
M_ZN MEMZP MB_DATA8 MA_DATA8
+1.8VSUS 2 1 AE10 Y10 CPU_VTT_SUS_FB T15
M_B_DQ9 A16 E15 M_A_DQ9
R266 39.2/F_4 MEMZN VTT_SENSE M_B_DQ10 MB_DATA9 MA_DATA9 M_A_DQ10
A19 E17
MEM_MA_RESET# H16 MB_DATA10 MA_DATA10
T43 W17 CPU_M_VREF M_B_DQ11 A20 H17 M_A_DQ11
RSVD_M1 MEMVREF M_B_DQ12 MB_DATA11 MA_DATA11 M_A_DQ12
C14 E14
MB_DATA12 MA_DATA12
<6> M_A_ODT0 T19 B18 MEM_MB_RESET# T54
M_B_DQ13 D14 F14 M_A_DQ13
MA0_ODT0 RSVD_M2 C100 C81 R102 M_B_DQ14 MB_DATA13 MA_DATA13 M_A_DQ14
<6> M_A_ODT1 V22 C18 C17
M_A1_ODT0 MA0_ODT1 M_B_DQ15 MB_DATA14 MA_DATA14 M_A_DQ15
T12 U21 W26 M_B_ODT0 <6> D18 G17
M_A1_ODT1 MA1_ODT0 MB0_ODT0 .1U_4 1000P_4 2K/F_4 M_B_DQ16 MB_DATA15 MA_DATA15 M_A_DQ16
T26 V19 W23 M_B_ODT1 <6> D20 G18
MA1_ODT1 MB0_ODT1 M_B1_ODT0 M_B_DQ17 MB_DATA16 MA_DATA16 M_A_DQ17
Y26 T13 A21 C19
MB1_ODT0 M_B_DQ18 MB_DATA17 MA_DATA17 M_A_DQ18
<6> M_A_CS#0 T20 D24 D22
MA0_CS_L0 M_B_DQ19 MB_DATA18 MA_DATA18 M_A_DQ19
<6> M_A_CS#1 U19 V26 M_B_CS#0 <6> C25 E20
M_A1_CS#0 MA0_CS_L1 MB0_CS_L0 M_B_DQ20 MB_DATA19 MA_DATA19 M_A_DQ20
T20 U20 W25 M_B_CS#1 <6> B20 E18
M_A1_CS#1 MA1_CS_L0 MB0_CS_L1 M_B1_CS#0 M_B_DQ21 MB_DATA20 MA_DATA20 M_A_DQ21
T16 V20 U22 T18 C20 F18
MA1_CS_L1 MB1_CS_L0 M_B_DQ22 MB_DATA21 MA_DATA21 M_A_DQ22
B24 B22
M_B_DQ23 MB_DATA22 MA_DATA22 M_A_DQ23
<6> M_A_CKE0 J22 J25 M_B_CKE0 <6> C24 C23
MA_CKE0 MB_CKE0 M_B_DQ24 MB_DATA23 MA_DATA23 M_A_DQ24
<6> M_A_CKE1 J20 H26 M_B_CKE1 <6> E23 F20
MA_CKE1 MB_CKE1 M_B_DQ25 MB_DATA24 MA_DATA24 M_A_DQ25
E24 F22
M_B_DQ26 MB_DATA25 MA_DATA25 M_A_DQ26
N19 P22 G25 H24
To reverse SODIMM socket
T40 MA_CLK_H5 MB_CLK_H5 T32 M_B_DQ27 MB_DATA26 MA_DATA26 M_A_DQ27
T33 N20 R22 T36 G26 J19
MA_CLK_L5 MB_CLK_L5 M_B_DQ28 MB_DATA27 MA_DATA27 M_A_DQ28
<6> M_A_CLKOUT1 E16 A17 M_B_CLKOUT1 <6> C26 E21
MA_CLK_H1 MB_CLK_H1 M_B_DQ29 MB_DATA28 MA_DATA28 M_A_DQ29
<6> M_A_CLKOUT1# F16 A18 M_B_CLKOUT1# <6> D26 E22
MA_CLK_L1 MB_CLK_L1 M_B_DQ30 MB_DATA29 MA_DATA29 M_A_DQ30
Y16 AF18 G23 H20
To normal SODIMM socket
<6> M_A_CLKOUT7 MA_CLK_H7 MB_CLK_H7 M_B_CLKOUT7 <6> MB_DATA30 MA_DATA30
AA16 AF17 M_B_DQ31 G24 H22 M_A_DQ31
<6> M_A_CLKOUT7# MA_CLK_L7 MB_CLK_L7 M_B_CLKOUT7# <6> M_B_DQ32 MB_DATA31 MA_DATA31 M_A_DQ32
T30 P19 R26 T31 AA24 Y24
MA_CLK_H4 MB_CLK_H4 M_B_DQ33 MB_DATA32 MA_DATA32 M_A_DQ33
T38 P20 R25 T24 AA23 AB24
MA_CLK_L4 MB_CLK_L4 M_B_DQ34 MB_DATA33 MA_DATA33 M_A_DQ34
<6> M_A_A[0..15] M_B_A[0..15] <6> AD24 AB22
M_A_A0 M_B_A0 M_B_DQ35 MB_DATA34 MA_DATA34 M_A_DQ35
N21 P24 AE24 AA21
M_A_A1 MA_ADD0 MB_ADD0 M_B_A1 M_B_DQ36 MB_DATA35 MA_DATA35 M_A_DQ36
M20 N24 AA26 W22
M_A_A2 MA_ADD1 MB_ADD1 M_B_A2 M_B_DQ37 MB_DATA36 MA_DATA36 M_A_DQ37
N22 P26 AA25 W21
M_A_A3 MA_ADD2 MB_ADD2 M_B_A3 M_B_DQ38 MB_DATA37 MA_DATA37 M_A_DQ38
M19 N23 AD26 Y22
M_A_A4 MA_ADD3 MB_ADD3 M_B_A4 M_B_DQ39 MB_DATA38 MA_DATA38 M_A_DQ39
M22 N26 AE25 AA22
M_A_A5 MA_ADD4 MB_ADD4 M_B_A5 M_B_DQ40 MB_DATA39 MA_DATA39 M_A_DQ40
3 L20 L23 AC22 Y20 3
M_A_A6 MA_ADD5 MB_ADD5 M_B_A6 M_B_DQ41 MB_DATA40 MA_DATA40 M_A_DQ41
M24 N25 AD22 AA20
M_A_A7 MA_ADD6 MB_ADD6 M_B_A7 M_B_DQ42 MB_DATA41 MA_DATA41 M_A_DQ42
L21 L24 AE20 AA18
M_A_A8 MA_ADD7 MB_ADD7 M_B_A8 M_B_DQ43 MB_DATA42 MA_DATA42 M_A_DQ43
L19 M26 AF20 AB18
M_A_A9 MA_ADD8 MB_ADD8 M_B_A9 M_B_DQ44 MB_DATA43 MA_DATA43 M_A_DQ44
K22 K26 AF24 AB21
M_A_A10 MA_ADD9 MB_ADD9 M_B_A10 M_B_DQ45 MB_DATA44 MA_DATA44 M_A_DQ45
R21 T26 AF23 AD21
M_A_A11 MA_ADD10 MB_ADD10 M_B_A11 M_B_DQ46 MB_DATA45 MA_DATA45 M_A_DQ46
L22 L26 AC20 AD19
M_A_A12 MA_ADD11 MB_ADD11 M_B_A12 M_B_DQ47 MB_DATA46 MA_DATA46 M_A_DQ47
K20 L25 AD20 Y18
M_A_A13 MA_ADD12 MB_ADD12 M_B_A13 M_B_DQ48 MB_DATA47 MA_DATA47 M_A_DQ48
V24 W24 AD18 AD17
M_A_A14 MA_ADD13 MB_ADD13 M_B_A14 M_B_DQ49 MB_DATA48 MA_DATA48 M_A_DQ49
K24 J23 AE18 W16
M_A_A15 MA_ADD14 MB_ADD14 M_B_A15 M_B_DQ50 MB_DATA49 MA_DATA49 M_A_DQ50
K19 J24 AC14 W14
MA_ADD15 MB_ADD15 M_B_DQ51 MB_DATA50 MA_DATA50 M_A_DQ51
AD14 Y14
M_B_DQ52 MB_DATA51 MA_DATA51 M_A_DQ52
<6> M_A_BS#0 R20 R24 M_B_BS#0 <6> AF19 Y17
MA_BANK0 MB_BANK0 M_B_DQ53 MB_DATA52 MA_DATA52 M_A_DQ53
<6> M_A_BS#1 R23 U26 M_B_BS#1 <6> AC18 AB17
MA_BANK1 MB_BANK1 M_B_DQ54 MB_DATA53 MA_DATA53 M_A_DQ54
<6> M_A_BS#2 J21 J26 M_B_BS#2 <6> AF16 AB15
MA_BANK2 MB_BANK2 M_B_DQ55 MB_DATA54 MA_DATA54 M_A_DQ55