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A GREAT ER M EA SU R E O F C O N F I D E N C E probe touchdown, parallel test offers fabs the
flexibility to choose whether they want to
increase their wafer test throughput dramati-
cally, or use the available time to acquire sig-
nificantly more data and thereby gain greater
insight into production processes.
At the present time, structures being
tested in parallel are typically located within
a single Test Element Group (TEG). Few IC
manufacturers test structures in different
TEGs simultaneously. To implement this
strategy the parametric tester's controller
is used to inter-leave execution of multiple
tests in a way that maximizes available
processing time and test instrumentation
Parallel Parametric
capacity, which might otherwise have idle
periods. With proper test structure design,
this "multi-threaded" sequencing reduces
Measurements
execution time for multiple tests on multiple
structures to little more than the time needed
to execute the longest test in a sequence.
Reduce Test Costs Comparison of parallel and sequential
test modes