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1 1




Compal Confidential
2 2




HTW20 LA-3171P Schematics Document
Intel Yonah/Merom with 945PM/GM + DDRII + ICH7M
(+VGA/B ATi M52P/M54P/56P)

3 2006-04-26 3




REV: 1.0




4 4




Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/04/22 Deciphered Date 2009/04/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HTW20 M/B LA-3171P
Date: Friday, April 28, 2006 Sheet 1 of 44
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Compal confidential
Model:HTW20 Fan Control
page 4
Yonah/Merom Thermal Sensor Clock Generator Accelerometer
File Name : LA-3171P uFCPGA-479 CPU ICS9LPRS325AKLFT LIS3L02AQ3TR
ADM1032AR
NAPA Platform page 4,5,6 page 4 page 15 page 27
1 1
H_A#(3..31)
FSB
H_D#(0..63)
LCD Conn. CRT & TV-out 533/667MHz
page 17 page 16

Intel Calistoga GMCH DDR2 -400/533/667 DDR2-SO-DIMM X2
BANK 0, 1, 2, 3 page 13,14

945PM/GM
ATI M52/M54/M56 Dual Channel
VGA/B Conn. PCBGA 1466
page 7,8,9,10,11,12
with 64/128/256MB page 17 PCI-Express
VRAM page 17 x16
PCI-E BUS 2.5GHz

New Card/B USB conn USB2.0
DMI x 4 Conn page 25 page 30
Bluetooth Conn
page 31
(port 1) (port 2)

2 USB 3.3V 48MHz PCI Express 2.5GHz 2


10/100/1000 LAN Mini Express Card (port 3)
USB port 6 USB port 2, 3, 4 USB port 7
RTL8111B/RTL8101E page 25 USB port 1 USB 3.3V 48MHz
3.3V 33 MHz
page 26 PCI BUS Azalia 3.3V 24.576MHz/48Mhz
MDC1.5
Intel ICH7-M SATA 1.5GHz
page 28


RJ45/11 CONN mBGA-652
page 26 VIA 1394 CardBus Controller PATA 3.3V ATA-100 Audio CKT AMP & Audio Jack
VT6311S ENE CB714 page 18,19,20,21 ALC861 page 28 TPA0232 page 29
page 24 page 22


SATA HDD Connector HTW20 Sub-board
SATA Master
1394 port Slot 0 5in1 Slot page 19 New Card/B
page 24 page 23 page 23
LED LS-2872P
PATA Slave
3
page 33
LPC BUS PATA ODD Connector 3

3.3V 33 MHz page 19 New Card/FPC
RTC CKT. LF-2873P
page 19
SW/B
Power On/Off CKT. TPM1.2 LS-2865P
page 33
SLB9635TT1.2
page 27 ENE KB910QF VGA/B
DC/DC Interface CKT. page 31
LS-3171P
page 34 LS-3172P

Power Circuit DC/DC TP/B
Page 35,36,37,38,39,40,41
LS-3173P
Touch Pad Int.KBD BIOS
4
page 32 page 33 page 32 4




Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/04/22 Deciphered Date 2009/04/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HTW20 M/B LA-3171P
Date: Friday, April 28, 2006 Sheet 2 of 44
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Voltage Rails Board ID / SKU ID Table for AD channel
Vcc 3.3V +/- 5%
Power Plane Description S1 S3 S5 Ra 100K +/- 5%
Board ID Rb V AD_BID min V AD_BID typ V AD_BID max
VIN Adapter power supply (19V) N/A N/A N/A
B+ AC or battery power rail for power circuit. N/A N/A N/A
0 0 0 V 0 V 0 V
1
+CPU_CORE Core voltage for CPU ON OFF OFF
1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V 1


+0.9VS 0.9V switched power rail for DDR terminator ON OFF OFF
2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+VCCP 1.05V switched power rail ON OFF OFF
3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+1.5VS 1.5V switched power rail ON OFF OFF
4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+1.8V 1.8V power rail for DDR ON ON OFF
5 100K +/- 5% 1.453 V 1.650 V 1.759 V
+1.8VS 1.8V switched power rail ON OFF OFF
6 200K +/- 5% 1.935 V 2.200 V 2.341 V
+2.5VS 2.5V switched power rail ON OFF OFF
7 NC 2.500 V 3.300 V 3.300 V
+3VALW 3.3V always on power rail ON ON ON*
+3VS 3.3V switched power rail ON OFF OFF
BOARD ID Table BTO Option Table
+5VALW 5V always on power rail ON ON ON*
+5VS 5V switched power rail ON OFF OFF Board ID PCB Revision BTO Item BOM Structure
+VSB +VSB always on power rail ON ON ON* 0 0.1 [email protected]
VGA [email protected]
+RTCVCC RTC power ON ON ON 1 0.2
New Card [email protected]
2 0.3
Giga LAN [email protected]
3 [email protected]
4 KILL SW [email protected]
2 2
5 BlueTooth [email protected]
6 5IN1 [email protected]
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
7

External PCI Devices SKU ID Table
DEVICE PCI Device ID IDSEL # REQ/GNT # PIRQ
SKU ID SKU
1394 D0 AD16 0 E 0
CARD BUS D4 AD20 2 A ,B 1
5IN1 D4 AD20 2 A ,B 2
3
4
5
6
KB910 I2C / SMBUS ADDRESSING 7
DEVICE HEX ADDRESS
3 3

SM1 24C16 A0H 1010000Xb
SM1 SMART BATTERY 16H 0001011Xb
SM2 ADM0132 98H 1001100Xb
CPU THERMAL MONITOR




ICH7-M SM Bus address
DEVICE HEX ADDRESS
DDR SO-DIMM 0 A0 10100000
DDR SO-DIMM 1 A4 10100100
CLOCK GENERATOR (EXT.) D2 11010010



4 4




Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/04/22 Deciphered Date 2009/04/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HTW20 M/B LA-3171P
Date: Friday, April 28, 2006 Sheet 3 of 44
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5 4 3 2 1




Place close to CPU within 500mil
+VCCP
7 H_A#[3..31] H_D#[0..63] 7
JP18A

H_A#3 J4 E22 H_D#0 XDP_TDI R56 1 2 56_0402_5%
H_A#4
H_A#5
L4
A3#
A4#
YONAH D0#
D1# F24 H_D#1
H_D#2 XDP_TMS R55 56_0402_5%
M3 A5# D2# E26 1 2
H_A#6 K5 H22 H_D#3
H_A#7 A6# D3# H_D#4 XDP_TDO R54
M1 F23 1 2 @ 56_0402_5%
H_A#8
H_A#9
N2
J1
A7#
A8#
D4#
D5# G25
E25
H_D#5
H_D#6
Thermal Sensor ADM1032ARM XDP_BPM#5 R53 1 2 56_0402_5%
D H_A#10 A9# D6# H_D#7 D
N3 A10# D7# E23
H_A#11 P5 K24 H_D#8 +3VS XDP_TRST# R57 1 2 56_0402_5%
H_A#12 A11# D8# H_D#9
P2 A12# D9# G24
H_A#13 L1 J24 H_D#10 XDP_TCK R47 1 2 56_0402_5%
H_A#14 A13# D10# H_D#11
P4 A14# D11# J23
H_A#15 P1 H26 H_D#12
H_A#16 A15# D12# H_D#13
R1 A16# D13# F26 1




1
H_A#17 Y2 K22 H_D#14
H_A#18 A17# D14# H_D#15 C209 R113
U5 A18# D15# H25
H_A#19 R3 N22 H_D#16 0.1U_0402_16V4Z @ 10K_0402_5%
H_A#20 A19# D16# H_D#17 2
W6 A20# D17# K25 1
H_A#21 U4 P26 H_D#18 C212




2
H_A#22 A21# D18# H_D#19 U8
Y5 A22# D19# R23
H_A#23 U2 L25 H_D#20 2200P_0402_50V7K H_THERMDA 2 1
H_A#24 A23# D20# H_D#21 2 D+ VDD1
R4 A24# D21# L22
H_A#25 T5 ADDR GROUP DATA GROUP L23 H_D#22 H_THERMDC 3 6
H_A#26 A25# D22# H_D#23 D- ALERT#
T3 A26# D23# M23
H_A#27 W3 P25 H_D#24 8 4
A27# D24# 31 EC_SMB_CK2 SCLK THERM#
H_A#28 W5 P22 H_D#25
H_A#29 A28# D25# H_D#26
Y4 A29# D26# P23 31 EC_SMB_DA2 7 SDATA GND 5
H_A#30 W2 T24 H_D#27
H_A#31 A30# D27# H_D#28
7 H_REQ#[0..4] Y1 A31# D28# R24
L26 H_D#29 ADM1032ARM_RM8
H_REQ#0 D29# H_D#30
K3 REQ0# D30# T25
H_REQ#1 H2 N24 H_D#31
H_REQ#2 REQ1# D31# H_D#32
K2 REQ2# D32# AA23
H_REQ#3 J3 AB24 H_D#33
H_REQ#4 REQ3# D33# H_D#34
L5 REQ4# D34# V24
V26 H_D#35 +5VS
H_ADSTB#0 D35# H_D#36
7 H_ADSTB#0 L2 ADSTB0# D36# W25
H_ADSTB#1 V4 U23 H_D#37
7 H_ADSTB#1 ADSTB1# D37#
U25 H_D#38
C D38# H_D#39 C
D39# U22 1




8




1
AB25 H_D#40 C596
D40#




1
W22 H_D#41 5 C D36




P
D41# 31 EN_DFAN1 +
Y23 H_D#42 7 FAN1_ON 1 2 2 Q40 10U_0805_10V4Z
CLK_CPU_BCLK A22 D42# H_D#43 0 R429 100_0402_5% B 2
FMMT619_SOT23 1SS355_SOD323
15 CLK_CPU_BCLK BCLK0 D43# AA26 1 2 6 -




G
CLK_CPU_BCLK# A21 HOST CLK Y26 H_D#44 R430 1 E




3




2
15 CLK_CPU_BCLK# BCLK1 D44# H_D#45 10K_0402_5% @ PU5B LM358DT_SO8
Y22




4
D45# H_D#46 C601
D46# AC26




1
AA24 H_D#47 0.1U_0402_16V4Z
H_ADS# D47# H_D#48 2 D37
7 H_ADS# H1 ADS# D48# AC22
H_BNR# E2 AC23 H_D#49 1 2 1N4148_SOT23
7 H_BNR# BNR# D49#
H_BPRI# G5 AB22 H_D#50 R431 8.2K_0402_5%
7 H_BPRI# BPRI# D50#
H_BR0# F1 AA21 H_D#51 JP4
7 H_BR0#




2
H_DEFER# BR0# D51# H_D#52 +FAN1_VOUT
7 H_DEFER# H5 DEFER# D52# AB21 1
H_DRD Y# F21 AC25 H_D#53
7 H_DRDY# DRDY# D53# 2
R94 H_HIT# G6 AD20 H_D#54
7 H_HIT# HIT# D54# 3
56_0402_5% H_HITM# E4 CONTROL AE22 H_D#55 +3VS 1 2
7 H_HITM# HITM# D55#
1 2 H_IERR# D20 AF23 H_D#56 R432 10K_0402_5% ACES_85205-0300
+VCCP H_LOCK# IERR# D56# H_D#57
7 H_LOCK# H4 LOCK# D57# AD24
H_RESET# B1 AE21 H_D#58 1
7 H_RESET# RESET# D58# 31 FAN_SPEED1
AD21 H_D#59 1 @
D59# H_D#60 C597
7 H_RS#[0..2] D60# AE25
H_RS#0 F3 AF25 H_D#61 C598 1000P_0402_50V7K
H_RS#1 RS0# D61# H_D#62 1000P_0402_50V7K 2
F4 RS1# D62# AF22
H_RS#2 H_D#63 2
G3 RS2# D63# AF26
H_TRDY# G2
7 H_TRDY# TRDY#
J26 H_DINV#0
DINV0# H_DINV#0 7
M26 H_DINV#1
DINV1# H_DINV#1 7
AD4 V23 H_DINV#2
BPM0# DINV2# H_DINV#2 7
AD3 AC20 H_DINV#3
BPM1# DINV3# H_DINV#3 7
AD1 BPM2#
B B
AC4 BPM3# H_DSTBN#[0..3] 7
H23 H_DSTBN#0
DBRESET# DSTBN0# H_DSTBN#1
20 DBRESET# C20 DBR# DSTBN1# M24
H_DBSY# E1 W24 H_DSTBN#2 Close to Fan Conn.
7 H_DBSY# DBSY# DSTBN2#
H_DPSLP# B5 AD23 H_DSTBN#3
19 H_DPSLP# DPSLP# DSTBN3# H_DSTBP#[0..3] 7
H_DPRSTP# E5 G22 H_DSTBP#0 Placement near to ICH7
19,41 H_DPRSTP# DPRSTP# DSTBP0#
H_DPWR# D24