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5 4 3 2 1
MODEL: REV: CHANGE LIST: MODEL : Z01 MB
1A FIRST RELEASE
PAGE FROM TO
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1B PAGE02. 1. R447,455,456 MODIFY to EP P/N:CS14752FB11
PAGE03. 1. STUFF HOLE6 P/N:FBZ01007010 , 2. STUFF HOLE7,8,15 P/N:FBED8001016 , 3. STUFF HOLE5 P/N:FBZ01006010 1 1A
PAGE03. 1. STUFF HOLE23,25 P/N:FBZ01003010 , 2. STUFF HOLE18 P/N:FBZ01004010 , 3. STUFF HOLE31 P/N:FBZ01005010
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PAGE05. 1. U22 MODIFY to GM965 P/N:AJ0QN120T04 , 2. R193,194 MODIFY to EP P/N:CS03902FB11 2 2B
PAGE06. 1. R242 MODIFY to EP P/N:CS33002JB23
Z01 PAGE08. 1. L52,53 MODIFY to EP P/N:CV01004KN00 3 2B
MotherBoard
blu
D
PAGE11. 1. R332 MODIFY to EP P/N:CS23243F930 , 2. U6 MODIFY to ICH8 P/N:AJ0QM740T03 D
PAGE12. 1. R244,R347,R353 MODIFY to EP P/N:CS00004JA40 , 2. L28 MODIFY to P/N:CV-1005MZ01 4 2B
PAGE13. 1. CN10 MODIFY to CRT P/N:DFDS15FR611
PAGE15. 1. R467 MODIFY to EP P/N:CS00004JA40,2. R50 MODIFY to EP P/N:CS31003J941,3.CN27 MODIFY to SATA P/N:DFHS22FR005 5 2B
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PAGE16. 1. CN16 MODIFY to RJ45/11 P/N:DFTJ15FR057
PAGE18. 1. R317,323 MODIFY to 0603 P/N:CS31003F949 , 2. R310 MODIFY to EP P/N:CS31003J941 6 2B
PAGE20. 1. PR100 MODIFY to EP P/N:CS51002FB11
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PAGE21. 1. PR86 MODIFY to EP P/N:CS24022FB13 , 2. PR38,82 MODIFY to 1% P/N:CS31002FB26 , 3. PR83 MODIFY to EP P/N:CS00004JA40 7 2B
PAGE22. 1. PR1 MODIFY to EP P/N:CS32002FB29 , 2. PR6 MODIFY to 1% P/N:CS51003F934
PAGE23. 1. PR106 MODIFY to 0 ohm P/N:CS00002JB38 , 2. UN-STUFF PR107,PC111 8 2B
PAGE24. 1. PR29 MODIFY to EP P/N:CS31003J941 2. PJ1 MODIFY to BATTERY P/N:DFHD07MR006
PAGE25. 1. PR70 MODIFY to EP P/N:CS32002FB29 9 2A
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2A PAGE02. 1. Connect VDDIO_CLK to +1.25V 2. un-stuff R292;R445;R308 3. stuff C575,C574,C576,C578,C573,C546 for EMI issue 10 3A 3B
PAGE06. 1. Connect ICH_PWROK SIGNAL TO NB CLPWROK 2.un-stuff R242;R235;R422;R222;R421;R423 3. R360,R361 only stuff for UMA
PAGE07. 1. MODIFY 22u to 10u 11 2B
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PAGE08. 1. R489 MODIFY to 0805 2. Stuff L50;R182;C238 for EV@ (MXM)
PAGE09. 1. Add PU for SMA_MA14 ; SMB_MA14 12 2B
PAGE10. 1. un-stuff R337,C115,C127,C129,C298,C302,C294,C283,C291
PAGE11. 1. Q18 MODIFY to P/N:AL07SZ04C27 2.R395 connect to VCCRTC 3.R336;R251;R419;R255 un-stuff 4.R226 connect to +3V_S5 5.ICH_PWROK to SB CLPWROK 13 3A 3B
PAGE11. 1. stuff C500,C509,C300,C513 33pF P/N:CH03306JB04 2. C507,C508 10pF change to 15pF P/N:CH01506JB06 , 3. stuff R238,R392,C2989 for Contr-LINK1
PAGE12. 1. VCCHDA & VCCSUSHDA change to 3V 14 3A
PAGE13. 1. ADD CRT DDC IN PU , 2. L8,L9,L10 P/N change to 0.47UH for MXM , 3. C22,C24,C25,C27,C31,C32 P/N change to 47pF for MXM
PAGE14. 1. CN6 MODIFY CONN. to 5 PIN P/N:DFHD05MRD98 15 3A 3B
C PAGE15. 1. MODIFY SWITCH BOARD PIN DEFINE 2. Modify FAN circuit , 2. MR1 P/N change to AL000268000 C
PAGE16. 1. C46,C47 27pF change to 33pF P/N:CH03306JB04 2. stuff C104,C105,C119,C112 0.1uF P/N:CH41003ZB35 16 3A 3B
PAGE17. 1. CARD READER COLAY TO CN28, DEL CN30 2. C311 change to 27pF P/N:CH02706JB06 3. stuff R209 4. un-stff R213,C325,U11
PAGE18. 1. CHANGE MDC & CODEC to 3V 2.Delete D12 3. stuff R314,R483,C393,C595 17 2A
PAGE19. 1. SWAP NBSWON# & ACIN 2. C363,C364 5.6pF change to 18pF P/N:CH01806JB07
PAGE20. 1. Modify PQ19 P/N 18 2B 3A
PAGE21. 1. Modify Capacitor P/N to meet ME height limit
PAGE22. 1. stuff PR74,PC69 2. Remove JP Pad 19 3A 3B
PAGE23. 1. stuff PR126,PC131,PC137 2. Remove JP Pad 3. un-stuff +1.8V
PAGE25. 1. un-stuff PR101,PQ21,PR22,PQ2,PR26,PR9,PR5,PC33,PC38,PC39,PC19,PC22,PU2 20 2B
2B PAGE02. 1. Change R293 to 2.2K for meet Intel Design checklist 21 3A
PAGE03. 1. Change XDP PU/PD resistors value to meet Intel Design checklist
PAGE04. 1. Un-stuff C28,C457 22 3A
PAGE05. 1. Add LVDS_VREF strap
PAGE06. 1. Add SDVO I2C strap 23 3A 3B
PAGE07. 1. Remove NB resistors to GND
PAGE08. 1. Remove DIODE for D27 2. Remove VCCA_DPLLA&B for external VGA 24 3A
PAGE10. 1. Add CRT & LVDS I2C Strap
PAGE11. 1. Un-stuff Control Link Vref1 25 3A 3B
PAGE12. 1. Remove reserve ICH8 HDA 1.5V power rail
PAGE13. 1. Modify LCD_VCC enable power rail 2. Add LVDS INV I2C Strap
PAGE14. 1. Add EMI solution for debug port PCI clock
PAGE15. 1. Change Q33,Q34 to MOSFET
B PAGE16. 1. Add PIN 59 & 3 B
PAGE18. 1. Change CN31 pin2 to +3V_S5 for Modem can't wake up from S3
PAGE19. 1. Add GPIO46 , 47
PAGE20~25. 1. Add EMI solution 2. Update Power component P/N
3A PAGE10. 1. Add +2.5V & +1.8V capacitors for nVIDIA MXM card
PAGE11. 1. Change C507,C508 to 15pF for RTC
PAGE13. 1. Add C609 & C610 to meet CM2009 specification
PAGE14. 1. Reserve +5VPCU & Add Q40,R540 for CIR
PAGE15. 1. Add C611 for PLC hall IC 2. Stuff R60 for G995
PAGE19. 1. CN24 un-stuff , 2. D322,D332 reserve for ESD
PAGE21. 1. Modify PC85 value
PAGE22. 1. Modify PR4,PC13 value for sequence
PAGE23. 1. Add PQ22 for nVIDIA MXM +1.8V
PAGE24. 1. Modify PF1 P/N
PAGE25. 1. Add PU2 for nVIDIA MXM +2.5V
3B PAGE10. 1. Remove R337 & Add R542,Q41,Q42 for Nvidia ACIN function
PAGE13. 1. Add D34~D36,D40 for ESD solution
PAGE15. 1. R484,R485,R486 from 330 change to 220 ohm for LED light issue 2. Add D41,D42,D43 for ESD 3. Stuff Q39
PAGE16. 1. Add C621,C622 for EMI solution 2. C112,C119 change to 100pF/50V for EMI
PAGE18. 1. Un-Stuff L55, Stuff U16,R470,R471 for internal Mic. issue
PAGE19. 1. Modify D32,D33 package to 0402 for ESD
PAGE23. 1. Add PR140,PR141 for +1.8V voltage
A PAGE25. 1. Stuff PR22,PR101,PQ2,PQ21 for nVIDIA MXM +1.8V & +2.5V Discharge A
PROJECT : ZO1 APPROVE BY: JIM HSU DRAWING BY:JACKY CHENG REV 3A
COVER SHEET 1 OF 1
MB ASSY'S P/N : 31Z01MB00XX PROJECT LEADER: JIM HSU DOCUMENT NO: 204 DATE :2007/04/14
Quanta Computer Inc.
5 4 3 2 1
5 4 3 2 1
Y5
14.318MHZ Z01 SYSTEM BLOCK DIAGRAM
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Clock Generator
SLG8SP512T Merom CPU CPU
D
U26
blu e.c 479 Pin uFCPGA
U21
Thermal Sensor
U5
D
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FSB
667/800 Mhz
.lap MXM
Ww
Intel NB DDRII
Type II Crestline
TV-OUT Dual Channel DDR2 SODIMM0
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PCI-Express X16 Lan
CN20 STD H9.9
965GM/965PM SODIMM1
TV-OUT 533/667 Mhz
TFT LCD Panel LVDS 1299 Pin FBGA CN19 - H5.2
CN18 - H9.2
VGA
14.1" WXGA U22
X4 DMI
C
CRT interface C
SATA HDD
SATA0
CN27 Intel SB MiniCard New Card POWER IC
Bluetooth PATA ODD ICH8M CN14 PCIE2 CN8 PCIE1 U24
CN6 USB4 PATA
NB82801HBM PCI-e X1
CN26
USB Port x 2 USB 2.0 676 Pin BGA PCI Bus interface Y1
CN21,23 USB3,5
25MHz
U6
USB Port x 2 Y4
CN12 USB0,1 RTC 32.768KHZ
1394 +Cardreader BroadCom
CN23
CCD Controller GIGA LAN
CN1 USB2 LPC Ricoh
Y3 BCM5787M
B
Winbond R5C832/R5C833 68 Pin QFN
B
32.768K
Realtek KBC PC8769L 128 Pin TQFP
AMP Audio Codec U2 PCIE3
ALC268 Azalia
G1411
U19 U17
BIOS IEEE 1394 Card reader
Audio Internal MMC SD Transformer RJ45
U14 CN13
conn MIC MS MS DUO U20 CN16
CN9 CN7
CIR
CN28,29,30
U28
Speaker AMP MIC In Line in
G1412 Touch Pad
CN5 U18
CN4
A SPDIF MDC K/B A
CN31
CN3
RJ11 FAN PROJECT : ZO1
CN17 CN15 Quanta Computer Inc.
Size Document Number Rev
Block Diagram 1A
Date: Thursday, May 17, 2007 Sheet 2 of 26
5 4 3 2 1
5 4 3 2 1
Clock Generator
L45
VDD_CK_VDD
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+3V
BK1608HS220_6_1A C386 C389
e.c
4.7u/6.3V_6 .1u/16V_4
U26 CLOCK_GEN
9 VDD_48 NC 48
VDD_CK_VDD 2
blu
VDD_PCI SMBCK
16 VDD_PLL3 SCL 64
D C385 C377 C381 C391 C390 C380 39 63 SMBDT D
VDD_SRC SDA
4.7u/6.3V_6 .1u/16V_4 .1u/16V_4 .1u/16V_4 .1u/16V_4 .1u/16V_4
SLG8SP512
61 38
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VDD_REF PCI_STOP# PM_STPPCI# 11
REV:B 55 VDD_CPU CPU_STOP# 37 PM_STPCPU# 11
MODIFY CLK_CPU_BCLK_R RN33 1 2 0_4P2R
Each Power pin have one 0.1u Capacitor 12 VDD_96_IO CPU0 54 CLK_CPU_BCLK 3
VDDIO_CLK 20 53 CLK_CPU_BCLK#_R 3 4
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+1.25V VDD_PLL3_IO CPU0# CLK_CPU_BCLK# 3
26 VDD_SRC_IO_1
C384 C378 C383 C379 C376 C387 C388 45 51 CLK_MCH_BCLK_R RN34 1 2 0_4P2R
VDD_SRC_IO_3 CPU1_MCH CLK_MCH_BCLK 5
36 50 CLK_MCH_BCLK#_R 3 4
VDD_SRC_IO_2 CPU1_MCH# CLK_MCH_BCLK# 5
4.7u/6.3V_6 .1u/16V_4 .1u/16V_4 .1u/16V_4 .1u/16V_4 .1u/16V_4 .1u/16V_4 49 VDD_CPU_IO
SRC8/ITP 47
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SRC8#/ITP# 46
R455 475/F_4 SATACLKREQ#_R 1 34 CLK_PCIE_3GPLL_R RN36 3 4 0_4P2R
11 SATACLKREQ# PCI0/CR#_A SRC10 CLK_PCIE_3GPLL 6
35 CLK_PCIE_3GPLL#_R 1 2
PCLK_LPC_DB_R SRC10# CLK_PCIE_3GPLL# 6
REV:B R461 33_4 3
14 PCLK_LPC_DB PCI1/CR#_B
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33 CLK_MCH_REQ# R447 475/F_4
MODIFY R465 33_4 PCLK_PCM_R 4
SRC11/CR#_H
32 NEW_CLKREQ#_R R456 475/F_4
CLK_MCH_OE# 6
17 PCLK_PCM PCI2/TME SRC11#/CR#_G NEW_CLKREQ# 14
R462 22_4 PCLK_591_R 5 30 CLK_PCIE_NEW_C_R RN43 3 4 0_4P2R
19 PCLK_591 PCI3 SRC9 CLK_PCIE_NEW_C 14
REV:C 31 CLK_PCIE_NEW_C#_R 1 2
SRC9# CLK_PCIE_NEW_C# 14
SEL_LCDCLK# 6
MODIFY PCI4/SEL_LCDCLK#
44 CLK_PCIE_MXM_R RN35 1 2 EV^0_4P2R
SRC7/CR#_F CLK_PCIE_MXM 10
R469 33_4 PCLK_ICH_R 7 43 CLK_PCIE_MXM#_R 3 4
11 PCLK_ICH PCIF5/ITP_EN SRC7#/CR#_E CLK_PCIE_MXM# 10
CG_XIN 60 41 CLK_PCIE_ICH_R RN37 1 2 0_4P2R
XTAL_IN SRC6 CLK_PCIE_ICH 11
40 CLK_PCIE_ICH#_R 3 4
SRC6# CLK_PCIE_ICH# 11
CG_XOUT 59 XTAL_OUT CLK_PCIE_MINI1_R RN42 3
SRC4 27 4 0_4P2R CLK_PCIE_MINI1 14
R460 33_4 FSA 10 28 CLK_PCIE_MINI1#_R 1 2
C
11 CLKUSB_48 USB_48/FSA SRC4# CLK_PCIE_MINI1# 14 C
MCH_BSEL1 57 24 CLK_PCIE_LAN_R RN41 3 4 0_4P2R
FSB/TEST/MODE SRC3/CR#_C CLK_PCIE_LAN 16
25 CLK_PCIE_LAN#_R 1 2
SRC3#/CR#_D CLK_PCIE_LAN# 16
R446 33_4 FSC 62
11 14M_ICH REF0/FSC/TESTSEL
21 CLK_PCIE_SATA_R RN40 3 4 0_4P2R
SRC2 CLK_PCIE_SATA 11
8 22 CLK_PCIE_SATA#_R 1 2
VSS_PCI SRC2# CLK_PCIE_SATA# 11
11 VSS_48
15 17 DREFSSCLK_R RN39 3 4 IV^0_4P2R
VSS_IO LCDCLK/27M DREFSSCLK 6
19 18 DREFSSCLK#_R 1 2
VSS_PLL3 LCDCLK#/27MSS DREFSSCLK# 6
CLKREQ_A# : SRC0 / SRC2 52 VSS_CPU
23 13 DREFCLK_R RN38 3 4 IV^0_4P2R
VSS_SRC1 SRC0/DOT96 DREFCLK 6
CLKREQ_B# : LCDCLK / SRC4 29 14 DREFCLK#_R 1 2
VSS_SRC2 SRC0#/DOT96# DREFCLK# 6
42 VSS_SRC3
CLKREQ_C# : SRC0 / SRC2 58 VSS_REF CKPWRGD/PWRDWN# 56 CK_PWRGD 11
CLKREQ_D# : LCDCLK / SRC4
SLG8SP512T: AL8SP512K05
CLKREQ_E# : SRC6
CLKREQ_F# : SRC8
CLKREQ_G# : SRC9
CLKREQ_H# : SRC10
CK505 SILEGO Clock Gen I2C Reserved for EMI
R458 *10K_4 SEL_LCDCLK# 0 : Pin 37,38 as SRC5 output 0 : Pin 13,14 & 17,18 for Internal VGA
+3V
PCLK_LPC_DB C575 22p_4
B R464 10K_4 B
1 : pin 37,38 as PCI_STOP & CPU_STOP 1 : 27M & 27M_SS & SRC0 for external VGA PCLK_PCM
R444 C574 10p_4
+3V
REV:C MODIFY
2
R466 *10K_4 PCLK_ICH_R CK505 SILEGO 4.7K_4
+3V
PCLK_591 C576 *10p_4
R459 10K_4 0 : Pin 46,47 as SRC output 0 : Pin 46,47 as SRC output 3 1 SMBDT
11,14,16 PDAT_SMB SMBDT 9
CLKUSB_48 C573 10p_4
1 : Pin 46,47 as CPU output 1 : Pin 46,47 as CPU output Q29 2N7002
R449
C557 R453 10K_4 NEW_CLKREQ#_R
+3V +3V
CG_XIN PCLK_ICH C578 10p_4
2
R443 10K_4 CLK_MCH_REQ# 4.7K_4
+3V
1
33p_4
Y5 R454 10K_4 SATACLKREQ#_R 3 1 SMBCK
+3V 11,14,16 PCLK_SMB SMBCK 9
14.318MHz 14M_ICH C546 4.7p_4
C560 Q21 2N7002
CG_XOUT
2
PU for ICS CLK GEN PCLK_PCM_R
R457 10K_4
+3V
33p_4 0 : CPU & SRC overclock allow REV:C
1 : CPU & SRC overclock not allow R496 *10K_4
MODIFY
CPU Clock select +1.05V +1.05V
BSEL Frequency Select Table
+1.05V
FSC FSB FSA Frequency
0 0 0 266Mhz
A REV:B R292 REV:B R445 A
R307 0 0 1 133Mhz
MODIFY *1K_4 MODIFY *1K_4
*1K_4 0 1 0 200Mhz
R293 R304
R288 0_4 MCH_BSEL2 FSC R441 0_4 MCH_BSEL1 R306 0_4 MCH_BSEL0 FSA 0 1 1 166Mhz
3 CPU_BSEL2 3 CPU_BSEL1 3 CPU_BSEL0
6 MCH_BSEL2
2.2K_4
6 MCH_BSEL1 6 MCH_BSEL0
2.2K_4 1 0 0 333Mhz PROJECT : ZO1
REV:B REV:C REV:B
1 0 1 100Mhz
MODIFY R290 MODIFY MODIFY R448 REV:B R308 Quanta Computer Inc.
MODIFY 1 1 0 400Mhz Size Document Number Rev
*1K_4 *1K_4 *1K_4
1 1 1 Reserved CLOCK GENERATOR CK505 W/REGULATOR 2B
Date: Thursday, May 17, 2007 Sheet 3 of 26
5 4 3 2 1
5 4 3 2 1
U21A U21B MAXIM 6657 : AL006657020
5 H_A#[35:3]
H_A#3 J4 A[3]# D[0]# E22 H_D#0
H_D#[63:0] 5
SMBUS Address : 98 GMT G781 : AL000781101
ADDRESS
H_A#4 L5 F24 H_D#1 A6 THERMAL
A[4]# D[1]# 11 H_A20M# A20M#
H_A#5 L4 E26 H_D#2 A5 B25 H_THERMDC
A[5]# D[2]# 11 H_FERR# FERR# THERMDC +3V
H_A#6 K5 G22 H_D#3 C4 A24 H_THERMDA
A[6]# D[3]# 11 H_IGNNE# IGNNE# THERMDA
DATA
ICH
H_A#7 H_D#4
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M3 A[7]# D[4]# F23