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5 4 3 2 1
+VCCP
o m
.c
+3V
D R534 D
1.2K +-1%
NS VCC3_CLK
1
1
1
R594 FB22 FB23
R535 R_0402 0 +-5% R_0402 BSEL0
s
6 CPU_BSEL0 600 OHM/1.5A 600 OHM/1.5A
8.2K +-5% C366 C313 C363 C315 C345
R532 1K +-1%
R533 0.047UF/16V 0.047UF/16V 0.1UF/10V 0.1UF/10V 10uF/6.3V R473 C365 C414
8 MCH_BSEL0 2 +-5%
ic
C_0402 C_0402 C_0402 C_0402 C_0805
1.2K +-1% 0.047UF/16V 10uF/6.3V
R_0603 C_0402 C_0805
R_0603 R354
NS For SLG8LP453 buildin Pulldown res.
2 +-5%
+VCCP R_0603
t
+V3.3S_CLKVDD1
NS R_0402
C350 C513 CLK_CPU_BCLK R316 54.9 +-1%
R496 C413 NS R_0402
Y4 R337 0.1UF/10V 10uF/6.3V CLK_CPU_BCLK# R317 54.9 +-1%
1.2K +-1% 0.047UF/16V C_0402
1 +-5%
a
NS C_0402 C_0805 NS R_0402
U19
7
1
1
R595 R_0603 CLK_MCH_BCLK R318 54.9 +-1%
R500 R_0402 0 +-5% R_0402 BSEL1 21 11 NS R_0402
VDD_PCI1
VDD_PCI0
6 CPU_BSEL1 VDD_SRC0 VDD_48 C312
14.31818MHZ VDD_A_CR 28 CLK_MCH_BCLK# R319 54.9 +-1%
0 +-5% VDD_SRC1 VDD_REF_CR 0.047UF/16V NS R_0402
C311 C310 34 VDD_SRC2 VDD_REF 48
R463 1K +-1% C_0402 DREFSSCLK R497 54.9 +-1%
R482 33PF/50V 33PF/50V 55 NS R_0402
8 MCH_BSEL1 C314 C324 PCI_STOP# STP_PCI# 17
C_0603 C_0603 42 54 DREFSSCLK# R530 54.9 +-1%
1.2K +-1% 0.047UF/16V 10uF/6.3V VDD_CPU CPU_STOP# STP_CPU# 17
m
RN4 0X2 NS R_0402
R_0603 C_0402 C_0805 CPU1 DREFCLK R389 54.9 +-1%
NS 37 VDD_A CPU1 41 1 2 CLK_MCH_BCLK 8
40 CPU#1 3 4 NS R_0402
CPU1# CLK_MCH_BCLK# 8
38 RN3 0X2 DREFCLK# R465 54.9 +-1%
VSS_A CPU0 R_SMT4_0402 NS R_0402
CPU0 44 1 2 CLK_CPU_BCLK 6
CPU#0 CLK_PCIE_ICH# R505 54.9 +-1%
e
C CPU0# 43 3 4 CLK_CPU_BCLK# 6
XTAL_IN 50 R_SMT4_0402 NS R_0402 C
+VCCP XTAL_IN CLK_PCIE_ICH
RN5 0X2 R495 54.9 +-1%
XTAL_OUT 49 36 ITP 1 2 CLK_ITP 6 NS R_0402
R381 33 +-5% XTAL_OUT CPU_2_ITP/SRC_7 ITP# NS CLK_PCIE_SATA# R456 54.9 +-1%
17 CLK48_USB CPU2_ITP/SRC7# 35 3 4 CLK_ITP# 6
BSEL0 12 R_SMT4_0402 NS R_0402
h
R352 FSA/USB_48 R338 10K +-5% CLK_PCIE_SATA R531 54.9 +-1%
SRC6/CLKREQA# 33
BSEL1 16 32 NS
1.2K +-1% FSB/TEST_MODE SRC6#/CLKREQB# R364 10K +-5% RN19 0X2
R_0603 R378 33 +-5% BSEL2 PCIE5 NS PCIE5 1
NS 31 PCLK_591 53 REF1/FSC/TEST_SEL SRC5 31 2 PCIECLK_3G 20
R593 PCIE#5 PCIE#5 3
c
SRC5# 30 4 PCIECLK_3G# 20
R345 R_0402 0 +-5% 8.2K +-5% BSEL2 5 RN30 0X2
R_SMT4_0402
6 CPU_BSEL2 PCI5
26 PCIE4 PCIE#4 1 2 PCIECLK_WLAN# 20
R_0402 SRC4 PCIE#4 PCIE4 3
4 PCI4 SRC4# 27 4 PCIECLK_WLAN 20
R363 1K +-1% R362 RN18 0X2
R_SMT4_0402
s
3 24 PCIE3 PCIE#3 1 2 NS R_0402
8 MCH_BSEL2 1.2K +-1% PCI3 SRC3 CLK_PCIE_MCH# 8
R353 10K +-5% 25 PCIE#3 PCIE3 3 4 CLK_PCIE_MCH R501 54.9 +-1%
R_0603 +3V SRC3# CLK_PCIE_MCH 8
NS R346 33 +-5% PCI2 56 0X2
RN17 R_SMT4_0402 NS R_0402
NS 24 PCLK_LAN PCI2/REQ_SEL
-
22 PCIE2 PCIE#2 1 2 CLK_PCIE_SATA# CLK_PCIE_SATA# 15 CLK_PCIE_MCH# R502 54.9 +-1%
SRC2 PCIE#2 PCIE2 3
26 PCLK_OZ711
R380 33 +-5% 9 PCIF1/DREF_SEL SRC2# 23 4 CLK_PCIE_SATA CLK_PCIE_SATA 15
R498 10K +-5% R_0603 RN16 0X2
+3V
R379 33 +-5% PCIF0 8 19 PCIE1 PCIE1# 1 2R_SMT4_0402
16 PCLK_ICH7 PCIF0/ITP_EN SRC1 CLK_PCIE_ICH# 17
20 PCIE1# PCIE1 3 4
R326 0 +-5% CGCLK_SMB SRC1# RN15 0X2 R_SMT4_0402 CLK_PCIE_ICH 17
change from 49.9 to 54.9
p
14,16 SMB_CLK_ICH7 46 SCLOCK
DREF_SSCLK 17 3 4 R_SMT4_0402
DREFSSCLK DREFSSCLK 8
R325 0 +-5% CGDAT_SMB 47 18 1 2 DREFSSCLK# DREFSSCLK# 8
14,16 SMB_DATA_ICH7 SDATA DREF_SSCLK#
IREF 39 RN14 0X2 Note:Pls confirm need BIOS modify?
IREF R_SMT4_0402
14 3 4DREFCLK
to
DOT96 DREFCLK 8
13 VSS_48 DOT96# 15 1 2DREFCLK# DREFCLK# 8
Place termination close to source IC
For SLG8LP453. 29 VSS_SRC
45 VSS_CPU
2 10 CKGEN_EN#
VSS_PCI0 VTT_PWRGD#/PD CKGEN_EN# 36
B
6 VSS_PCI1 B
51 52 R334 12.1 +-1%
VSS_REF REF CLK14_ICH7 17
SLG8LP453B/SLG84420
p
Check the CLK14_ICH6 clock SI after bring up!!
If need changed to 33R
SLG8LP453 buildin dumping and terminal res.
. la
w w
w
5 4 3 2 1
8 H_A#[31:3]
o m
.c
U3A
8 H_D#[63:0] H_D#[63:0] 8
H_A#3 J4 H1 U3B
A[3]# ADS# H_ADS# 8
H_A#4 L4 E2 H_D#0 E22 AA23 H_D#32
A[4]# BNR# H_BNR# 8 D[0]# D[32]#
D H_A#5 M3 G5 H_D#1 F24 AB24 H_D#33 D
A[5]# BPRI# H_BPRI# 8 D[1]# D[33]#
H_A#6 K5 H_D#2 E26 V24 H_D#34
A[6]# D[2]# D[34]#
0
ADDR GROUP
ADDR GROUP
H_A#7 M1 H5 H_D#3 H22 V26 H_D#35
A[7]# DEFER# H_DEFER# 8 D[3]# D[35]#
DATA GRP 0
H_A#8 N2 F21 H_D#4 F23 W25 H_D#36
A[8]# DRDY# H_DRDY# 8 D[4]# D[36]#
H_A#9 J1 E1 H_D#5 G25 U23 H_D#37
DATA GRP 2
s
A[9]# DBSY# H_DBSY# 8 D[5]# D[37]#
H_A#10 N3 +VCCP H_D#6 E25 U25 H_D#38
H_A#11 A[10]# H_D#7 D[6]# D[38]# H_D#39
P5 A[11]# BR0# F1 H_BREQ#0 8 E23 D[7]# D[39]# U22
H_A#12 P2 R76 H_D#8 K24 AB25 H_D#40
H_A#13 A[12]# H_IERR# H_D#9 D[8]# D[40]# H_D#41
L1 A[13]# IERR# D20 G24 D[9]# D[41]# W22
CONTROL
ic
H_A#14 P4 B3 H_D#10 J24 Y23 H_D#42
A[14]# INIT# H_INIT# 15 D[10]# D[42]#
H_A#15 P1 56 +-5% H_D#11 J23 AA26 H_D#43
H_A#16 A[15]# H_D#12 D[11]# D[43]# H_D#44
R1 A[16]# LOCK# H4 H_LOCK# 8 H26 D[12]# D[44]# Y26
L2 H_D#13 F26 Y22 H_D#45
8 H_ADSTB#0 ADSTB[0]# H_CPURST# 8 D[13]# D[45]#
B1 H_CPURST# H_D#14 K22 AC26 H_D#46
8 H_REQ#[4:0] RESET# H_RS#[2:0] 8 D[14]# D[46]#
t
H_REQ#0 K3 F3 H_RS#0 H_D#15 H25 AA24 H_D#47
H_REQ#1 REQ[0]# RS[0]# H_RS#1 D[15]# D[47]#
H2 REQ[1]# RS[1]# F4 8 H_DSTBN#0 H23 DSTBN[0]# DSTBN[2]# W24 H_DSTBN#2 8
H_REQ#2 K2 G3 H_RS#2 G22 Y25
REQ[2]# RS[2]# 8 H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 8
H_REQ#3 J3 G2 J26 V23
REQ[3]# TRDY# H_TRDY# 8 8 H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 8
H_REQ#4 L5 +VCCP
REQ[4]# 8 H_D#[63:0] H_D#[63:0] 8
a
8 H_A#[31:3] HIT# G6 H_HIT# 8
H_A#17 Y2 E4 H_D#16 N22 AC22 H_D#48
A[17]# HITM# H_HITM# 8 D[16]# D[48]#
H_A#18 U5 H_D#17 K25 AC23 H_D#49
A[18]# D[17]# D[49]# H_DINV#[3:0] 8
H_A#19 R3 AD4 BPM0# H_D#18 P26 AB22 H_D#50
A[19]# BPM[0]# D[18]# D[50]#
1
ADDR GROUP
ADDR GROUP
H_A#20 W6 AD3 BPM1# R65 H_D#19 R23 AA21 H_D#51
A[20]# BPM[1]# D[19]# D[51]# H_DSTBP#[3:0] 8
H_A#21 U4 AD1 BPM2# H_D#20 L25 AB21 H_D#52
H_A#22 A[21]# BPM[2]# BPM3# 54.9 +-1% H_D#21 D[20]# D[52]# H_D#53
Y5 A[22]# BPM[3]# AC4 L22 D[21]# D[53]# AC25 H_DSTBN#[3:0] 8
DATA GRP 1
H_A#23 PRDY# +VCCP R_0603 H_D#22 H_D#54
DATA GRP 3
U2 A[23]# PRDY# AC2 L23 D[22]# D[54]# AD20
XDP/ITP SIGNALS
m
H_A#24 R4 AC1 PREQ# +3V TDI H_D#23 M23 AE22 H_D#55
H_A#25 A[24]# PREQ# TCK H_D#24 D[23]# D[55]# H_D#56
T5 A[25]# TCK AC5 P25 D[24]#