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Mar.7 '03 CPU
Banias
Pebble Qual Build 91.42Y01.001
Ver.B1
CLK GEN P.4,5 QVJ3/5/6 02203-SE
ICS 950810CG
Cypress CY28346-2 HOST BUS DVO B S-video,DVI,CRT
P.3 CH7009B Vcc_core: 0.7~1.708V @32A
P.10 Vccp:1.05V @3A
DDR MEM BUS GMCH Vcc_GMCH:1.2V @1.65A
Vcc_mem:2.5V @1.2A + 2*SO-DIMM
266/200 Montara-GM CRT
SO-DIMM*2 P.7,8,9
Ver.A2
QE27 LCD
P.11
P.12,13,14 LVDS CONN
BlueTooth P.11 I/F IC Smart
Module conn.
USB 1.1 P.31
HUB I/F
NCN6000
Card
P.21 P.21
Primary
IDE
P.19
USB 2.0
P.22 USB*4 ICH4-M PCI BUS
P.15,16,17
Ver.B1 CardBus PWR SW
POWER QD68
PCI7510 Socket TPS2211A
P.21
USB Pass 2 SLOT*1
P.22 P.20
P.21
AC97 MiniPCI
P.23
1394 conn.
P.21

LPC BUS MDC
S/W 1.05V/1.2V
Gigabit LAN




Xformer
MODEM
RJ11 MAX1715
X-BUS P.19 Broadcom LAN Switch VCC_IO:1.05V @3A
BIOS IrDA PI31301DA RJ45
P.30 SMsC P.31
INT SPK BCM5705M
P.18 P.18
Vcc_GMCH:1.2V @1.65A
P.38
SIO&KBC mono A1
Ver.B
P.18

LPC47N254 CPU CORE POWER
Serial P.25 P.18 SC1476 Ver.A2
P.28,29
Port Vcc_core: 0.7~1.708V @32A
P.31
P.36
CODEC OP
OP AMP STAC9750
TouchPad
TPA0312
CC1 P.24
QSW DDR 2.5V/1.25V
P.31 P.31 P.25 SC1486
P.26
KB INT MIC VCC_mem:2.5V @1.2A+2*SO-DIMM
CONN Headphone
Mic P.25 P.37
jack
P.25 jack
K/B P.25
3V/5V/12V CHARGER
MAX1632
P.35 MAX1645B
USB 2.0 PS2 SMBus LPC BUS SPDIF MODEM PCI BUS S-video CRT DVI RJ45
INPUT OUTPUT
1.5V/1.8V
D- Dock
+DC_IN BATT+
MAX1644/MAX1792 +RTC_PWR
P.27 500mA
P.38 P.39




Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title


DELL-Wistron confidential Size
Custom
BLOCK DIAGRAM
Document Number
PEBBLE--02203
Rev
SE

Date: Thursday, March 13, 2003 Sheet 1 of 40
01.BLOCK DIAGRAM
02.TABLE OF CONTENT PCI TABLE +DC_IN +DC_IN 27,37,39

DOCK_DC_IN DOCK_DC_IN 27
03.CLOCK GENERATOR
DEVICE IDSEL IRQ REQ# / GNT# DREQ/DGNT PWR_SRC PWR_SRC 11,22,27,33,35,36,37,38,39
04.CPU
PIRQD# DOCK_PWR_SRC DOCK_PWR_SRC 27
05.CPU CONFIGURATION PCMCIA PCI7510 AD17 PIRQC# REQB# / GNTB# REQ#1 / GNT#1
VCC_IO VCC_IO 4,5,6,7,9,16,17,33,38
06.MAX6654 & ITP & FAN LAN Broadcom
BCM5705M AD16 PIRQC# REQ4# / GNT4# VCC_CORE VCC_CORE 5,33,36
07.GMCH (1/3)
+1.5VRUN +1.5VRUN 4,7,8,9,10,11,15,17,33
08.GMCH (2/3) MINIPCI SLOT AD19 PIRQB# REQ3# / GNT3#
PIRQD# +1.8VRUN +1.8VRUN 4,33,38
09.GMCH (3/3)
+1.2VRUN +1.2VRUN 7,9,38
10.S-VIDEO/DVI D-DOCK AD24 PIRQB# REQ0# / GNT0#
11.LCD / INVERTER & CRT CONN
+3VRUN +3VRUN 3,4,6,8,9,10,11,12,15,16,17,18,19,23,24,26,28,29,31,32,33,34,36,38,40
12.DDR SOCKET
+3VSUS +3VSUS 6,11,15,16,17,18,19,20,21,23,25,27,31,33,34,37,38,40
13.DDR SERIAL/TERMINATOR RESISTOR
14.DDR DECOUPLING CAP
15.ICH-4M (1/3)
Montania to Montania+ changes +3VALW

+3.3VRTC
+3VALW 16,25,27,28,29,30,34,40

+3.3VRTC 16,28,34,37

+5VRUN +5VRUN 6,8,10,11,17,19,23,26,29,31,32,33,34,36,37,40
16.ICH-4M (2/3) 1.Changed VR resistor to generate 1.35V for MGM+ core(R529,R530)
17.ICH-4M (3/3)
2.Changed R112 from 27.4 to 37.4 Ohm (changes HLZCOMP for MGM+) +5VSUS +5VSUS 6,11,17,21,22,24,25,31,32,33,34,35,37,38,40
18.GIGABIT LAN
+5VALW +5VALW 11,27,28,32,33,34,39
19.HDD & MDC CONN. 3.Put R612,R613,R614 1K ohm
+5V_QDOCK +5V_QDOCK 26
20.CARDBUS CONTROLLER
4.Need Changed PSWING,HLVREF for MGM+ if use MGM core +3VAUX_LAN +3VAUX_LAN 18,23,33
21.CARDBUS & 1394 CONNECTOR & POWER SWITCH (For Pebble don't need change because we use +1.5VRUN)
+1.2VAUX_LAN +1.2VAUX_LAN 18
22.USB POWER SWITCH & CONN
5.Layour meet DDR333 require +2.5VAUX_LAN +2.5VAUX_LAN 18,27
23.MINIPCI CONN (For Pebble already done)
BATT+ BATT+ 39
24.AUDIO CODEC
+5VHDD +5VHDD 19,33
25.AUDIO AMP & JACK
26.D DOCK BUFFERS
27.D DOCK
28.SIO (1/2)
LCDVDD LCDVDD 11
29.SIO (2/2)
30.BIOS
AC97_5V AC97_5V 19
31.TOUCHPAD, KB ,BLUETOOTH CONN, IR
AC97_3V AC97_3V 19
32.LED & BUTTON CONN
CRT_VCC CRT_VCC 11
33.POWER PLANE ENABLES
CBS_VCC CBS_VCC 20,21
34.POWER-ON RESET LOGIC
CBS_VPP CBS_VPP 21
35.DCDC 3V/5V
CBS_VCCF CBS_VCCF 21
36.CPU VCORE-IMVP4 SC1476
+1.25VRUN +1.25VRUN 13,14,33,37
37.DDR 2.5V/1.25V & RTC & BIRIDGE BATTERY
+2.5VSUS +2.5VSUS 6,7,9,12,14,33,37
38.VCC_IO,1.2V, 1.5V, 1.8V
ICH_VBIAS ICH_VBIAS 16
39.CHARGER
VCC_RTC VCC_RTC 16
40.HOLES & GND PADS
+RTCSRC +RTCSRC 37

+RTC_PWR +RTC_PWR 34,35,37,39,40



CG_* : CPU GTL+
CC_* : CPU CMOS
M_* : MEMORY BUS
G_* : AGP BUS
P_* : PCI BUS
HL_* : HUB LINK I/F
LPC_* : LPC I/F
ICH_AC_* : AC'97 LINK I/F
IDE_* : IDE BUS
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Table of Content
Size Document Number Rev
A3 SD
PEBBLE--02203
Date: Monday, February 24, 2003 Sheet 2 of 40
+3VRUN
L18 S.B. PLACE NEAR EACH PIN
1 2 CLKGEN_+3VRUN
+3VRUN Filtering CKT for MLB-201209-19




1




1




1




1




1
Host Freq. Setting 48MHz power plane
L21 *S.C. BC150 BC185 BC153 BC184 BC151 BC187 BC475 BC155
2 1 CLKGEN_48MPWR SC10U10V-U1 SCD1U16V3KX SCD1U10V2MX-1 SCD1U10V2MX-1 SCD1U16V3KX SCD1U10V2MX-1 SCD1U10V2MX-1 SCD1U16V3KX




2




2




2




2




2
FS1/0 = 00 66MHz S.C. S.C. S.C. S.C.




1
FS1/0 = 01 100MHz MLB201209-1
BC190 BC189 BC485 BC188
FS1/0 = 10 200MHz SCD1U16V3KX SC10U10V-U1 SCD01U50V3KX SCD1U16V3KX +3VRUN




2
FS1/0 = 11 133MHz S.C. S.C.
L20
CLKGEN_APWR 1 2
FS2 = 0 unbuffer mode (disable 66MHz-IN) MLB201209-1




1




1
FS2 = 1 buffer mode *S.C.
BC484 BC186 BC183
SCD1U10V2MX-1 SCD01U50V3KX SC10U10V-U1




2




2
Mult0 = 0 Rr=221,Iref=5mA =>[email protected] No stuff: U34 S.C.
Mult0 = 1 Rr=475,Iref=2.32mA =>[email protected] caps are internal to CK-TITAN.
1 26
VDDREF VDDA RN7 SRN33-2-U2
8 CLK_CPU 4
BC152 VDDPCI R545 1
CPU & MEMORY Freq. Selection 14 27 1 4 2 49D9R3F
VDDPCI GND R546 1
19 2 3 2 49D9R3F
+3VRUN VDD3V66
32
VDD3V66 CPUCLKT2
45 S.C. CLK_CPU# 4
SC10P 37 44 RN5 SRN33-2-U2
+3VRUN VDD48 CPUCLKC2 CLK_MCH 7




2
46 1 4 R214 1 2 49D9R3F
X3 VDDCPU R216 1
50 49 2 3 2 49D9R3F
VDDCPU CPUCLKT1
1




X-14D318MHZ-1-U 48 S.C.
CPUCLKC1 CLK_MCH# 7
1




1




2 RN6 SRN33-2-U2 R523 1 2 0R3-U
X1 CLK_ITP_CPU 4




1
R544 R520 R519 BC154 52 1 4 CLK_ITP_R R215 1 2 0R3-U
CPUCLKT0 CLK_ITP 6
10KR3 1KR3 DUMMY-R3 3 51 2 3 CLK_ITP#_R R217 1 2 0R3-U
X2 CPUCLKC0 CLK_ITP# 6
R218 R524 1 2 0R3-U
CLK_ITP_CPU# 4
SC10P 1 2 SEL2 40 24 TP108
FS2 3V66_5
2




2




2




CLK_ITP_R R220 1 2 49D9R3F
CK-408
23 TP110
CK-408_MULT0 1KR3 3V66_4 R267 1
55 22 S.D. 2 22R3 CLK66_GMCH 8 CLK_ITP#_R R221 1 2 49D9R3F
FS1 3V66_3 R266 1 2 22R3 S.C.
3V66_2
21 CLK66_ICH 15 NS
1




54
FS0 S.D.
+3VRUN
1




1




R543 25 7 R209 1 2 33R3
16 PM_SLP_S1# PD# PCICLK_F2 CLKPCIF_ICH 16
DUMMY-R3 R522 34
16 PM_STPPCI# PCI_STOP#
R521 1KR3 R291 53 6 TP107
16,36 PM_STPCPU# CPU_STOP# PCICLK_F1
DUMMY-R3 1 2 VTT_PWRGD# 28
VTT_PWRGD#
2




CK-408_MULT0 43 5 TP105
MULTSEL0 PCICLK_F0
2




10KR3
2




CK-408_SDA 29 18 R265 1 2 33R3
SDATA PCICLK6 PCLK_SIO 29
CK-408_SCL 30
SCLK R269 1
S.C. 17 2 22R3 PCLK_PCM 20
PCICLK5
3




D 8 DREFSSCLK R270 1 2 33R3 33 *S.C.
R626 1 3V66_0
7,34 CK408_IMVP_PWRGD 1 20 CLK_48M_SCR 2 33R3 35 16 TP109
Q31 3V66_1/VCH_CLK PCICLK4
G S.C.
S 1 R273 2 42 13 R264 1 2 33R3 PCLK_DOCK 27
IREF PCICLK3
2




2N7002 475R3F
41 12 R268 1 2 22R3
GND PCICLK2 PCLK_MINI 23
*S.C.
11 R210 1 2 22R3
PCICLK1 PCLK_LAN 18
4
GND *S.C.
9 10 TP106
GND PCICLK0
15
GND
S.C.
20 39 R272 1 2 33R3
GND 48MHZ_USB CLK48_ICH 15
+3VRUN 31
+3VRUN GND R271 1
36 38 2 33R3 CLK48_DREF 8
GND 48MHZ_DOT
47
GND R212 1
56 2 33R3 CLK14_ICH 16
REF
1




R211 1 2 33R3 CLK14_SIO 29
3
4




R292 ICS950810CG
10KR3 RN18 S.B.
SRN10KJ
2




2
1
1
G




Q33
12,16,18,23 SMBC_ICH 3 2 CK-408_SCL
2N7002
1
S
D




G




Q32
12,16,18,23 SMBD_ICH 3 2 CK-408_SDA
2N7002
S
D




Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Clock GEN.
Size Document Number Rev
A3 SD
PEBBLE--02203
Date: Thursday, March 13, 2003 Sheet 3 of 40
U7C
CPU_VCCA +1.8VRUN 7 GTL_D#[15..0] GTL_D#[47..32] 7

R450 GTL_D#15 C25 Y25 GTL_D#47
D15# D47#
1 2 GTL_D#14 E23 AA26 GTL_D#46
D14# D46#
GTL_D#13 B23 Y23 GTL_D#45
0R3-U D13# D45#
For CPU VCCA[0:3] PLL +1.5VRUN
GTL_D#12 C26
D12# D44#
V26 GTL_D#44
GTL_D#11 E24 U25 GTL_D#43
place one 0.01u & 10u for R451 GTL_D#10 D24