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A B C D E
1 1
Compal Confidential
2 2
NAL00 Schematics Document
AMD L310/L110 Processor with RS780MN/SB710/M92-S2/S3 LP
3
2009-04-24 3
REV:0.2
[email protected]
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5401
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401728
Date: Monday, May 04, 2009 Sheet 1 of 49
A B C D E
A B C D E
Compal Confidential
Model Name : NAL00
VRAM 512MB Fan Control AMD S1G1 Processor
page 4 Memory BUS(DDRII) 200pin DDRII-SO-DIMM X2
1 64M16 x 4 uPGA-638 Package 1
page 18 Dual Channel BANK 0, 1, 2, 3 page 8,9
page 4,5,6,7 1.8V DDRII 667/800
LVDS Conn. DDR3
page 21 Hyper Transport Link
ATI M92-S2 LP 16 x 16 5 in 1 socket
uFCBGA-631 PCI-Express 8x Thermal Sensor Clock Generator page 30
CRT Conn. Page 14,15,16,17,19
Gen1 ATI RS780MN ADM1032 SLG8SP626VTR
page 23
page 6 page 20
uFCBGA-528 Card Reader
RTS5159
HDMI Conn. page 30
page 22
PCI-Express 1x page 31
page 32 page 31 page 32
page 10,11,12,13
Port 2 Port 0 Port 1 USB conn To IO Board Mini Card 2
BT Conn (WWAN)
MINI Card 2 MINI Card 1 To IO board A link Express2 X2 USB conn X 2 page 31
Mini Card 1 Port 4
2
WWAN page 31
WLANpage 31 LAN(GbE) page 21 2
Realtek RTL8111CA Camera (WLAN)
page 31
ATI SB710 Port 1 Port 0
USB Port 6 Port 2 Port 3 Port 12 Port 8 Port 5
3.3V 48MHz
uFCBGA-528
HD Audio 3.3V 24.576MHz/48Mhz
S-ATA
port 0 port 1 HDA Codec
page 24,25,26,27,28
IO Board ALC269X-GR Digital MIC
page 31 page 37
SATA HDD CDROM page 36
PWR Board Conn.
page 29
Conn. 29
page
page 35
LPC BUS Phone Jack x2
page 37
TP Board
page 34
3 LID SW/Cap sensor Board 3
page 33
ENE KB926
LED page 33
page 35
Power On/Off CKT.
page 35
Int.KB BIOS
page 34 page 34
RTC CKT.
page 24
DC/DC Interface CKT.
page 38
Power Circuit
page 39,40,41,42,43,44,4546,47
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5401
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401728
Date: Monday, May 04, 2009 Sheet 2 of 49
A B C D E
A B C D E
SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Voltage Rails Full ON HIGH HIGH HIGH HIGH ON ON ON ON
Power Plane Description S1 S3 S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
VIN Adapter power supply (19V) N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
B+ AC or battery power rail for power circuit. N/A N/A N/A
1
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1
+CPU_CORE Core voltage for CPU (0.7-1.2V) ON OFF OFF
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+NB_CORE 1.0V switched power rail ON OFF OFF
+0.9V 0.9V switched power rail for DDR terminator ON ON OFF
+1.1VS 1.1V switched power rail for NB VDDC & VGA ON OFF OFF Board ID / SKU ID Table for AD channel
+1.2V_HT 1.2V switched power rail ON OFF OFF Vcc 3.3V +/- 5%
+VGA_CORE 0.90-0.95V switched power rail ON OFF OFF Ra/Rc/Re 100K +/- 5%
+1.5VS 1.5V power rail for PCIE Card ON OFF OFF Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+1.8V 1.8V power rail for CPU VDDIO and DDR ON ON OFF 0 0 0 V 0 V 0 V
+1.8VS 1.8V switched power rail ON OFF OFF 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+2.5VS 2.5V for CPU_VDDA ON OFF OFF 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+3VALW 3.3V always on power rail ON ON ON* 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+3V_LAN 3.3V power rail for LAN ON ON ON 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+3VS 3.3V switched power rail ON OFF OFF 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
+5VALW 5V always on power rail ON ON ON* 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
+5VS 5V switched power rail ON OFF OFF 7 NC 2.500 V 3.300 V 3.300 V
2 2
+VSB VSB always on power rail ON ON ON*
+RTCVCC RTC power ON ON ON
BOARD ID Table BTO Option Table
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Board ID PCB Revision BTO Item BOM Structure
External PCI Devices 0 0.1 Discrete VGA@
Device IDSEL# REQ#/GNT# Interrupts 1 0.2 UMA UMA@
2 0.3 UMA_HDMI UMA_H@
3 1.0 Side port SP@
4 JM51 JM@
5 HM52 HM@
6
7
EC SM Bus1 address EC SM Bus2 address
3 3
Device Address HEX Device Address HEX
Smart Battery 0001 011X b 16H ADI ADM1032 (CPU) 1001 100X b 98H SB700 SB700 RS780MN DISPLAY OUTPUT
PX_GPIO0 PX_GPIO1 PX_GPIO2
SB-Temp Sensor 9CH Function Description dGPU_Reset dGPU_PWR_Enable PX Mode Switch
IGP only mode X X X
PowerXpress mode H : Enable H : Enable L : iGPU(DC) / H : dGPU(AC) LVDS / CRT
SB710 SB700
SM Bus 0 address SM Bus 1 address KB926
PX_GPIO1 PX_GPIO2 PX_+3VS PX_+1.8VS PX_+VGA_CORE PX_GPIO2_NB
Device Address HEX Device Address Function Description Enable +1.1VS_PX PX MODE SWITCH Enable +3VS_DELAY Enable +1.8VS_PX Enable +VGA_CORE Trigger from SB
New card IGP only mode X X X X X X
Clock Generator 1101 001Xb D2
(SILEGO SLG8SP626) PowerXpress mode H : Enable Reserved H : Enable H : Enable H : Enable Reserved
DDR DIMM1 1001 000Xb 90
KB926
DDR DIMM2 1001 010Xb 94
PX_GPIO1_SB
Mini card
Function Description Trigger from SB to Enable (PX_GPIO1/PX_+3VS/PX_+1.8VS/PX_+VGA_CORE)
[email protected]
4 4
IGP only mode X
PowerXpress mode H : Enable
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5401
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401728
Date: Monday, May 04, 2009 Sheet 3 of 49
A B C D E
5 4 3 2 1
D H_CADIP[0..15] H_CADOP[0..15] D
<10> H_CADIP[0..15] H_CADOP[0..15] <10>
H_CADIN[0..15] H_CADON[0..15]
<10> H_CADIN[0..15] H_CADON[0..15] <10>
+1.2V_HT
JCPU1A
D4 VLDT_A3 VLDT_B3 AE5 1 2
VLDT=500mA D3 AE4 C904 4.7U_0805_10V4Z
VLDT_A2 VLDT_B2
D2 VLDT_A1 VLDT_B1 AE3
D1 VLDT_A0 VLDT_B0 AE2
H_CADIP15 N5 T4 H_CADOP15
H_CADIN15 L0_CADIN_H15 L0_CADOUT_H15 H_CADON15
P5 L0_CADIN_L15 L0_CADOUT_L15 T3
H_CADIP14 M3 V5 H_CADOP14
H_CADIN14 L0_CADIN_H14 L0_CADOUT_H14 H_CADON14
M4 U5
H_CADIP13
H_CADIN13
L5
L0_CADIN_L14
L0_CADIN_H13
L0_CADOUT_L14
L0_CADOUT_H13 V4 H_CADOP13
H_CADON13
FAN1 Conn
M5 L0_CADIN_L13 L0_CADOUT_L13 V3
H_CADIP12 K3 Y5 H_CADOP12
H_CADIN12 L0_CADIN_H12 L0_CADOUT_H12 H_CADON12 +5VS
K4 L0_CADIN_L12 L0_CADOUT_L12 W5
H_CADIP11 H3 AB5 H_CADOP11 C108 10U_0805_10V4Z +5VS
H_CADIN11 L0_CADIN_H11 L0_CADOUT_H11 H_CADON11
H4 L0_CADIN_L11 L0_CADOUT_L11 AA5 1 2
H_CADIP10 G5 AB4 H_CADOP10
L0_CADIN_H10 L0_CADOUT_H10
1
H_CADIN10 H5 AB3 H_CADON10
H_CADIP9 L0_CADIN_L10 L0_CADOUT_L10 H_CADOP9 U10 D11
F3 L0_CADIN_H9 L0_CADOUT_H9 AD5
H_CADIN9 F4 AC5 H_CADON9 1 8 1SS355_SOD323-2
H_CADIP8 L0_CADIN_L9 L0_CADOUT_L9 H_CADOP8 EN GND @
E5 L0_CADIN_H8 L0_CADOUT_H8 AD4 2 VIN GND 7
H_CADIN8 F5 AD3 H_CADON8 +VCC_FAN1 3 6
2
C H_CADIP7 L0_CADIN_L8 L0_CADOUT_L8 H_CADOP7 VOUT GND D12 C
N3 L0_CADIN_H7 L0_CADOUT_H7 T1 <33> EN_DFAN1 2 1 4 VSET GND 5
H_CADIN7 N2 R1 H_CADON7 R62 300_0402_5% 1 2
H_CADIP6 L0_CADIN_L7 L0_CADOUT_L7 H_CADOP6 APL5607KI-TRG_SO8
L1 L0_CADIN_H6 L0_CADOUT_H6 U2 1
H_CADIN6 M1 U3 H_CADON6 @ BAS16_SOT23-3
H_CADIP5 L0_CADIN_L6 L0_CADOUT_L6 H_CADOP5 C105 C121
L3 L0_CADIN_H5 L0_CADOUT_H5 V1
H_CADIN5 L2 U1 H_CADON5 0.1U_0402_16V4Z 10U_0805_10V4Z
H_CADIP4 L0_CADIN_L5 L0_CADOUT_L5 H_CADOP4 2
J1 L0_CADIN_H4 L0_CADOUT_H4 W2 1 2
H_CADIN4 K1 W3 H_CADON4
H_CADIP3 L0_CADIN_L4 L0_CADOUT_L4 H_CADOP3 +3VS C119
G1 L0_CADIN_H3 L0_CADOUT_H3 AA2
H_CADIN3 H1 AA3 H_CADON3 1000P_0402_50V7K
H_CADIP2 L0_CADIN_L3 L0_CADOUT_L3 H_CADOP2
G3 L0_CADIN_H2 L0_CADOUT_H2 AB1 1 2
1
H_CADIN2 G2 AA1 H_CADON2
H_CADIP1 L0_CADIN_L2 L0_CADOUT_L2 H_CADOP1 R298
E1 L0_CADIN_H1 L0_CADOUT_H1 AC2
H_CADIN1 F1 AC3 H_CADON1 10K_0402_5%
H_CADIP0 L0_CADIN_L1 L0_CADOUT_L1 H_CADOP0
H_CADIN0
E3 L0_CADIN_H0 L0_CADOUT_H0 AD1
H_CADON0
40mil JP13
E2 AC1
2
L0_CADIN_L0 L0_CADOUT_L0 +VCC_FAN1
1
<10> H_CLKIP1 J5 L0_CLKIN_H1 L0_CLKOUT_H1 Y4 H_CLKOP1 <10> <33> FAN_SPEED1 2
<10> H_CLKIN1 K5 L0_CLKIN_L1 L0_CLKOUT_L1 Y3 H_CLKON1 <10> 3
<10> H_CLKIP0 J3 L0_CLKIN_H0 L0_CLKOUT_H0 Y1 H_CLKOP0 <10> 1
J2 W1 C670 ACES_85205-03001
<10> H_CLKIN0 L0_CLKIN_L0 L0_CLKOUT_L0 H_CLKON0 <10>
1000P_0402_50V7K CONN@
H_CTLIP1_R P3 H_CTLOP1_R 2
<10> H_CTLIP1 1 2 L0_CTLIN_H1 L0_CTLOUT_H1 T5 1 2 H_CTLOP1 <10>
R225
1 0_0402_5%
2 H_CTLIN1_R P4 R5 H_CTLON1_R R227
1 0_0402_5%
2
<10> H_CTLIN1 L0_CTLIN_L1 L0_CTLOUT_L1 H_CTLON1 <10>
R226 0_0402_5% R250 0_0402_5%
H_CTLIP0 N1 R2 H_CTLOP0
<10> H_CTLIP0 L0_CTLIN_H0 L0_CTLOUT_H0 H_CTLOP0 <10>
H_CTLIN0 P1 R3 H_CTLON0
<10> H_CTLIN0 L0_CTLIN_L0 L0_CTLOUT_L0 H_CTLON0 <10>
FOX_PZ63823-284S-41F
CONN@
Athlon 64 S1
B Processor Socket B
+1.2V_HT
R829 2 1 51_0402_1%
@ H_CTLIP1_R
R814 2 1 51_0402_1%
@ H_CTLIN1_R
AMD : 49.9 1%
ATI : 51 1%
+1.2V_HT
250 mil
VLDT CAP.
1 1 1 1 1 1
C910 C911 C912 C913 C914 C915
4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J
2 2 2 2 2 2
Near CPU Socket
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/5/18 Deciphered Date 2009/06/11 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5401
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401728 A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 04, 2009 Sheet 4 of 49
5 4 3 2 1
A B C D E
Processor DDR2 Memory Interface
<9> DDR_B_D[63..0]
JCPU1C
DDR_A_D[63..0] <8>
+1.8V DDR_B_D63 AD11 AA12 DDR_A_D63
4 DDR_B_D62 MB_DATA63 MA_DATA63 DDR_A_D62 4
AF11 MB_DATA62 MA_DATA62 AB12
DDR_B_D61 AF14 AA14 DDR_A_D61
MB_DATA61 MA_DATA61
2
DDR_B_D60 AE14 AB14 DDR_A_D60
R801 DDR_B_D59 MB_DATA60 MA_DATA60 DDR_A_D59
Y11 MB_DATA59 MA_DATA59 W11
1K_0402_1% DDR_B_D58 AB11 Y12 DDR_A_D58
+CPU_M_VREF DDR_B_D57 MB_DATA58 MA_DATA58 DDR_A_D57
AC12 MB_DATA57 MA_DATA57 AD13
DDR_B_D56 AF13 AB13 DDR_A_D56
1
DDR_B_D55 MB_DATA56 MA_DATA56 DDR_A_D55
AF15 MB_DATA55 MA_DATA55 AD15
1000P_0402_50V7K
0.1U_0402_16V4Z
DDR_B_D54 AF16 AB15 DDR_A_D54
MB_DATA54 MA_DATA54
2
1 1 DDR_B_D53 AC18 AB17 DDR_A_D53
MB_DATA53 MA_DATA53
C916
C917
R800 DDR_B_D52 AF19 Y17 DDR_A_D52
1K_0402_1% DDR_B_D51 MB_DATA52 MA_DATA52 DDR_A_D51