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5 4 3 2 1
Project code: 91.4HX01.001
SYSTEM DC/DC
PCB P/N : 48.4HX01.0SB RT8223 34
REVISION : SB INPUTS OUTPUTS
Slot 0 DDRIII Channel A 5V_S5(6A)
DDRIII 800 18 DCBATOUT
Clock Generator AMD 3D3V_S5(6A)
ICS9LPRS480BKLFT
3
Slot 1 ASB2 CPU PCB STACKUP SYSTEM DC/DC
D
DDRIII 800 DDRIII Channel B RT8209E 35 D
17 4,5,6,7
TOP
INPUTS OUTPUTS
DCBATOUT 1D5V_S3(7.5A)
OUT
HyperTransport GND
IN
LINK0
16x16 S SYSTEM DC/DC
RT8209E 36
RS880M S INPUTS OUTPUTS
CRT GND
RGB CRT DCBATOUT 1D1V_S0(11A)
HyperTransport LINK0 CPU I/F 20
BOTTOM RT9026 35
10 DX10 IGP
LVDS/TVOUT/TMDS LVDS 2CH
LCD 5V_S5 DDR_VREF_S3
WXGA+ 19
DISPLAY PORT X2
Giga LAN RT9025 37
Side Port Memory
RJ45 MDI PCIE Digital Display HDMI
AR8151 1 X16 PCIE I/F 21 3D3V_S5 1D1V_S5
CONN 24
23
C
1 X4 PCIE I/F WITH SB C
RT9025 37
6 X1 PCIE I/F
PCIE 8,9,10,11 3D3V_S5 CPU_VDDR
WEBCAM 19
A-Link
4X4
Mini-Card PCIE+USB 2.0 USB 2.0 BLUETOOTH
31
WLAN & 3G SB800 CHARGER
26 ISL88731A
USB 2.0
38
USB2.0 (14)+1.1(2)
USB x 3 31
INPUTS OUTPUTS
SATA III (6 PORTS)
MIC IN HD AUDIO 4 X1 PCIE GEN2 I/F CHG_PWR
CODEC AZALIA Card Reader 18V 6.0A
INT. CLK GEN. SD/MMC
INT MIC ALC271 22 RTS 5138 DCBATOUT
GB MAC
25
MS/MS Pro/xD
25
UP+5V
HW MONITOR 5V 100mA
B PCI/PCI BDGE CPU DC/DC B
INT. RTC SATA SATA HDD 31 ISL6265AHR 33
LINE OUT EC INPUTS OUTPUTS
HD AUDIO VCC_CORE_S0_0
LPC I/F 0~1.55V 18A
SPI I/F VCC_CORE_S0_1
DCBATOUT
2CH SPEAKER ACPI 1.1 12,13,14,15,16 0~1.55V 18A
VDDNB
0~1.55V 18A
LPC Bus LPC debug 30
KBC
SPI
NPCE781B
29
A
CPU FAN SJV10-NL
A
SMB PS/2 KBC Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Thermal
Flash ROM Touch Int. Block Diagram
Sensor Size Document Number Rev
2MB 30 PAD KB29 A3
[email protected] G792 28 31
SJV10-NL -1
Date: Tuesday, January 05, 2010 Sheet 1 of 42
5 4 3 2 1
5 4 3 2 1
Power on Sequence required:
SB800:
1, +3.3VDUAL ramp before +1.1VDUAL >1 mS >1 mS
2, +3.3V ramp before +1.8v CPU_LDT_RST#
3, +1.8V ramp before +1.1v (SB TO CPU)
4, +3.3v ramp before +1.1v
5, +3.3VALW_R ramping down time > 300us A_RST#/PCI_RST#
(SB OUTPUT)
6, 50uS <= All power rails except +3.3VALW_R <= 40mS
7, 100uS <= +3.3VALW_R <= 40mS CPU_PWROK
(SB TO CPU) >1 mS Req.
RS880: CPU_CLKP/N running
1, 0 <(+3.3V) - (+1.8v) < 2.1 (CPU INPUT CLK)
D D
2, +1.8V ramp before +1.1v >1 mS Req.
3. +1.1V ramp before VCC_NB -22 mS-500ms for extenal gen. NBPWRGD,
For SB800, SB gen NBPWRGD
HT_REFCLKP/N running
(NB INPUT CLK)
>1 mS Req. VCC_NB(all NB power) valid before NB_PWRGD.
SB OUTPUT NB_PWRGD
NB_PWRGD_IN
SLP_S3# 1V1DUAL_PWRGD
SB INPUT SB_PWRGD 1)+1.5V SWITCH TO +1.5VDUAL 2)LASSO_PWRON 3)LPCPD# for TPM 4) TO SB&KBC SYS_RST# 1V5_PWRGD/DNI
+1.2V_PWRGD KBC_GPIO77/DNI
+1.2V_PWRGD
RC=~22ms VCC_NB should not ramp before 1.1v
VCC_NB
RC=~4.7ms
VLDT
GROUP B
VRM_PWRGD AND 1V8_PWRGD
+1.1V
VRM_PWRGD
RC=0
CPU_VDDR
RC=0
CPU_VDD_RUN
RC=0
CPU_VDDNB_RUN
VDDA_PWRGD
GROUP A
C C
+2.5V_LDO
(CPU_VDDA_2.5_RUN)
+1.5V
1V8_PWRGD
RC=0
+1.8V
+5V/+3.3V
RUN_EN_HIGH
RUN_EN_LOW
VDD_BOOST_LOW
to S3
SLP_S3#
VDRAM_PWRGD
CPU MEM CTL &
DDR3 SODIMM PWRS MEM_VTT VTT only will be shut down in S3 mode, and VTT for DDR3 SODIMM only.
MEM_VREF
CPU_VDDIO_SUS
SLP_S5#
Power button from EC to SB
PWR_BTN#_EC
20mS
CPU_THM/SB/SB_SCL1/2 delay +3.3VDUAL RC=~40ms
SB_KB/SPI/LPC ROM PWRS RSMRST#
When IMC, it's same signals for PBT.
V3V5DUAL_PWRGD
B B
1V1DUAL_PWRGD
SYSTEM_DUAL_PG
+5VDUAL/+3.3VDUAL/+1.5VDUAL/+1.1VDUAL
DUAL RAILS When IMC, always on at all time( always PWR)
When IMC,always high
per shorting JU3000 HDR VDD_DUAL_EN
VDD_DUAL_EN_EC
Power button pressed
PWR_BTN#_HW
PWR_BTN#_SB
KBC is ready
AC not present scenario = LOW AC present= high
AC_OK
(ACIN detect)
KBC is powered by
A_VBAT & +3.3VALW +5VALW/+3.3VALW stays active if AC present
LDO:5.4V stays active if AC present
(from DCIN)
USB Battery inserted/AC IN
+VIN/+12V_HD stays active if AC present
Pair Device A_VBAT
0 USB1(HS)
1 MINICARD1
2 NC
3 NC
4 Cardreader
A A
5 USB2
6 USB3
7 Blue Tooth
PCIE Routing 8 NC
SJV10-NL
LANE1 LAN 9 WECAM Wistron Corporation
10 NC 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
LANE2 MiniCard1 11 MINIC2(3G sim)
Title
LANE3 MiniCard2 12 MINIC2(3G) Table of Content
13 NC Size Document Number Rev
[email protected] A2
SJV10-NL -1
Date: Tuesday, January 05, 2010 Sheet 2 of 42
5 4 3 2 1
5 4 3 2 1
3D3V_S0
3D3V_CLK_VDD
R1
1 2 3D3V_S0
MGB1005G601EBP-GP R2
1
1
1
1
1
1
1
C4 C5 C6 C7 C8 C9 1 2 3D3V_48MPW R_S0
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C1
-1 Change R1 to bead (68.00373.001)
1
1
2R3J-GP C10 C11
SC10U10V5KX-2GP
2
2
2
2
2
2
2
DY SC1U10V2KX-1GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
2
2
3000mA.80ohm
D D
3D3V_S0
R3
1 2
0R3J-0-U-GP SB X1 change to smaller
DY package(82.30005.A51) SC12P50V2JN-3GP
1D1V_S0 1D1V_CLK_VDDIO R5 C12
R4 1 DY 2 1 2
1 2
MGB1005G601EBP-GP 10MR2J-L-GP
1
1
1
1
1
1
C13 C16 C17 C18 C19 3D3V_CLK_VDD X1 -1 Change C12,C20 to 12pF.
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
-1 Change R4 to bead X-14D31818M-50GP
U1 82.30005.A51
(68.00373.001)
2
2
2
2
2
1D1V_CLK_VDDIO 2nd = 82.30005.C51
2
26 61 GEN_XTAL_IN SC12P50V2JN-3GP
VDDATIG X1 GEN_XTAL_OUT
25 VDDATIG_IO X2 62 1 2
48 SRN0J-10-GP-U C20
VDDCPU CLK_SMBCLK
47 VDDCPU_IO SMBCLK 2 4 1 SMBC0_SB 13,17,18
3 CLK_SMBDAT 3 2
SMBDAT SMBD0_SB 13,17,18
16 VDDSRC
17 RN38 3D3V_S0
VDDSRC_IO RN1
-1 Change R7 to bead 11 VDDSRC_IO ATIG0T_LPRS 30 CLK_NB_GFX 9
3D3V_CLK_VDD 29 8 1 CLKG_PD#
(68.00373.001) 35
ATIG0C_LPRS
28
CLK_NB_GFX# 9
7 2 W LAN_CLKREQ#
R7 VDDSB_SRC ATIG1T_LPRS W LAN2_CLKREQ#
34 VDDSB_SRC_IO ATIG1C_LPRS 27 6 3