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1 1




Compal Confidential
NIMUA/UB
2


Schematics Document 2




Arrandale
with Intel IBEX PEAK-M core logic
3 3



REV:0.3




4 4




Security Classification Compal Secret Data Compal Electronics,Ltd.
Issued Date 2010/01/13 Deciphered Date 2011/01/13 Title
Cover Sheet
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5941P
Date: Thursday, April 08, 2010 Sheet 1 of 50
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Compal confidential
File Name : CR BD:
Thermal-sensor POWER BD:
ZZZ
LS-5941P LS-5944P
EMC1403 page38
POWER BT
14.1W_PCB_LA5941P VRAM 64*16 Intel
DDR3*4 SW BD: Body-Detect BD:
1 DAZ0D500102
page20 PCI-E X16 Arrandale Clock Generator LS-5942P 1



(UMA/SG) LS-5947P
SLG8LV597VTR NOVO BT
page12

NVidia N11M-LP1 Socket-rPGA989 Finger Print BD:
page19~23
37.5mm*37.5mm DDR3-SO-DIMM X2 LS-5943P
BANK 0, 1, 2, 3 U-pek TCS5D
page5~9 page 10,11
level shift IC Dual Channel
HDMI ASM1442 UP TO 8G
CONN page25 100MHz FDI *8 DMI *4 DDR3-800(1.5V)
page24 2.7GT/s DDR3-1067(1.5V) 2Channel Speaker
page33
CRT Connector SW1
page26
Intel Ibex Peak M
2 DMIC_Int 2


LVDS Audio Codec page33
SW2 AZALIA ALC259
Connector page27
FCBGA 951 page33 Audio Jack CONN.
PCI Express page37

6*PCI-E BUS 25mm*25mm
Mini card Slot 2 14*USB2.0 CMOS Camera
page28
page27


USB(WLAN) SPI page 13~18
6*SATA serial BlueTooth CONN
page37



PCI Express SPI ROM USB1 CONN. page37
LPC BUS
Mini card Slot 3 BIOS+ME
3
page28 page13 USB2 CONN page37 3




Atheros 8131/32
EC USB3 CONN
ENE KB926E0 page37
SIM Card 10/100/1G LAN page34
page29
page28 USB(WWAN)
WWAN/3G page28
Card Reader
RJ45 CONN Touch Pad Int.KBD CONN
page30 page35 page38
page35
AD ESATA AND USB CONN
SPI ROM
G-sensor EC page37

page38 page36
CAP SENSOR BD: USB/JACK BD:
LS-5945P SATA HDD CONN
LS-5946P page32
4

USER/SG USB PORT1,2,3 4




MUTE HP JACK SSD Mini card Slot 1
page28
Power Saving MIC JACK
BUTTON & LED KILL SW Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/01/13 Deciphered Date 2011/01/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MB Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5941P
Date: Thursday, April 08, 2010 Sheet 2 of 50
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A B C D E


DDR3 Voltage Rails
SMBUS Control Table
+5VS N11x
WLAN Thermal Cap sensor ALS PCH
+3VS SOURCE RAM BATT KB926 SODIMM CLK CHIP WWAN EMC1403
Sensor board
+1.5VS M2
SMB_EC_CK1
power +VCCP
SMB_EC_DA1
KB926 X V
+3VALW
X X X X X X X X X
plane +CPU_CORE +3VALW
SMB_EC_CK2
1
+5VALW +1.5V
+VGA_CORE
SMB_EC_DA2
KB926 X X V X X X V V X V V 1
+3VALW +3VALW +3VS +3VS +3VS +3VALW
+1.8VS
+B SMBCLK
+3VALW
+0.75VS
SMBDATA
PCH V X X V V X X X X X X
+3VALW +3VALW +3VS +3VS
+1.05VS
SML0CLK
State For SG SML0DATA
PCH
+3VALW
X X X X X X X X X X X
+3VS_DELAY SML1CLK
+1.8VS_VGA SML1DATA
PCH
+3VALW
X X V X X X X X X X X
+1.5VS_VGA




S0
O O O O PCH, I2C / SMBUS ADDRESSING EC, I2C / SMBUS ADDRESSING

DEVICE HEX ADDRESS DEVICE HEX ADDRESS
S3
O O O X DDR SO-DIMM 0 A0 10100000 PCH 96/98,R/W 1001011X 1001100X
2
DDR SO-DIMM 1 A4 10100100 EMC1403 Thermal sensor 9A 1001101X 2
S5 S4/AC
O O X X CLOCK GENERATOR (EXT.) D2 11010010 N-vidia Thermal sensor 9E 1001111X
ALS 70/72,R/W 0111000X 0111001X
S5 S4/ Battery only
O X X X
S5 S4/AC & Battery
don't exist X X X X

@ FUNCTION PCIE PORT LIST USB PORT LIST
PVT NON-USE
[email protected] (45 BOM) PORT DEVICE PORT DEVICE
[email protected] 10/100 LAN 1 NEW CARD 0 USB 1
[email protected] GIGA LAN 2 WLAN 1 USB/ESATA
[email protected] FOR UMA HDMI components 3 LAN 2 CMOS
[email protected] FOR HDMI components 4 3G 3 USB 2
3
[email protected] 3G(WWAN) function 5 4 3
[email protected] (X76 BOM) 6 5 CARD READER
[email protected] ESATA function 7 6 X HM55 disabled
[email protected] Camera function 8 7 X HM55 disabled
[email protected] SSD w/ miniPCIE socket 8 WIRELESS
[email protected] FOR 10M CHIP 9 USB 3
[email protected] FOR 11M CHIP 10 FigerPrinter
[email protected] UMA only (Arranddale) SATA PORT LIST
11 BT
[email protected] DIS only (Arranddale) PORT DEVICE 12
[email protected] FOR NVIDIA PART 13 3G
[email protected] FOR SWITCHABLE 0 HDD
[email protected] SWITCHABLE or UMA only 1 SSD
[email protected] SWITCHABLE or DIS only 2,3 HM55 disabled
4 E-SATA
SKU 5

Arrandale(dGPU) [email protected] / [email protected] for EVT
4 4
DIS only
Arrandale(iGPU) [email protected] / [email protected] for EVT
UMA only
Arrandale(iGPU+dGPU) [email protected]
SWITCHABLE
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/01/13 Deciphered Date 2011/01/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MB Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5941P
Date: Thursday, April 08, 2010 Sheet 3 of 50
A B C D E
A B C D E



VGA and DDR3 Voltage Rails (N11M GPIO)
GPIO I/O ACTIVE Function Description

GPIO0 N/A N/A

GPIO1 IN - HDMI_DETECT_VGA

GPIO2 OUT H NV_INVTPWM
1 1

GPIO3 OUT H VGA_ENVDD_R The ramp time for any rail must be more than 40us
Power Sequence
GPIO4 OUT H VGA_ENABLT

GPIO5 OUT - GPU VID0

GPIO6 OUT - GPU VID1 (+3VS) VDD33
GPIO7 OUT -
PEX_VDD can ramp up any time
GPIO8 I/O L
(1.05VS)PEX_VDD
GPIO9 OUT L
tNVVDD
GPIO10 OUT

GPIO11 I/O L (+VGA_CORE) NVVDD
GPIO12 IN - tNV-IFPAB_IOVDD

2
GPIO13 OUT - (1.8VS)IFPAB_IOVDD 2


GPIO14 OUT -
tNV-FBVDDQ
GPIO15 IN -
(1.5VS) FBVDDQ
GPIO16 OUT -

GPIO17 IN -

GPIO18 IN -

GPIO19 IN -

GPIO20 IN -

GPIO21 IN -

GPIO22 IN -

GPIO23 I/O
3 3




GPIO5 GPIO6
Device ID GPU_VID0 GPU_VID1 VGA_CORE P-State
0 0 0.8V Deep P12
N11M-LP1
(40nm) 0x0A6E 0 1 0.85V P8
1 1 0.86V P0




4 4




Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/01/13 Deciphered Date 2011/01/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5941P
Date: Thursday, April 08, 2010 Sheet 4 of 50
A B C D E
5 4 3 2 1




DDR3 Compensation Signals


SM_RCOMP0 1 2
R567 100_0402_1%
SM_RCOMP1 1 2
R566 24.9_0402_1%
SM_RCOMP2 1 2
R565 130_0402_1%

Layout Note:Please these
D

Layout rule 10mil width trace
length < 0.5", spacing 20mil
resistors near Processor D



JCPU1B
20_0402_1% 1 R560 2COMP3 AT23 COMP3 CLK_CPU_BCLK
BCLK A16 CLK_CPU_BCLK 16 +VCCP




MISC
MISC
20_0402_1% 1 R558 2COMP2 AT24 COMP2 BCLK# B16 CLK_CPU_BCLK#
CLK_CPU_BCLK# 16
49.9_0402_1% 1 R548 2COMP1 CLK_CPU_ITP PM_EXTTS#0




CLOCKS
G16 COMP1 BCLK_ITP AR30 T17 PAD 1 2
AT30 CLK_CPU_ITP# T18 PAD R561 10K_0402_5%
49.9_0402_1% BCLK_ITP#
1 R557 2COMP0 AT26 COMP0
PM_EXTTS#1 1 2
E16 CLK_EXP R562 10K_0402_5%
PEG_CLK CLK_EXP 14
D16 CLK_EXP#
PEG_CLK# CLK_EXP# 14
TP_SKTOCC# AH24 SKTOCC#
DPLL_REF_SSCLK A18
DPLL_REF_SSCLK# A17
+VCCP 2 1 H_CATERR# AK14 XDP_PREQ# R136 1 @ 2 51_0402_1%
CATERR#




THERMAL
THERMAL
49.9_0402_1% R163
XDP_TMS R138 1 @ 2 51_0402_1%

16 H_PECI
R564
1
0_0402_5%
2 H_PECI_ISO AT15 PECI
SM_DRAMRST# F6 SM_DRAMRST# 3 only for Arrandale
XDP_TDI R556 1 @ 2 51_0402_1%
AL1 SM_RCOMP0 without EDP
SM_RCOMP[0]
+VCCP 2 R569 1 68_0402_5% SM_RCOMP[1] AM1 SM_RCOMP1 XDP_TDO R134 1 2 51_0402_5%
AN1 SM_RCOMP2
H_PROCHOT# SM_RCOMP[2]
34,48 H_PROCHOT# AN26 PROCHOT#
AN15 PM_EXTTS#0 XDP_TCK R57 1 @ 2 51_0402_1%
PM_EXT_TS#[0]




DDR3
MISC
AP15 PM_EXTTS#1 1 2
PM_EXT_TS#[1] PM_EXTTS#1_R 10,11
R563 0_0402_5% XDP_TRST# R133 1 2 51_0402_5%
H_THERMTRIP# AK15
16 H_THERMTRIP# THERMTRIP#

AT28 XDP_PRDY# T19 PAD R137
C PRDY# XDP_PREQ# XDP_DBRESET# @ C
PREQ# AP27 1 2 1K_0402_5% +3VS
SVT
@ AN28 XDP_TCK
TCK
1 H_CPURST#_R XDP_TMS
+VCCP 2 AP26 RESET_OBS# TMS AP28
CHECK INTEL DOCUMENT #385422




PWR MANAGEMENT
PWR MANAGEMENT
68_0402_5% R135 AT27 XDP_TRST#
TRST#
Debug Port Design Guide Rev1.3




JTAG & BPM
15 H_PM_SYNC 1 R187 2 H_PM_SYNC_R AL15 PM_SYNC TDI AT29 XDP_TDI
0_0402_5% AR27 XDP_TDO
TDO
TDI_M AR29
1 R190 2 VCCPWRGOOD_1 AN14 VCCPWRGOOD_1 TDO_M AP29 R555 2 1 0_0402_5%
0_0402_5%
AN25 XDP_DBRESET#
DBR#
16 H_CPUPWRGD 1 R139 2 VCCPWRGOOD_0 AN27 VCCPWRGOOD_0
0_0402_5%
AJ22 XDP_BPM#0
BPM#[0]
15 PM_DRAM_PWRGD 1 R191 2 VDDPWRGOOD_R AK13 SM_DRAMPWROK BPM#[1] AK22 XDP_BPM#1
0_0402_5% AK24 XDP_BPM#2