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1 2 3 4 5 6
J8
1
6
2
UART 7
R3
D 3 D
1
3
8
4 CAN
9 JP21
5
U6 U2
2
C32 1 16 VCC UART1 1 8
C1+ VCC D Rs
VCC C33 2 15 CAN_TX 1JP6 4 2 7
V+ GND GND CANH
3 14 CAN_RX 2JP7 3 V3.3 3 6
C1- T1OUT Vcc CANL
C30 4 13 4 5
C2+ R1IN R Vref
5 12 JP12 U1RX U1_RX
C2- R1OUT
C25 6 11 U1_TX VP230 J2
V- T1IN JP2
7 10 U2_TX
T2OUT T2IN 1
8 9 JP11 U0RX U2_RX R1 121
R2IN R2OUT J3 2
3
MAX3232 1
6 CAN
2
7
3
8
4
9
5
C C
U8 UART2
C38 1 16 VCC
C1+ VCC
VCC C40 2 15
V+ GND
3 14
C1- T1OUT
C36 4 13
C2+ R1IN
5 12 JP13 U0RX U0_RX
C2- R1OUT
C35 6 11 U0_TX
7
V- T1IN
T2OUT T2IN
10 U0_RTS LCD
8 9 JP16 U0CTS U0_CTS J9
R2IN R2OUT
1
MAX3232 6 J6
2
7 ADUIO V5
1
2
3 R12 1K 3
8 P0.18
J5 4
4 P0.17
5
9 P0.16
6
5 P2.10
JP3 7
P2.11
R4 8
UART0 T2_OC2 P2.12
9
C1 1K2 Audio P2.13
10
P2.14
33n 11
B P2.15 B
12
P2.16
JTAG P2.17
13
14
V5 R21 10R
15
16
J7
17
VCC
1 2 18
RESET JP15 NJTRST
3 4 19
JTDI
5 6 20
JTMS
JP19 7 8
JTCK LCD1602
9 10
RTCK RTCK
11 12
JTDO
13 14
RESET
15 16
17 18
19 20
JTAG20
16
15
14
13
12
11
10
9
RS1
10KA9
A A
VCC
1
2
3
4
5
6
7
8
Title
Size Number Revision
B
Date: 3-Nov-2006 Sheet of
File: E:\EV750\EV750.DDB Drawn By:
1 2 3 4 5 6
B
C
A
D
1
1
2
2
VCC
3
1
BZ1
JP17
+
2
V5
JTDI
D1
JTCK
JTMS
JTDO
RTCK
R29
U1_TX
U1_RX
NJTRST
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
U5
P2.00
P2.01
P2.02
P0.28
P0.29
P0.30
P0.31
P0.01
P0.02
P1.12
TEST
Q2
VSS_IO
NJTRST
STR750
S8050
JTDI / P1.16
JTCK / P1.18
JTDO / P1.17
JTMS / P1.19
RTCK / P0.13
BOOT0/P0.00
VCC 1 U0_CTS 26 100 JP14 R28
UART0_CTS / P0.12 P0.03 / TIM2_TI1 / ADC_IN1
2 U0_TX 27 99 VCC
TIM2_OC1/ P2.04
UART0_TX / P0.11 VDD_IO
3
3
UART1_TX / P0.21
UART1_RX / P0.20
3 U0_RX 28 98
UART1_CTS / P0.22
UART1_RTS / P2.03
UART1_RTS / P0.23
UART0_RX / P0.10 VSS_IO
R27
I2C_SDA 29 97
I2C_SDA / P0.09 VSS18
I2C_SCL 30 96
I2C_SCL / P0.08 V18
BOOT1
31 95
C28
P2.19 P1.00 / TIM0_OC2
32 94
P2.18 P1.01 / TIM0_TI2
P1
P2.17 33 93 VCC
UART2_RTS / P2.17 P1.13 / ADC_IN14 1
20K
VCC
U0_RTS 34 92
UART0_RTS P1.11 P1.14/ ADC_IN15 2
35 91
UART2_RTS / P0.27 P1.04 / PWM3N / ADC_IN9 3
JP20
36 90
UART2_CTS / P0.26 P1.05 / PWM3
I2
STR750
U2_TX 37 89
UART2_TX / P0.25 P1.06 / PWM2N/ ADC_IN10
U2_RX 38 88 P1.07
UART2_RX / P0.24 P1.07 / PWM2
39 87 P1.08
USB_CK / P0.19 P1.08 / PWM1N/ ADC_IN11
P0.18 40 86 P2.05
SSP1_MOSI / P0.18 P2.05 / PWM3N
P0.17 41 85 P2.06
C20 SSP1_MISO / P0.17 P2.06 / PWM3
P0.16 42 84 P2.07
SSP1_SCLK / P0.16 P2.07 / PWM2N
P2.16 43 83 P2.08
P2.16 P2.08 / PWM2
VCC 44 82 P2.09
E7 VDD_IO P2.09 / PWM1N
45 81 P1.09
VDDA_PLL P1.09 / PWM1
46 80 P1.10
XT2 P1.10 / PWM_EMERGENCY
47 79 SSP0_NSS
XT1 P0.04 / SMI_CS0 / SSP0_NSS
48 78 SSP0_SCLK
22p
C19
VSS_IO P0.05 / SSP0_SCLK / SMI_CK
49 77 SSP0_MISO
VSSA_PLL P0.06 / SMI_DIN / SSP0_MISO
P2.15 50 76 SSP0_MOSI
1M
R16
R17
XT2
P2.15 P0.07 / SMI_DOUT / SSP0_MOSI
4MHz
4
4
2
22p
NRSTOUT
P1.03 / TIM2_TI2
NRSTIN
VDD_IO
XRTC1
XRTC2
USB_DP
V18REG
P0.15 / CAN_TX
VSS_IO
P1.15 / WKP_STDBY
VDDA_ADC
VSS18
V18BKP
P0.14 / CAN_RX
USB_DN
VSSA_ADC
VSSBKP
VREG_DIS
P2.14
P2.13
P2.12
P2.11
P2.10
P1.02 / TIM2_OC2
C18
JP10
51
52
53
54
56
57
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
3
1
58 JP5
55 C15 1u
VCC
P2.14
P2.13
P2.12
P1.03
P2.11
P2.10
RESET
VCC
T2_OC2
USB_DP
USB_DN
CAN_TX
CAN_RX
R14
JP8
VCC
WKP_STDBY
VREG_DIS
nRESET C5
E6
104
C16
V18
XT1
C14 22pF
C13 22pF
5
5
32768Hz
C12
B
Size
File:
Title
Date:
E5
I1
Number
3-Nov-2006
E:\EV750\EV750.DDB
VCC
Sheet of
Drawn By:
6
6
Revision
B
C
A
D
1 2 3 4 5 6
POWER
D W1 U1 D
LM1117-3V3 2 R6 1K RESET
JP1 RESET
V_USB
J4 V5 3 2 V3.3 3
GND
Vin Vout VCC
3 E4
SE5V6 1
2 C10 E2 E9 C4 C6 C9 GND
1
809S
SSP0_MISO
1
100uF 100uF
SSP0_NSS
DC5V L6 R2
SPI
R11 P1.03
V5 1 JP4
1K
2 VCC